* include/bsp.h: Changed <sh/null.h> to <rtems/devnull.h> to reflect
the movement of this component to libmisc.
* wrapup/Makefile.am: /dev/null driver is no longer in libcpu/sh.
* devnull: New addition. Moved from libcpu/sh.
* devnull/devnull.c, devnull/devnull.h, devnull/.cvsignore,
devnull/Makefile.am: New files.
* Makefile.am, configure.in, wrapup/Makefile.am: Modified to reflect
addition of above.
* clock/clock.c: Use shared clock driver shell.
* console/console.c: Removed. Now use shared polling shell.
* console/console-io.c: New file.
* console/Makefile.am: Correct to use shared polling shell.
* startup/bspstart.c: Remove all fast idle references.
* new_exception_processing/cpu.h, old_exception_processing/cpu.c:
old_exception_processing/cpu.h, Added _CPU_Initialize_vectors().
In particular, spurious vector initialization had to be moved
on old exception processing model.
* clockdrv_shell.c: Added fast idle mode which is enabled by defining
CLOCK_DRIVER_USE_FAST_IDLE.
* console-polled.c: Added console_initialize_hardware() hook.
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Modify to properly dereference _ISR_Vector_table
now that it is dynamically allocated.
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Modify to properly dereference _ISR_Vector_table
now that it is dynamically allocated.
* tx39/vectorisrs/vectorisrs.c: Modified to have default exception
vector handler. This should be in a separate file so the BSP can
easily override it.
* Makefile.am: Added tools subdirectory and removed commented out line.
* configure.in: Added tools subdirectory.
* tools: New subdirectory.
* tools/.cvsignore, tools/Makefile.am, tools/configure.in,
tools/runtest: New files -- based on powerpc/psim.
* clock/clockdrv.c: Guessed new value for clock tick. Need to
add fast idle support.
* include/bsp.h: tm27 support initiated.
* start/start.S: Fixed frame/endframe problems on _sys_exit.
* startup/bspstart.c: Increased Workspace size to 4 MBYTES!
* linkcmds: Increased Workspace size to 4 MBYTES!
* Most tests appear to run correctly!
* cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
Previous code resulting in the interrupted immediately returning
to the caller of the routine it was inside.
* cpu.c: Do not read or write raw interrupt vector table if
we are on a CPU that does not have a %vbr register and the
BSP is configured as having the table in ROM.
* configure.in: Added new directories.
* shared/interrupts/Makefile.am: Added AM_CPPFLAGS to define TX39
when compiling for a TX3904.
* shared/interrupts/maxvectors.c: Corrected conditional logic.
* tx39/Makefile.am: Added vectorisrs.
* tx39/vectorisrs/Makefile.am, tx39/vectorisrs/vectorisrs.c,
* tx39/vectorisrs/.cvsignore: New files. This decodes the
interrupt pending information on the TX3904 and vectors
an interrupt.
* README: Updated. We are now vectoring a clock tick ISR handler.
But RTEMS is not returning from the ISR properly.
* clock/clockdrv.c: Now causes interrupts but has not been calibrated.
* include/bsp.h: Use <libcpu/tx3904.h>
* startup/Makefile.am: Add setvec.c from shared.
* startup/bspstart.c: Initialize the status register (SR) so
no interrupts are masked but global interrupts (SR_IEC) are off.
Added call to install the ISR prologue code.
* wrapup/Makefile.am: Pick up more pieces from libcpu.
* include/rtems/score/isr.h, src/isr.c: Allocate it from the
workspace rather than explicitly declaring it. This allows
the size to be a non-constant from the perspective of score/cpu.
* cpu.c: Removed duplicate declaration for _ISR_Vector_table.
* cpu_asm.S: Removed assembly language to vector ISR handler
on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
longer a constant -- get the real value from libcpu.
* configure.in: Added new directories.
* shared/interrupts/Makefile.am: Added AM_CPPFLAGS to define TX39
when compiling for a TX3904.
* shared/interrupts/maxvectors.c: Corrected conditional logic.
* tx39/Makefile.am: Added vectorisrs.
* tx39/vectorisrs/Makefile.am, tx39/vectorisrs/vectorisrs.c,
* tx39/vectorisrs/.cvsignore: New files. This decodes the
interrupt pending information on the TX3904 and vectors
an interrupt.
* cpu_asm.h: Removed.
* Makefile.am: Remove cpu_asm.h.
* rtems/score/mips64orion.h: Renamed mips.h.
* rtems/score/mips.h: New file, formerly mips64orion.h.
Header rewritten.
(mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
mips_disable_in_interrupt_mask): New macros.
* rtems/score/Makefile.am: Reflect renaming mips64orion.h.
* asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
few defines that were in <cpu_asm.h>.
* cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
MIPS ISA 3 is still in assembly for now.
(_CPU_Thread_Idle_body): Rewrote in C.
* cpu_asm.S: Rewrote file header.
(FRAME,ENDFRAME) now in asm.h.
(_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
(_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
(_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
leaves other bits in SR alone on task switch.
(mips_enable_interrupts,mips_disable_interrupts,
mips_enable_global_interrupts,mips_disable_global_interrupts,
disable_int, enable_int): Removed.
(mips_get_sr): Rewritten as C macro.
(_CPU_Thread_Idle_body): Rewritten in C.
(init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
placed in libcpu.
(exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
to libcpu/mips/shared/interrupts.
(general): Cleaned up comment blocks and #if 0 areas.
* idtcpu.h: Made ifdef report an error.
* iregdef.h: Removed warning.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
number defined by libcpu.
(_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
to access SR.
(_CPU_ISR_Set_level): Rewritten as macro for ISA I.
(_CPU_Context_Initialize): Honor ISR level in task initialization.
(_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
* src/imfs/linearfile.c, src/imfs/imfs_load_tar.c: New files.
* src/imfs/Makefile.am, src/imfs/imfs.h,
src/imfs/imfs_creat.c, src/imfs/imfs_debug.c,
src/imfs/imfs_eval.c, src/imfs/imfs_handlers_memfile.c,
src/imfs/imfs_init.c, src/imfs/imfs_initsupp.c,
src/imfs/imfs_stat.c, src/imfs/miniimfs_init.c: Added "tarfs".
This is not really a tar filesystem. It is a way to load a tar
image into the IMFS but actually leave bulky file contents in the
original tar image. It essentially adds the linear file type and
associated support and a loader routine.
* shared/.cvsignore, shared/Makefile.am,
shared/cache/.cvsignore, shared/cache/Makefile.am,
shared/cache/cache.c, shared/cache/cache_.h,
shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
shared/interrupts/installisrentries.c,
shared/interrupts/isr_entries.S,
shared/interrupts/maxvectors.c, tx39/.cvsignore,
tx39/Makefile.am, tx39/include/.cvsignore,
tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
Moved some pieces of interrupt processing from score/cpu to
libcpu/mips since many interrupt servicing characteristics are
CPU model dependent. This patch addresses the number of interrupt
sources and where the ISR prologues are located. The only way to
currently install the ISR prologues requires that the prologues
be installed into RAM.
