Add a workaround for Cortex-A9 Errata 845369: Under Very Rare Timing
Circumstances Transition into Streaming Mode Might Create Data Corruption.
Update #4115.
In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.
Close#4068.
The register definition for the CP15 PMCR (performance monitor control
register) has the bits for X (export enable) and D (clock divider
enable) backwards. Correct them according to ARMv7-A/R Architecture
Reference Manual, Rev C, Section B4.1.117.
Consequences: On an implementation that starts off with D set at reset,
the clock divider will not be disabled by using RTEMS' definition of the
D bit.
Tested by using the counter on Xilinx Zynq 7020 to measure some atomic
accesses and cache flushing operations.
The system register in use for retrieval of the virtual timer value was
mistakenly copied from the physical timer value retrieval function.
Virtual timer value retrieval should use the same system register as the
virtual timer value setter.
Close#3699.
