Commit Graph

9 Commits

Author SHA1 Message Date
Sebastian Huber
21a36ed19b bsps: Fix .data.rel.ro placement
The .data.rel.ro* linker input section pattern accidentally matches with
writeable data those symbol name starts with "ro".

Close #4701.
2022-08-12 10:10:17 +02:00
Chris Johns
b868d0a722 basp/aarch64: Make the unexpected sections origin address 64bit
Update #4684
2022-07-28 09:04:46 +10:00
Sebastian Huber
5ed0035377 bsps: Sort .noinit* sections
Sort the .noinit* input sections by name first, then by alignment if two
sections have the same name.  This allows the placement of begin/end symbols to
initialize some areas with a special value.

Update #4678.
2022-07-15 10:46:02 +02:00
Sebastian Huber
96221e40dd bsps/aarch64: Support .noinit linker section 2021-12-13 07:32:58 +01:00
Kinsey Moore
6bfbfb5a3d bsps/aarch64: Resolve usage of SUBALIGN()
Remove usage of SUBALIGN() in aarch64 linkcmds which works around a
difference in behavior on AArch64 platforms. This is no longer necessary
since alignment is now enforced explicitly.

Closes #4178.
2021-03-05 08:43:15 -06:00
Sebastian Huber
9eb9813dc1 bsps: Add missing DWARF 5 sections
Sort alphabetically.
2021-01-26 15:29:36 +01:00
Sebastian Huber
33c12d5f92 bsps: Support DWARF 5 sections
GCC 11 uses DWARF 5 by default.
2021-01-25 12:56:00 +01:00
Kinsey Moore
1cbe5773ab spec/aarch64: Only apply SUBALIGN(4) to ILP32
The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds
was previously present on LP64 builds and causes no issues within RTEMS,
but causes relocation/alignment issues when building libbsd. This
restricts those alignment changes to ILP32 builds.
2020-11-23 09:57:45 -06:00
Kinsey Moore
db68ea1b9b bsps: Add Cortex-A53 LP64 basic BSP
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
2020-10-05 16:11:40 -05:00