The current algorithm scans all PCI busses (0..ff)
and all devices (0..31) on each bus for bridges
and determines the maximum of all subordinate
busses encountered.
However, the algorithm does not scan all functions
present in multi-function devices -- I have a PCI express
root complex (82801H) where multiple (non-zero index)
functions are 'PCI bridges' whose subordinate bus number is
missed by the original algorithm.
This commit makes sure that the scan
is extended to all functions of multi-function
devices.
See #2067
According with comment in
rtems_cache_invalidate_multiple_instruction_lines(), final_address
indicates the last address which needs to be invalidated. But if in
while loop we got final_address == i_addr condition then loop breaks and
final_address will not be invalidated.
STOP_TRANSMISSION command is used to finish READ_MULTIPLE_BLOCK
command and its format is regular command format.
It requires valid CRC-7 to have effect at least on
same cards types else it is ignored and attempt
to issue next READ or WRITE commands results in
illegal command condition (0x04) preceded by strange
(0x3f) for tested card.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
CSB336 i.MX1/i.MXS memory map organization
- SDRAM starts at address 0x08000000 but 2 MB are reserved
for boot-block/loader (or other use) before RTEMS image
origin/load address (that is kept from previous setup)
- Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000)
is changed to writeback mode which provides higher throughput.
- The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0
to provide area for ARM CPU exceptions table.
- Internal registers and rest of the Flash (above 1 MB) are mapped
one to one. Registers region is extended to 2 MB to cover
eSRAM found on i.MX1 chip variant.
- The first two megabytes of SDRAM unused by RTEMS are mapped
with attributes to allow specific purposes.
- the first MB (at address 0x08000000) is nocached to allow
directly set some values read by booot-block after warm reset
- the second MB (at address 0x08100000) is set for write-through
caching. That allows to use memory for LCD frame-buffer without
need to flush cache after each redraw.
Signed-off-by: Pavel Pisa <pi@baree.pikron.com>
The original version is missing void and result is that (*x >> 16) is
optimized to ldh rX,[rY]. But it is not allowed/supported to access
bus/address range used by AITC by other than 32 bit wide accesses
and 16-bit access results in the data abort exception.
The corrected version works on real hardware and is even
more readable.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
PR 2015/bsps
Since the configuration struct is always present one can let
DATA initialize it to reduce footprint, at the same time it
is made weak to let the user able to configure the SHM driver
without editing the driver code.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* console/console.c: char_ready() was never returning true so console
never processed input data
* console/console.c: added printk() support to default device
* include/bsp.h: Added #define for MOT_162BUG_VEC_ADDRESS
* startup/bspclean.c: Modified to use MOT_162BUG_VEC_ADDRESS
* startup/bspstart.c: Modified to use MOT_162BUG_VEC_ADDRESS
* make/custom/mvme162.cfg: Modified to use "RTEMS_CPU_MODEL=68lc040"
and "CPU_CFLAGS = -mcpu=68040 -msoft-float" so BSP will always
work with all board variations.
* README: Added notes on user required configuration changes and
information about board models and variants
* README.models: New file that contains a detailed list of MVME162
models and variants.
Signed-off-by: Vic Hoover <victor.hoover.ctr@navy.mil>
GRETH driver updated, 10-15% performance improvements for GBIT MAC,
unnecessary RX interrupts not taken which under heavy load saves approx.
1500 interrupts/s, one task removed saving about 5kb memory and 1 bug
solved.
BUG: RX interrupt was enabled before the RX-daemon was created which could
result in a faulty call to rtems_event_send.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Deadlock may arise when the EDCL bug link is used to tunnel
console output over Ethernet, when Ethernet is down one should
avoid using console (only during debugging of LEON targets)
Author: Marko Isomaki <marko@gaisler.com>
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
PR 2010/bsps
The previous code only checked if d-cache snooping was implemented,
however snooping may be available but not enabled which may lead
to driver bugs.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2009/bsps
All LEON3/4 systems have a CPU-id, if on a single-CPU system the
ID is always zero. On a multicore system it ranges from 0 to 15.
The CPU index should always by updated even in a non-MP RTEMS OS
since the CPU running RTEMS may not always be CPU0. For example
when RTEMS runs on CPU1 and Linux on CPU0 in a mixed ASMP system.
The old code executed within the IRQ controller initialization code
makes no sense since the ASR register is a CPU register, it has
nothing to do with AMBA initialization either.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
The SHM code always wakes one CPU more that configured, however
this has never been a problem since RTEMS will be running on all CPUs
or only two cores were available.
PR 2006/bsps
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* irq/irq.c: Removed printk() before the interrupt initialization
because it somehow destroys the interrupt context.
* make/custom/nds.cfg: Enable Thumb interwork.
* startup/bspstart.c: Set default exception handler.
PR 1832/libcpu
* at91rm9200/irq/irq.c: he bsp_interrupt_dispatch routine does not
determine the correct interrupt source number. According to the
datasheet, the reading of the interrupt vector register (AIC_IVR)
notifies the hardware that the OS is taken care of the interrupt.
Only after AIC_IVR have been read can the correct source number be
read from the interrupt status register (AIC_ISR).
PR 1786/bsps
* Makefile.am: Add support for Altivec.
* startup/bspstart.c, Makefile.am: Use shared/startup/zerobss.c instead.
* make/custom/mvme5500.cfg: Change CPU_CFLAGS to
"-mcpu=7450 -mtune=7450 -Dmpc7455"
* irq/BSP_irq.c, pci/detect_host_bridge.c, pci.c, pcifinddevice.c:
Remove warnings.
* vme/VMEConfig.h, include/bsp.h: use VME shared IRQ handlers.
* network/if_100MHz/GT64260eth.c: Recycle the Rx mbuf if there
is any Rx error.
PR 1781/bsps
* console/console-io.c: The UART RX and TX are different ISR
now. So the array containing the registeration changes. The
change is due to change in the libcup uart function.
PR 1781/bsps
* ChangeLog, Makefile.am, README, bsp_specs, configure.ac,
preinstall.am, times, console/console.c, include/bsp.h,
include/cplb.h, include/tm27.h, make/custom/TLL6527M.cfg,
startup/bspstart.c, startup/linkcmds: New files.
Initial port for the TLL6527Mboard that contains blackfin 52X
range of processors. Used eZKit533 as a reference for building
the port.
PR 1781/bsps
* bf52x/include: Added additional MMR.
* bf52x/interrupt: The BF52X processors have a different
System interrupt controller than present in the 53X range of
processors. The 52X have 8 interrupt assignment registers. The
implementation uses tables to increase predictability.
* serial/uart.?: Added DMA based and interrupt based transfer
support. The uart code used a single ISR for TX and RX and tried
to identify and multiplex inside the ISR. In the new code the
type of interrupt is identified by the central ISR dispatcher
bf52x/interrupt or interrupt/. This simplifies the UART ISR.
