Commit Graph

89 Commits

Author SHA1 Message Date
Jiri Gaisler
b4c29b54e7 Add networking support for griscv bsp
* Only GRETH device supported for now
	* Fix endian problem in GRETH driver
	* Remove SPARC assembly from greth.c
	* Builds with both autoconf and waf
2020-11-09 09:35:11 +01:00
Sebastian Huber
e1a0e0c308 grlib: Add and use irqmp_has_timestamp()
Replace leon3_irqmp_has_timestamp() with irqmp_has_timestamp() and move
it to grlib.h.

Close #4128.
2020-10-10 14:00:37 +02:00
Sebastian Huber
e8450a6c36 bsps/riscv: Add bsp_fdt_map_intr()
This function is required by libbsd.
2020-09-23 07:35:05 +02:00
Hesham Almatary
4897a82dec riscv: Make sifive_test finisher 4 bytes
QEMU is now stricter with MMIO sizes and accesses. uintptr_t on RV64
is 8 bytes and generates an sd instruction that Store/AMO faults
because sifive_test MMIO expects 4 bytes accesses.
2020-09-17 09:01:51 +01:00
Sebastian Huber
2786b0aa38 bsps/riscv: Use far jump to boot_card()
Use a far jump to avoid errors like this:

relocation truncated to fit: R_RISCV_JAL against symbol `boot_card'
2020-09-15 09:20:27 +02:00
Hesham Almatary
764ea57879 htif_console_handler is defined in htif.c
closes #4069.
2020-09-06 16:11:45 -05:00
Sebastian Huber
d556af3605 bsps: Always install IPI in SMP configs
The inter-processor interrupt (IPI) may be used to process per-CPU jobs.
See for example the blocked handler in T_interrupt_test().

Update #3199.
2020-08-31 16:19:53 +02:00
Sebastian Huber
d35722e66c bsps/riscv: Fix multiple definition 2020-04-10 19:56:50 +02:00
Sebastian Huber
0161b93d50 imfs: Replace devfs with an IMFS specialization
Add a simplified path evaluation function IMFS_eval_path_devfs() for a
device only IMFS configuration.

The code size can be further reduced by the application if it disables
the support for legacy IO drivers via:

  #define CONFIGURE_IMFS_DISABLE_MKNOD
  #define CONFIGURE_IMFS_DISABLE_MKNOD_DEVICE

Obsolete CONFIGURE_MAXIMUM_DEVICES.  Remove BSP_MAXIMUM_DEVICES.

Update #3894.
Update #3898.
2020-03-09 17:26:54 +01:00
Sebastian Huber
c344e5828c Use RTEMS_SYSINIT_ORDER_LAST_BUT_5
Use RTEMS_SYSINIT_ORDER_LAST_BUT_5 instead of RTEMS_SYSINIT_ORDER_LAST
to allow applications and support functions to place system
initialization handlers behind the standard handlers.

Update #3838.
2020-02-04 06:06:42 +01:00
Sebastian Huber
ffa1153170 bsps: Add RamEnd to linker command files
Update #3838.
2020-02-04 05:52:28 +01:00
Sebastian Huber
f4fda72f65 Regenerate headers.am 2019-11-29 19:01:48 +01:00
Sebastian Huber
ae5546704d bsp/riscv: Fix format and warnings
Update #3785.
2019-11-14 11:48:33 +01:00
Sebastian Huber
e9ae74369d bsp/riscv: Fix use of uninitialized integer 2019-11-14 11:48:32 +01:00
Sebastian Huber
df9426f970 bsp/riscv: riscv_get_core_frequency()
Always provide this function.  Return 0 by default.  Fix formatting.
Simplify function.

Update #3785.
2019-11-14 11:48:28 +01:00
Hesham Almatary
044687d335 bsps/riscv: UART - Read reg-shift from DTB to properly set/get registers 2019-10-30 09:30:09 +00:00
Hesham Almatary
94481cedc4 riscv: Add new BSP cfg variants to be built with llvm/clang 2019-10-27 10:45:31 +00:00
Hesham Almatary
ce5988e10a riscv: Add new offending input sections to the linker script 2019-10-27 10:45:20 +00:00
Hesham Almatary
7f0c41c759 riscv: Add NOLOAD directive to the .work section
ld.lld defaults .work to PROGBITS otherwise
2019-10-27 10:45:14 +00:00
Hesham Almatary
f462bcbb0a riscv: Address differences in the linkerscript between GNU LD and LLVM/LLD
LLVM/LLD does not support STARTUP and ALIGN_WITH_INPUT directives that
GNU LD support. INPUT and ALIGN(8) are supported by LLVM/LLD and can
replace the unsupported STARTUP/ALIGN_WITH_INPUT directives.

The commit conditionally adds the supported directive that linkers
can understand depending on the toolchain used to compile RTEMS
i.e., clang or gcc. Clang is assumed to use LLD by default.
2019-10-27 10:45:00 +00:00
Hesham Almatary
ca82ded785 riscv: Generate linkcmds.base from the shared linkcmds.base.in
This commit moves the existing linkcmds.base to linkcmds.base.in
in order to make it configurable by autotools.
2019-10-27 10:44:52 +00:00
Pragnesh Patel
a7f5e42cc5 riscv: add freedom E310 Arty A7 bsp
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2019-10-23 08:11:50 +02:00
Sebastian Huber
ad87de4a67 score: Rename _SMP_Get_processor_count()
Rename _SMP_Get_processor_count() in _SMP_Get_processor_maximum() to be
in line with the API level rtems_scheduler_get_processor_maximum().

Update #3732.
2019-04-11 09:19:12 +02:00
Sebastian Huber
f9219db2a9 rtems: Add rtems_scheduler_get_processor_maximum()
Add rtems_scheduler_get_processor_maximum() as a replacement for
rtems_get_processor_count(). The rtems_get_processor_count() is a bit
orphaned. Adopt it by the Scheduler Manager. The count is also
misleading, since the processor set may have gaps and the actual count
of online processors may be less than the value returned by
rtems_get_processor_count().

Update #3732.
2019-04-09 08:06:46 +02:00
Sebastian Huber
828276b081 bsps: Adjust shared Doxygen groups
Update #3706.
2019-03-08 07:42:54 +01:00
Sebastian Huber
c991eeeccc bsps: Adjust bsp.h Doxygen groups
Update #3706.
2019-03-08 07:42:54 +01:00
Sebastian Huber
212663bede bsps: Adjust architecture Doxygen groups
- Use CamelCase as it is not used in our C code.  Enables simple search and
   replace.

 - Prefix with "RTEMS" to aid deployment and integration.  It aids
   searching and sorting.

Update #3706.
2019-03-04 07:51:38 +01:00
Jiri Gaisler
568490a054 griscv: add additional cpu configurations
* Also switch default config to imafd as the C extension
	  is not supported for code coverage
2019-02-08 13:07:27 +01:00
Jiri Gaisler
d3d4e77c42 riscv: add griscv bsp
Update #3678.
2019-01-22 12:50:09 +01:00
Sebastian Huber
9aee88aa54 bsp/riscv: Clear boot command line 2019-01-08 14:44:08 +01:00
Sebastian Huber
ff081aee72 score: Rename interrupt stack symbols
Rename

  * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
  * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
  * _Configuration_Interrupt_stack_size in _ISR_Stack_size.

Move definitions to <rtems/score/isr.h>.  The new names are considerable
shorter and in the right namespace.

Update #3459.
2018-11-08 08:09:20 +01:00
Hesham Almatary
9cda6f29a7 riscv: Allow platforms with no PLIC to proceed
Spike simulator and QEMU's spike_v1.10 don't have a PLIC
2018-09-17 14:22:17 +02:00
Sebastian Huber
141d502b52 bsp/riscv: Add missing BSP variant
Update #3433.
2018-08-02 15:33:00 +02:00
Sebastian Huber
4c740de6e2 bsp/riscv: Fix build with RTEMS_SMP undefined
Update #3433.
2018-08-02 14:13:25 +02:00
Sebastian Huber
3d11c1e2af bsp/riscv: Fix a synchronization issue for PLIC
Update #3433.
2018-08-02 09:28:23 +02:00
Sebastian Huber
dee2ebbaa6 bsp/riscv: Remove unused variable
Update #3433.
2018-08-01 11:15:55 +02:00
Sebastian Huber
56b0387d2f bsp/riscv: Add NS16750 support to console driver
Update #3433.
2018-08-01 11:15:14 +02:00
Sebastian Huber
529154bad2 bsp/riscv: Initialize FPU depending on ISA
Initialize fcsr to zero for a defined rounding mode.

Update #3433.
2018-08-01 10:08:59 +02:00
Sebastian Huber
48cbd63c84 bsp/riscv: Fix clock driver
Do not assume that mtime is zero at boot time.

Update #3433.
2018-08-01 10:07:18 +02:00
Sebastian Huber
44c2d393bd bsp/riscv: Fix inter-processor interrupts
The previous version worked only on a patched Qemu.  Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.

Update #3433.
2018-07-27 15:06:55 +02:00
Sebastian Huber
cfc95736ff riscv: Rework CPU counter support
Update #3433.
2018-07-27 15:06:55 +02:00
Sebastian Huber
581a0f8866 bsp/riscv: Use interrupt driven NS16550 driver
Update #3433.
2018-07-25 10:07:44 +02:00
Sebastian Huber
adede135e7 bsp/riscv: Add PLIC support
Update #3433.
2018-07-25 10:07:44 +02:00
Sebastian Huber
bd5603868a bsp/riscv: Add simple SMP support to clock driver
This is a hack.  The clock interrupt should be handled by each hart.

Update #3433.
2018-07-25 10:07:44 +02:00
Sebastian Huber
6552ba8c37 bsp/riscv: Use CPU counter btimer
Update #3433.
2018-07-25 10:07:44 +02:00
Sebastian Huber
447fd894ae bsp/riscv: Add basic SMP startup
Update #3433.
2018-07-25 10:07:44 +02:00
Sebastian Huber
6b9ef097c3 riscv: Add CLINT and PLIC support
The CLINT and PLIC need some per-processor state.

Update #3433.
2018-07-25 10:07:43 +02:00
Sebastian Huber
f5fd8eb9e3 bsps/riscv: Update linker-symbols.h
Update #3433.
2018-07-25 10:07:43 +02:00
Sebastian Huber
dda6e06edb bsp/riscv: Add reset via for SiFive Test Finisher
Update #3433.
2018-07-25 10:07:43 +02:00
Sebastian Huber
3a263a9b02 bsp/riscv: Add and use riscv_fdt_get_address()
Update #3433.
2018-07-25 10:07:43 +02:00