The default tms570ls3137_hdk variant is for building RTEMS
application image starting directly from start of Flash.
Variant tms570ls3137_hdk_with_loader skips 256kB at start
of Flash to allow use with application loader.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Parameters overlay module is initialized and cleared first.
It is used later to replace exception target vectors
only if that is required.
The application loader code with CPU and SDRAM setup
code has to provide well defined pattern of instructions
at addresses 0x00000000 and 0x0000001f, because only data
read accesses can be processed reliably by POM. The expected
instruction pattern can be seen in the next example
https://github.com/hornmich/tms570ls3137-hdk-sdram/blob/master/SDRAM_SCI_configuration/source/sys_intvecs.asm
Comments with detailed description of code, background
and reasons for selected approach have been included
in TMS570 bsp startup code.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.
In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.
The LPC1768 variants have a gpio.h file whose name clashes with the gpio.h from
the new GPIO API. This results on the BSPs failing to compile.
This patch renames the LPC1768 gpio.* files to lpc-gpio.*, as it's done on other
BSPs (e.g. Beaglebone).
Closes#2441.
According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order. Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.
