The IRQ list in this file are specific to PC hardware and should be
part of the BSP. Further, there are paravirtualized environments which
do not follow the PC hardware IRQ list. Moving this avoids collisions.
This adds support for the 6 SPI interfaces on the STM32H7 series chips
with an initial example for the stm32h750b discovery kit development
board. Configuration is similar to existing peripherals. Chip select
lines are software-controlled since the SPI peripheral only supports a
single hardware-controlled chip select line. This implementation does
not use interrupts.
The default exception handler uses the Save Program Status Register
(SPSR), however, if _ARMV4_Exception_reserved_default() would get
called, the state of this register is unpredictable. Replace potential
calls to _ARMV4_Exception_reserved_default() with an undefined
instruction.
Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM
GIC support. Enable this option for arm/altera-cyclone-v and
arm/xilinx-zynq BSPs by default.
The EOZ9 RTC has a similar register interface like the MCP7940M (and
quite some other I2C RTCs). This commit:
* Extracts the generic parts from MCP7940M and moves it into a generic
i2c-rtc driver.
* Uses the new i2c-rtc for the MCP7940M.
* Uses the new i2c-rtc for the new Abracom EOZ9.
Add support to configure the second region of DDR memory if the
BSP configured RAM size is greater than 2G.
Add the second region's memory to the heap.
Currently, if a BSP is built without MPU alignment enforcement, the MPU
is still enabled and can produce a non-functional binary since code can
be mixed with data within a memory region and memory regions are marked
as read-only or no-execute based on section addresses and sizes leading
to overlapping regions being defined which causes the later-defined
region to take precedence. This change disables the MPU when alignment
is not enforced, allowing the binary to function.
- Move the APIC implementation to its on file instead of having it in clock.c;
- Use the MADT for retrieving the Local APIC base address;
- Initialize the APIC during interrupt initialization.
Add a method for initializing the ACPICA table subsystem earlier than
the initilization of the entire ACPICA subsystem. Also add a method to
walk through the subtables of an ACPI table
There is certainly no USB 20 TG while there is a known USB 2 OTG tech. The
crash caused by this is well observed from media01.exe from libbsd compiled
for H7 and run on the board.
This fixes the ECC info struct naming such that they all use the _Info
suffix. This also adds comments describing which structures are paired
with which event types.
- Implements necessary ACPICA OS Services Layer interfaces;
- Retrieve the RSDP from the FreeBSD Bootloader for amd64 or from multiboot2 for amd64efi;
- Add ACPI initialization routine;
- Use ACPI in bsp_reset.
This patch updates STM32 H7 HAL source files. The files are taken from two
STM projects from their github.com repositories:
(i)
https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git
The project files are still available under BSD-3 license
and the version/commit used is:
fec141ce999da655a48e1a15db83a72d564a1312
which represents Release v1.11.3 exactly.
(ii)
https://github.com/STMicroelectronics/cmsis_device_h7.git
The project files are available under Apache 2.0 license. Fortunately
the project does not contain NOTICE file so no need to do anything special
when used in RTEMS.
The project version/commit imported is:
faccfec37f82f7a1319c21638111b0f7335de7fe
which represents Release v1.10.4 exactly.
