An extern for the linker symbol _ttbl_base was declared incorrectly
and gcc reported an overwrite of the four byte area by 16K. Switched
to using the standard linker symbol macros and the warning was
removed.
This is an update of many lingering embedded brains GmbH licenses from
the RTEMS License to the 2-BSD license where possible depending on the
joint copyrights.
Updates #3053.
The devfg driver loads the PL with a bitfile image. The driver can also
support scrubbing.
These drivers are from Patrick Gauvin <pggauvin at gmail.com> and a thread
on the devel list: https://lists.rtems.org/pipermail/devel/2017-May/017705.html
When using QEMU configurations that support SMP for Zynq7000 systems,
the second core is started at the same time as the first core instead of
waiting for an event to trigger a check for the value at 0xfffffff0
before jumping into RTEMS code. This makes the erroneously started core
wait as expected and prevents prefetch and data aborts from occurring
before the MMU has been properly configured. This was recently exposed
by cleanup done to the ARM GICv2 driver that removed some delays which
were allowing this to operate normally.
This removes the headers imported from the embeddedsw repository in
favor of a much thinner shim. This also removes the complicated build
system configuration necessary to support use of these headers. The
primary reason for removal is that certain external Xilinx libraries
also require use of these headers and this causes version mismatches and
header conflicts that can be avoided.
The information from the README.md have been merged into the
documentation.
The necessary tools for the sdcard.sh are quite tricky to build. All
necessary information to create an SD image are in the documentation
already. So the script isn't necessary any more.
Update #5088
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to
emphasize that this BSP is for the lock-step mode RPU configuration.
Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split
mode RPU configuration for core 0 and 1 respectively.
Remove copyright from DornerWorks since the files contain not contributions
from this company. Fix the copyright years of the embedded brains
contributions.
Do not wait in the individual _CPU_SMP_Start_processor() for the
secondary processor. Wait for all of them in
_CPU_SMP_Finalize_initialization() before the L2 cache is enabled.
There is no need to wait for the secondary processor in
_CPU_SMP_Start_processor() since _CPU_SMP_Finalize_initialization() does
nothing.
The caller of _CPU_SMP_Start_processor() ensures that we do not start
the current processor.
- Refactor the pl011 driver to be extensible.
- Add IRQ support and baudrate configuration support for pl011 driver.
- Modify related BSP.
- Add doxygen comments for arm-pl011.
Close#5026
Co-authored-by: Ning Yang <yangn0@qq.com>
This adds support for the 6 SPI interfaces on the STM32H7 series chips
with an initial example for the stm32h750b discovery kit development
board. Configuration is similar to existing peripherals. Chip select
lines are software-controlled since the SPI peripheral only supports a
single hardware-controlled chip select line. This implementation does
not use interrupts.
The default exception handler uses the Save Program Status Register
(SPSR), however, if _ARMV4_Exception_reserved_default() would get
called, the state of this register is unpredictable. Replace potential
calls to _ARMV4_Exception_reserved_default() with an undefined
instruction.
Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM
GIC support. Enable this option for arm/altera-cyclone-v and
arm/xilinx-zynq BSPs by default.
Currently, if a BSP is built without MPU alignment enforcement, the MPU
is still enabled and can produce a non-functional binary since code can
be mixed with data within a memory region and memory regions are marked
as read-only or no-execute based on section addresses and sizes leading
to overlapping regions being defined which causes the later-defined
region to take precedence. This change disables the MPU when alignment
is not enforced, allowing the binary to function.
There is certainly no USB 20 TG while there is a known USB 2 OTG tech. The
crash caused by this is well observed from media01.exe from libbsd compiled
for H7 and run on the board.
