The 64-bit timestamps were introduced to simplify the timestamp
calculations. This works well since nearly all operations are
additions. The previous _TOD_Tickle_ticks() implementation had a
serious performance regression in case of 64-bit timestamps due to the
usage of two 64-bit divisions which are quite expensive on some
architectures.
A new field seconds_trigger in TOD_Control is introduced to trigger the
_Watchdog_Tickle_seconds() in _TOD_Tickle_ticks(). This avoids the
64-bit divisions completely and only 32-bit additions are used.
Add nanoseconds_per_tick to rtems_configuration_table. This value will
be derived from the microseconds_per_tick value. This avoids some
calculations at run-time.
Port
+ v850 does not have appear to have any optimized bit scan instructions
+ v850 does have single instructions for wap u16 and u32
+ Code path optimization preferences set
+ Add BSP variants for each GCC CPU model flag and a README
- v850e1 variant does not work (fails during BSP initialization)
BSP for GDB v850 Simulator
+ linkcmds matches defaults in GDB simulator with RTEMS mods
+ crt1.c added from v850 newlib port for __main()
+ BSP exits cleanly
+ printk and console I/O work
+ uses clock tick from IDLE task
+ Tests not requiring real clock ISR work
Documentation
+ CPU Supplment chapter for v850 added
The XDR library has a problem on architectures with short enums like the
default ARM EABI. Short enums means that the size of the enum type is
variable and the smallest integer type to hold all enum values will be
selected. For many enums this is char. The XDR library uses int32_t
for enum_t. There are several evil casts from an enum type to enum_t
which leads to invalid memory accesses on short enum architectures. A
workaround is to add appropriate dummy enum values.
The file size was wrong in the no space left on device condition. This
resulted in turn in a read of an invalid block which lead to an EIO
error status.
Read-ahead requests were previously executed in the context of the
reading task. This blocks the reading task until the complete read
with read-ahead transfer is finished. A read-ahead task is introduced
to off-load the read-ahead transfer. This allows the reading task to
work with the requested block more quickly. The read-ahead is triggered
after two misses of ascending consecutive blocks or a read hit of a
block read by the most-recent read-ahead transfer. The read-ahead
feature is configurable and can be disabled.
PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers. The SPE context switch code has been merged
with the standard context switch code. The context switch may use cache
operations to increase the performance. It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This
increases the overall memory size of the context area in the thread
control block slightly. The general-purpose registers GPR2 and GPR13
are no longer part of the context. The BSP must initialize these
registers during startup (usually initialized by the __eabi() function).
The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.
The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch. This should be not
necessary in most cases.
