* include/rtems/system.h: Use proper conditional (RTEMS_POSIX_API)
so prototypes for POSIX_MP_NOT_IMPLEMENTED(), POSIX_NOT_IMPLEMENTED(),
POSIX_BOTTOM_REACHED() are actually included.
* aclocal/canonicalize-tools.m4, aclocal/check-tool.m4,
aclocal/prog-cc.m4, aclocal/prog-cxx.m4: Replace AC_CHECK_TOOL
with an RTEMS specific but more restrictive autoconf macro.
* src/heapgetinfo.c, include/rtems/score/heap.h, src/Makefile.am:
Added _Heap_Get_information() and information control block.
* src/heapgetinfo.c: New file.
a BSP (c4xsim) supporting the simulator included with gdb. This port
was done by Joel Sherrill and Jennifer Averett of OAR Corporation.
Also included with this port is a space/time optimization to eliminate
FP context switch management on CPUs without hardware or software FP.
An issue with this port was that sizeof(unsigned32) = sizeof(unsigned8)
on this CPU. This required addressing alignment checks and assumptions
as well as fixing code that assumed sizeof(unsigned32) == 4.
routines and structures that require CPU model specific information
are now in libcpu. This primarily required moving erc32 specific
information from score/cpu files to libcpu/sparc and the erc32 BSP.
that decouples exec/ for the sh, m68k and i960 from targopts.h.
NOTE: The change to system.h is a hack to enable cpuopts.h
for some targets, but keep using targopts.h for others - I know it
does *not* work for sparc, mips, i386 and ppc. This will have
to be addressed as work continues on multilibing.
that addresses aspects of the targopts.h multilib related
issues.
Changes:
* Move targopts.h to libbsp/include, because the current targopts.h
actually is a per-BSP-header and therefore can not stay below exec/.
* Introduce an autoheader generated header file
(exec/score/include/rtems/score/cpuopts.h), which shall take per-cpu
configuration options only.
* Move all autoconf-detectable/configure specified per-cpu
option-defines from targopts.h to cpuopts.h.
* Add Makefiles to the libbsp/shared directory hierarchy.
Notes:
* The new per-bsp targopts.h in libbsp includes the per-cpu
cpuopts.h. This way, the new targopts.h is kept backward compatible
to the old targopts.h and existing BSPs which (carelessly) include
targopts.h (i386, ppc) should be kept working when using the
multilib-disabled configuration scheme.
* cpuopts.h is not yet complete, because the per-BSP make-targopts
rules from custom/<BSP>.cfg files can not be applied to files below
exec/ when building multilibs.
* All files below exec/ should not include targopts.h anymore, but
should include cpuopts.h instead. However, eliminating inclusion of
targopts.h currently triggers further structural / header file inclusion
related issues, because several ports apply BSP or CPU_MODEL specific
defines from targopts.h below exec/
<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860
I'd like to propose a change to RTEMS task variables that I think would
make them more useful. I think that it is early enough in their
existence to still make changes to their API.
1) Change type from `int' to `void *'.
2) Add extra argument to task_variable_add -- if non-NULL, a pointer to
a `destructor' function to be called when the task exits. This function
would be called with that task's value of the task variable as its
argument. In many cases, the `dtor' function could be `free'.
rtems_status_code rtems_task_variable_add (
rtems_id tid, void **ptr, void (*dtor)(void *));
rtems_status_code rtems_task_variable_delete (rtems_id tid, void **ptr);
This would be all we'd need to cleanly and efficiently support C++
per-thread exception information without dragging in all that POSIX API
stuff.
blocking sends when the queue is full. The SuperCore was enhanced
to support blocking on send. The existing POSIX API was debugged
and numerous test cases were added to psxmsgq01 by Jennifer Averett.
SuperCore enhancements and resulting modifications to other APIs
were done by Joel.
There is one significant point of interpretation for the POSIX API.
What happens to threads already blocked on a message queue when the
mode of that same message queue is changed from blocking to non-blocking?
We decided to unblock all waiting tasks with an EAGAIN error just
as if a non-blocking version of the same operation had returned
unsatisfied. This case is not discussed in the POSIX standard and
other implementations may have chosen differently.
power binary/mutex style semaphores already supported by RTEMS. This
was done at the request of Eric Norum <eric@cls.usask.ca> in support
of his effort to port EPICS to RTEMS. This change consisted of
changing the nesting_allowed boolean into a lock_nesting_behavior
enumerated value as well as allowing the core mutex object to optionally
support ensuring that the holder of a binary semaphore released it.
Finally, a more subtle enhancement was to allow the non-holder to release
a priority inheritance/ceiling mutex and still allow the holding task
to return to its original priority.
RTEMS API extension to avoid problems when the extension is freed.
Eventually the task variable switch extension should become part
of the core context switch and the Ada tcb self implemented in
terms of it.
unnecessarily uses any variables defined by the BSP. On this
sweep, use of BSP_Configuration and Cpu_table was eliminated.
A significant part of this modification was the addition of
macros to access fields in the RTEMS configuration structures.
This is necessary to strengthen the division between the BSP independent
parts of RTEMS and the BSPs themselves. This started after
comments and analysis by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.
described in the message following this paragraph. This patch also includes
a mcp750 BSP.
From valette@crf.canon.fr Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@crf.canon.fr>
To: joel@oarcorp.com
Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr
Subject: Questions/Suggestion regarding RTEMS PowerPC code (long)
Dear knowledgeable RTEMS powerpc users,
As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.
In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.
the MCP750 is a COMPACT PCI powerpc board with :
1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,
This architecture is common to most Motorola 60x/7xx
board except that :
1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...
So the port should be a rather close basis for many
60x/7xx motorola board...
On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.
Now the questions/suggestions I have :
1) EXCEPTION CODE
-------------------
As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :
a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC
==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)
See remark about files/directory layout organization in 4)
2) Current Implementation of ISR low level code
-----------------------------------------------
I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S
#if (PPC_USE_SPRG)
mfmsr r5
mfspr r6, sprg2
#else
lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5
#endif
Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :
a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.
Reading the code, I see others have the same kind of request :
/* SCE 980217
*
* We need address translation ON when we call our ISR routine
mtmsr r5
*/
This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...
Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.
I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...
So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)
I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.
3) R2/R13 manipulation for EABI implementation
----------------------------------------------
I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).
So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.
The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.
=> I propose to suppress any specific code for r2 and
r13 in the EABI case.
4) Code layout organization (yes again :-))
-------------------------------------------
I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.
a) exec/score/cpu/* vs lib/libcpu/cpu/*.
I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.
This include at least :
a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,
b) lib/libcpu/cpu/powerpc/*
With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)
powerpc
ppc421 mpc821 ...
I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.
So, except if the support of automake provides a better solution
I would like to propose something like this :
powerpc
mpc421 mpc821 ... mpc750 shared wrapup
with the following rules :
a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a
b) layout under processor specific directory is free provided
that
1)the result of the compilation process exports :
libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu
2) each processor specific directory creates
a library called libcpuspecific.a
Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...
c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu
The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...
Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...
NB: I have done this for mpc750 and other processors could just use
similar Makefiles...
c) The exec/score/cpu/powerpc directory layout.
I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...
Besides that I do not understand why
1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,
I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),
5) Interrupt handling API
-------------------------
Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :
--------- 0 ------
| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |
--------- ------ | |
^ ------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts
OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :
1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.
I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :
1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...
I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).
Additional note : I think the _ISR_Is_in_progress()
inline routine should be :
1) Put in a processor specific section,
2) Should not rely on a global variable,
As :
a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via __CPU_IRQ_info.Nest_level a dedicated
SPR could be used.
NOTE: most of this is also true for _Thread_Dispatch_disable_level
END NOTE
--------
Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :
1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)
Any comments/objections are welcomed as usual.
--
__
/ ` Eric Valette
/-- __ o _. Canon CRF
(___, / (_(_(__ Rue de la touche lambert
35517 Cesson-Sevigne Cedex
FRANCE
Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@crf.canon.fr
First, the unlimited patch. I have compiled the unlmited patch for the
Linux posix BSP only and it seems to work cleanly. I would like a really
major application run on this change before commiting as the changes are
very core and significant. I am currently building all the tests to run.
I have no targets suitable to test on at the moment.
I have tested the patch for inline functions and macros.
Turning macros on has found some core bugs. I have fixed these but have
not run all the tests. Please review the patch for these changes. They
are:
1) The conditional compilation for MP support broke the core messages
code. You cannot embed a conditional macro in another macro. The Send
and Urgent Send calls are macros.
2) User extensions handler initialisation now has two parameters. I have
updated the macros to support the extra parameter.
The patch also contains the gcc-target-default.cfg fix required to build
the kernel. More of a by product than a fix for you.
1) Socket timeout field changed from `short' to `long'. This makes longer
timeouts possible. With a 1 kHz system clock the old system allowed
timeouts only up to a little over 30 seconds! This change is a
slightly cleaned-up version of the patch proposed by Ian Lance Taylor.
2) Major changes to BOOTP/DHCP reply handling. Now supports much of
RFC2132. These changes were done at the request of, and with the
assistance of, Erik Ivanenko.
If you're making changes, you might want to change the network
supplement Essentially just do a global search and replace of BOOTP
with BOOTP/DHCP.
to multiple. This lets the stack check extension be installed
at system initialization time and avoids the BSP having to
even know about its existence.
>> >>There is a 30 day error in _TOD_Days_since_last_leap_year[2..3]
>> >
>> >Thanks.
>> >What's the condition to hit this error?
>> >Every year 4n+2 and 4n+3 ?
>> >(i.e. 1998, 1999, 2002, 2003, ...)
>> >
>> OK: 96 97 00 01 04 05 ...
>> Bad: 98 99 02 03 06 07 ...
There is also a problem in newlib 1.7.x reported at the same time:
>> I found another, that would strike only on 2/29/2000, or other leapyears.
>> Only a problem on 1 day.
>>
>> Joel: FYI, there is a bug in Newlib localtime.c, localtime or (_tm_time).
>> Ours is modified for dst and timezones, but the bug was in original source.
>> I have not looked at the latest public source (nor do I know where to find
>> it).
