Place the vector table in the start section so that the overlay can be
avoided if we execute from internal flash. The problem is that when the
POM is enabled, the ECC cannot be enabled for the internal flash.
With this, it is possible to use GPIOs as CS pins in the LPSPI. To avoid
additional complexity, the GPIOs will have the same limitations as the
native (hardware) CS pins.
The GPIO CS feature adds a number of extra code when starting SPI
transfers on this controller. Therefore it is possible to disable the
additional code by just setting the IMXRT_LPSPI_MAX_CS option to 0. In
that case only native CS pins are supported.
At the moment, this feature is only enabled on i.MXRT1166 by default
because it is not tested on i.MXRT1050. But it should work there too.
Device trees allow mixing different kinds of GPIOs in one property. For
that it is usefull to only provide a pointer to an arbitrary location in
the property and initialize a GPIO from that.
For uniprocessor configurations, the selection of
RTEMS_MULTIPROCESSOR_RESOURCE_SHARING results in a priority ceiling
mutex.
Build the MrsP validation tests only if RTEMS_SMP is enabled.
Update #3716.
This imports the TTC hardware definitions for the triple timer counters
on various Xilinx platforms. This was imported as specified in the
VERSION file in this commit.
The code coverage build is usually done without compiler optimizations.
This results in long performance test runtimes and useless performance
results.
Enable an individual testsuite only through the corresponding enable.
Use BUILD_TESTS to change the default value of the individual testsuite
enable options. This allows the user to enable all testsuites with
specific exceptions.
For example, this builds all testsuites except the benchmarks:
[arch/bsp]
BUILD_TESTS = True
BUILD_BENCHMARKS = False
Thread_Life_state is used as a bitfield, but is declared as an enum.
This converts the enum typedef to a uint32_t typedef and associated bit
definitions.
The xnandpsu driver conditionally tries to wrap page index to NAND chip
size causing an off-by-one error where the first page of the second chip
is not wrapped correctly. This removes the conditional so that page
index is always wrapped.
On configurations where multiple NAND chips are in use, the erasure
loop in XNandPsu_Erase() can reset the loop counter variable once it
gets to blocks in the second chip causing an infinite loop overwriting
parts of the first chip. This change ensures that the loop counter is
not accidentally reset.
Prefer use of XNandPsu_Erase instead of XNandPsu_EraseBlock since the
XNandPsu driver does not expose the primitives necessary to ensure
device readiness after the operation is complete.
