Add and use _ASR_Get_posted_signals(). The post-switch handler is not
protected by disabled thread dispatching. Use proper SMP lock for
signal management.
pc386 set CLOCK_DRIVER_ISRS_PER_TICK to a
string rather than a numeric value. Add
CLOCK_DRIVER_ISRS_PER_TICK_VALUE and
other clean up on the clock driver.
The _Thread_queue_Process_timeout() operation had several race
conditions in the event of nested interrupts. Protect the critical
sections via disabled interrupts.
Add Thread_Control::is_in_the_air field if configured for SMP. This
helps to simplify the extract operation and avoids superfluous
inter-processor interrupts. Move the processor allocation step into the
enqueue operation.
Add and use _Scheduler_simple_smp_Get_highest_ready(). Add and use
_Scheduler_SMP_Get_lowest_scheduled().
Delete _Priority_bit_map_Handler_initialization() and rely on BSS
initialization. Move definition of _Priority_Major_bit_map and
_Priority_Bit_map to separate file. Move definition of __log2table also
to this file.
Add call to _Scheduler_Schedule() in missing path after
_Thread_Set_transient() in _Thread_Change_priority(). See also
sptests/spintrcritical19.
Add thread parameter to _Scheduler_Schedule(). This parameter is
currently unused but may be used in future SMP schedulers.
Do heir selection in _Scheduler_Schedule(). Use
_Scheduler_Update_heir() for this in the particular scheduler
implementation.
Add and use _Scheduler_Generic_block().
CSB336 i.MX1/i.MXS memory map organization
- SDRAM starts at address 0x08000000 but 2 MB are reserved
for boot-block/loader (or other use) before RTEMS image
origin/load address (that is kept from previous setup)
- Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000)
is changed to writeback mode which provides higher throughput.
- The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0
to provide area for ARM CPU exceptions table.
- Internal registers and rest of the Flash (above 1 MB) are mapped
one to one. Registers region is extended to 2 MB to cover
eSRAM found on i.MX1 chip variant.
- The first two megabytes of SDRAM unused by RTEMS are mapped
with attributes to allow specific purposes.
- the first MB (at address 0x08000000) is nocached to allow
directly set some values read by booot-block after warm reset
- the second MB (at address 0x08100000) is set for write-through
caching. That allows to use memory for LCD frame-buffer without
need to flush cache after each redraw.
Jump to start provided at address 0x08200000 allows
to load application image even as plain binary file
and start it by jump to image start address.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
