The commit partially restores the _ISR_Handler code to the original
version in commit b8fc2de1ce. A list of
reverted changes follows.
commit c236082873
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue Jul 30 15:54:53 2013 +0200
smp: Provide cache optimized Per_CPU_Control
Delete _Per_CPU_Information_p.
This commit was completely reverted.
commit 39e51758c8
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri Jun 14 14:00:38 2013 +0200
smp: Add and use _CPU_SMP_Get_current_processor()
Add and use _SMP_Get_current_processor() and
rtems_smp_get_current_processor().
Delete bsp_smp_interrupt_cpu().
Change type of current processor index from int to uint32_t to match
_SMP_Processor_count type.
This commit was completely reverted.
commit e94aa61b68
Author: Till Straumann <strauman@slac.stanford.edu>
Date: Fri Aug 5 00:15:50 2011 +0000
2011-08-04 Till Straumann <strauman@slac.stanford.edu>
* shared/irq/irq_asm.S: BUGFIX (introduced by SMP changes
which moved code around, apparently): *must* store i8259
mask to frame *before* switching to IRQ stack. The code
retrieves the mask after switching back to original stack.
Also, the IRQ stack has no reserved space for the mask;
storing it there could overwrite memory!
This commit was completely reverted.
commit 01f2692e33
Author: Jennifer Averett <Jennifer.Averett@OARcorp.com>
Date: Mon Aug 1 13:41:50 2011 +0000
2011-08-01 Jennifer Averett <Jennifer.Averett@OARcorp.com>
PR 1802
* shared/irq/irq_asm.S, shared/irq/irq_init.c, shared/smp/smp-imps.c,
shared/smp/smp-imps.h: Add SMP support for i386.
* shared/smp/getcpuid.c: New file.
The parts modifying the code of _ISR_Handler were reverted.
commit 66729db311
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Wed Mar 16 20:05:17 2011 +0000
2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>
PR 1729/cpukit
* shared/irq/irq_asm.S: Add next step in SMP support. This adds an
allocated array of the Per_CPU structures to support multiple cpus vs
a single instance of the structure which is still used if SMP support
is disabled. Configuration support is also added to explicitly enable
or disable SMP. But SMP can only be enabled for the CPUs which will
support it initially -- SPARC and i386. With the stub BSP support, a
BSP can be run as a single core SMP system from an RTEMS data
structure standpoint.
This commit was completely reverted.
Move the _CPU_Context_switch(), _CPU_Context_restore() and
_CPU_Context_switch_to_first_task_smp() code since the method to obtain
the processor index is BSP specific.
As a side-effect the PR2082 is fixed with this and later changes.
The commit restores the _ISR_Handler code to the original version in
"cpukit/score/sparc/cpu_asm.S" in commit
6d42b4c60a. A list of reverted changes
follows.
commit c236082873
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue Jul 30 15:54:53 2013 +0200
smp: Provide cache optimized Per_CPU_Control
Delete _Per_CPU_Information_p.
This commit was completely reverted.
commit e517714b7c
Author: Jennifer Averett <jennifer.averett@oarcorp.com>
Date: Tue Feb 26 12:31:23 2013 -0600
sparc: Remove dead code that was leftover from SMP development.
This commit was completely reverted.
commit 47a61aa16f
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Fri Oct 7 14:35:03 2011 +0000
2011-10-07 Daniel Hellstrom <daniel@gaisler.com>
PR 1933/cpukit
* shared/irq_asm.S: From code inspection I have found the following
issues (most SMP), and some improvements in irq_asm.S. I would need a
long test with interrupts to verify the interrupt handler better,
however I can not see that these patches hurt. Please see comment per
hunk below, One should go through the file to indent delay-slots
correctly, I have fixed some in the patch areas. An extra space is
added in front of delay slots to indicate a delay slot.
This commit was completely reverted.
commit 0bd3f7e5d1
Author: Jennifer Averett <Jennifer.Averett@OARcorp.com>
Date: Thu Jul 28 17:33:07 2011 +0000
2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com>
PR 1801
* shared/irq_asm.S: Modifications to synch the sparc with the smp
working tree.
This commit was completely reverted.
commit 5d69cd33e9
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Wed Mar 16 20:05:30 2011 +0000
2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>
PR 1729/cpukit
* shared/irq_asm.S: New file.
The parts modifying the original code of _ISR_Handler were reverted.
Only the content move remains.
Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
Add and use _Per_CPU_Release_all().
The context switch user extensions are invoked in _Thread_Dispatch().
This change is necessary to avoid the giant lock in _Thread_Dispatch().
Rename _Per_CPU_Lock_acquire() to _Per_CPU_ISR_disable_and_acquire().
Rename _Per_CPU_Lock_release() to _Per_CPU_Release_and_ISR_enable().
Add _Per_CPU_Acquire() and _Per_CPU_Release().
The initial region (64 bytes) of SDRAM RTEMS image is remapped
to provide overlay of the initial/ROM exceptions table.
This area cannot be used for MMU mapping table. Different correctly
aligned block has to be used for MMU table. Remapping of SDRAM
(address 0x08200000) to address 0 is supported only on 1 MB block
granularity and that is why SDRAM_VEC area has to be 1 MB aligned too
but unused part of remapped region can be freely used for other
purposes (as MMU tables).
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Use the POSIX configuration value directly. Use right type early and
avoid casts. Use proper unlimited objects API. Check workspace
allocation. Make functions static.
This patch enables unlimited model in POSIX key manger and have a decent
runtime on POSIX key searching, adding and deleting operations. Memory
overhead is lower than current implementation when the size of key and key
value becomes big.
Add context parameter to _Thread_Start_multitasking() and use this
function in rtems_smp_secondary_cpu_initialize(). This avoids
duplication of code.
Fix missing floating point context initialization in
rtems_smp_secondary_cpu_initialize(). Now performed via
_Thread_Start_multitasking().
