Add functions for flushing and invalidating whole cache.
Since we don't have system calls that can operate on anything more than
a single cache line, these simply retrieves the cache size and iterates
over the full size, invalidating each line.
The current implementation assumes that there's only one level of cache.
These changes were contributed by Antmicro under contract by ÅAC
Microtec AB.
Close#2602
Callers of _Thread_Do_dispatch() must have a valid
Per_CPU_Control::Stats::thread_dispatch_disabled_instant.
Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt
stack to not exceed Per_CPU_Control::Interrupt_frame.
Update #2751.
Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution. During this period we must not use
a thread stack for interrupt processing.
Update #2809.
Use the previously unused TPIDRPRW register to get the per-CPU control
of the current processor. This avoids instructions in
GET_SELF_CPU_CONTROL which are not available in Thumb mode.
Add _CPU_Get_current_per_CPU_control() on SMP configurations. Use SPRG0
for the current per-CPU control. This reduces the code size by three
instructions and is slightly faster.
Update #2805.
The single write to memory or ioport output are mostly
atomic operations already. The proper memory synchronization barrier
should be used around them to guarantee ordering (sync or eieio
on PowerPC for example) but because I have not found settable
portable primitive only compiler barrier is used.
It should be enough on x86 because the externally visible order
should be/is guaranteed to be preserved on x86 architecture.
When GCC option -march is not specifies i386-rtems toolchain
defaults to i386 architecture instruction set. It does not
provide atomic instructions which results in really inefficient
atomic_fetch_or even on UP build.
SMP build is broken with i386 set because libatomic and GCC
generate infinite loop for __atomic_fetch_add_4 used
in rtems_interrupt_lock_acquire
__atomic_fetch_add_4:
push %ebp
mov %esp,%ebp
movl $0x5,0x10(%ebp)
pop %ebp
jmp __atomic_fetch_add_4
The global state of enabled and disabled interrupts has to hold
interrupts really disabled by drivers and system. If the state is
combined with interrupts temporarily disabled because they are
processed at given time then it is impossible to maintain state
by interrupt handlers in drivers.
The configuration is specific for TMS570LS3137 based HDK.
Pins configuration can be easily changed in
rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c
file.
The list tms570_selftest_par_list in the file
rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c
specifies peripherals which health status is examined
by parity self-test at BSP start-up. It can be easily
modified for other TMS570 family members variants same
as the selection of other tests in bspstarthooks-hwinit.c.
Generated header file ti_herc/reg_spi.h contains complete registers
and fields set for Ti MibSPI peripheral.
Care has to be taken that only TMS570_SPI1, TMS570_SPI3 and TMS570_SPI5
are of this complete multibuffer type. TMS570_SPI2 and TMS570_SPI4
have substantial part of registers removed but else they are compatible.
