* new-exceptions/e500_raw_exc_init.c, new-exceptions/raw_exception.c,
shared/include/cpuIdent.c, shared/include/cpuIdent.h:
Added different kinds of 'bookE' to the ppc_cpu_is_bookE feature
check; unfortunately...
* shared/include/cpuIdent.h, shared/include/cpuIdent.c:
Added a simple 'feature check' facility. Code should
not check for a particular CPU type if possible but
check the respective feature bit (e.g., 'has_altivec').
This makes it much less cumbersome to add more CPU
types in the future.
* powerpc/shared/include/cpuIdent.c,
powerpc/shared/include/cpuIdent.h: Add 603le.
(Submitted by Thomas.Doerfler <Thomas.Doerfler@imd-systems.de>
as part of the patch attached to PR 703).
* configure.ac, mpc6xx/exceptions/raw_exception.c,
mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c,
mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, shared/include/cpuIdent.c,
shared/include/cpuIdent.h: Add MPC8240 and MPC8245 support. There was
also a significant amount of spelling and whitespace cleanup.
PR 349/bsps
* mpc6xx/exceptions/raw_exception.c, mpc6xx/mmu/bat.c,
mpc6xx/mmu/pte121.c, shared/include/cpuIdent.c,
shared/include/cpuIdent.h, shared/src/Makefile.am, shared/src/stack.c,
shared/src/stackTrace.h, powerpc/registers.h:
- undo improper 'fix' who broke mpc604r identification
- fix: 7400 identification PVR value was wrong
- enhance 'setdbat()' to switch OFF a given BAT if called with 0 size
- fix: page table support bugfix
- enhancement: provide routines to take and print stack trace
snapshots
- add definitions for HID1 and DABR SPRs
* rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add
the following:
- support for the MPC74000 (AKA G4); there is no
AltiVec support yet, however.
- the cache flushing assembly code uses hardware-flush on the G4.
Also, a couple of hardcoded numerical values were replaced
by more readable symbolic constants.
- extended interrupt-disabled code section so enclose the entire
cache flush/invalidate procedure (as recommended by the book).
This is not (latency) critical as it is only used by
init code but prevents possible corruption.
- Trivial page table support as been added.
(1:1 effective-virtual-physical address mapping which is only
useful only on CPUs which feature hardware TLB replacement,
e.g. >604. This allows for write-protecting memory regions,
e.g. text/ro-data which makes catching corruptors a lot easier.
It also frees one DBAT/IBAT and gives more flexibility
for setting up address maps :-)
- setdbat() allows changing BAT0 also (since the BSP may use
a page table, BAT0 could be available...).
- asm_setdbatX() violated the SVR ABI by using
r20 as a scratch register; changed for r0
- according to the book, a context synchronizing instruction is
necessary prior to and after changing a DBAT -> isync added
* mpc6xx/clock/c_clock.c: Include rtems/bspIo.h instead of bspIo.h.
* mpc6xx/mmu/bat.h: Include rtems/bspIo.h instead of bspIo.h.
* mpc8260/console-generic/console-generic.c: Include rtems/bspIo.h instead of bspIo.h.
* mpc8260/cpm/brg.c: Include rtems/bspIo.h instead of bspIo.h.
* mpc8xx/console-generic/console-generic.c: Include rtems/bspIo.h instead of bspIo.h.
* shared/include/cpuIdent.c: Include rtems/bspIo.h instead of bspIo.h.
