This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
Exception handling should be enabled at all times during execution to
ensure that exceptions are not ignored which would cause further
problems. This separates use of the exception enable bit from use of the
interrupt enable bit in the machine status register so that they can be
manipulated independently.
A device tree binary has to be 8 byte aligned in memory. This is checked
since RTEMS commit 34052ef78c "libfdt: Add
FDT alignment check to fdt_check_header()".
Put the next character into the send buffer if the buffer is empty and
not when the last character has been sent out to the line. This improves
the performance slightly.
Before that patch, the receive path was faster than the transmit path.
Therefore a simple echo could drop characters on a busy connection.
With this patch sending and receiving has about the same performance so
that no characters are lost.
Fixes#4610
The driver didn't return with an error on (for example) a NACK on the
bus. This adds the expected error return. Due to the new case that a
transfer can be interrupted on an error, there were some new edge cases.
This patch therefore also fixes these edge cases by removing the
transfer_state that more or less duplicated the interrupt states.
Fixes#4592
Do some clean ups. Remove superfluous variables. Eliminate some overly
complex logic (information about transfer and remaining bytes has been
tracked redundantly in multiple variables).
This patch doesn't change the behavior of the driver.
Update #4592
This patch adds a vector for debug events along with a hook similar to
the exception framework. The debug vector generates an exception frame
for use by libdebugger.
This patch updates the CPU_Exception_frame to include all necessary
registers, combines hardware snd software exception handlers into a
shared vector, provides an architecture-specific hook for taking
control of exception handling, and moves exception handling over to
actually using the CPU_Exception_frame instead of a minimal interrupt
stack frame. As the significant contents of _exception_handler.S have
been entirely rewritten, the copyright information on this file has been
updated to reflect that.
If the system is busy with other interrupts and the UART is set to a
fast baud rate, it's possible to loose UART interrupts and therefore
characters. This allows to optionally enable a DMA for the UARTs so that
a number of lost interrupts can be tolerated.
The number of DMAs on this chip is limited and not not all applications
need that feature. Therefore the DMA is disabled by default.
Close#4578
If no extended features of the USART are used and if the comparison
feature of the UART is not used, the two modules are compatible. The
drivers were nearly identical except for some names of the defines.
This patch merges the two drivers into one.
Update #4578
Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
