Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the "flush instruction cache" bit in the cache control register.
A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
This patch allows the user to configure the PHY address for the DWMAC
driver by giving a pointer to a dwmac_user_cfg structure to network
stack via rtems_bsdnet_ifconfig::drv_ctrl.
BSP completes build with tests and debug enabled for all three variants now
tms570ls3137_hdk
tms570ls3137_hdk_intram
tms570ls3137_hdk_sdram
Even that all enabled tests builds for internal RAM variant, many
of them are expected to fail on hardware because whole tests
including code, data and runtime work area demands has to fit
into 256 kB of RAM.
This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram
BSP variant in in default build. Debug build with --enable-rtems-debug set
has succeed for samples subset of tests as well.
Also cleanup:
* Remove un-needed interrupt disables.
* Address errata "e989: FLASH: Disable Prefetch during programming and erase"
* Use RTEMS_ARRAY_SIZE() macro instead of own macro.
Included variants:
tms570ls3137_hdk_intram - place code and data into internal SRAM
tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM
tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication
stored and running directly from flash. Not working yet.
Chip initialization code not included in BSP.
External startup generated by TI's HalCoGen was used for
testing and debugging.
More information about TMS570 BSP can be found at
http://www.rtems.org/wiki/index.php/Tms570
Patch version 2
- most of the formatting suggestion applied.
- BSP converted to use clock shell
- console driver "set attributes" tested. Baudrate change working
Patch version 3
- more formatting changes.
- removed leftover defines and test functions
Todo:
refactor header files (name register fields)
The problem wit incorrect switching of pins into analog mode manifestes
on LPC4088 based board.
LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin
with analog option). The pin was listed as D category on LPC1788
which does not have analog mode control bit. If analog option is
not explicitly switched off on LPC4088 then the pin does not work
as digital pin.
Code tested on LPC1788 and no problems has been observed even that
manual specifies the IOCON_ADMODE field as reserved and should
be written as zero. But even RTEMS lpc24xx_gpio_config sets this
bit unconditionally.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
The first pass at building these was without networking enabled.
This pass addresses that plus accounts for some new BSPs which
needed testsuite.tcfg files and BSPs which could not link tests
which had been added since the first pass.
Move the APBUART console driver support to the shared SPARC area so that
it can be reused by other BSPs. Only the console driver initialization
is now BSP specific.
Fix context switch on SMP for ARM, PowerPC and SPARC.
Atomically test and set the is executing indicator of the heir context
to ensure that at most one processor uses the heir context. Break the
busy wait loop also due to heir updates.
Rename bsp_mm_config_table to arm_cp15_start_mmu_config_table and
rename bsp_mm_config_table_size to arm_cp15_start_mmu_config_table_size
to be in line with the other names in <bsp/arm-cp15-start.h>.
.. according to the maximum number of termios ports which is
8. Since LEON3 uses PnP to find how many UARTs there are
present we must make sure worst case work.
The current maximum of 4 free nodes caused for example the
GR712RC with its 6 UARTs to fail during devfs02 test.
On SMP rtems_interrupt_lock_context must be used. Most tests fail with a
NULL pointer exception when exiting, except on NGMP where main memory is
at 0x00000000.
When trying to compile RTEMS for the Stellaris LM3S6965 board, I had an
issue of pppd.exe's .rodata section being too big to fit in the board's
memory image (region 'ROM_INT' overflowed).
This reverts commit d9ff8b3e68.
It is not that simple:
https://sourceware.org/ml/binutils/2014-06/msg00062.html
On Fri, Jun 06, 2014 at 01:31:48PM +0200, Sebastian Huber wrote:
> On 2014-06-06 13:23, Sebastian Huber wrote:
> >Ok, so this "cmplwi cr0, rX, ppc_exc_lock_std@sdarel" is illegal,
> >since
> >ppc_exc_lock_std@sdarel is signed and the immediate is unsigned
> >16-bit? The
> >assembler doesn't issue a warning about this.
> >
> >Exists there a way to rescue this cmplwi hack without relaxing the
> >overflow
> >checks?
>
> Hm, sorry, it was surprisingly simple. This works:
>
> "cmplwi cr0, rX, ppc_exc_lock_std@sdarel@l"
>
> I was not aware that you can add several @ in a row.
That is the wrong thing to use here. sdarel@l translates to a VLE
reloc which applies to a split 16-bit field in VLE insns.
You want
cmpwi cr0, rX, ppc_exc_lock_std@sdarel
to properly compare a 16-bit signed number from sym@sdarel.
Note that the assembler does error if you write something like
cmplwi 3,-30000
or
cmpwi 3,40000
so what the linker is now doing is extending this behaviour to link
time.
