By default, allocate the IDLE task storage areas from the RTEMS Workspace.
This avoids having to estimate the thread-local storage size in the default
configuration.
Add the application configuration option CONFIGURE_IDLE_TASK_STORAGE_SIZE to
request a static allocation of the task storage area for IDLE tasks.
Update #3835.
Update #4524.
Add the INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILED fatal error in case the
creation of an idle thread fails. This may happen due to a failing create
extension provided by the application.
This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently
only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in
64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry
Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM
BSP.
Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently.
Mini-UART is not supported. Mini-UART is default UART on the board so it needs
to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support
for additional 4 PL011-UARTs on the board.
The raspberrypi.h includes many of the address required for the future
development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore
Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
There is not just big-endian on ARM. We have two variants BE32
(obsolete) and BE8. The Cortex-R5F processor supports only BE8,
however, some TMS570 variants are BE32 internally. In GCC 8 and later,
the --be8 option is passed to the linker based on the selected
architecture or CPU. Use BE32 by default for the TMS570 BSP.
In GCC, see:
commit 63d03dcecdafe34715282a5155cfc2162375feca
Author: Richard Earnshaw <rearnsha@arm.com>
Date: Mon Jul 3 13:22:05 2017 +0000
[arm] Clean up generation of BE8 format images.
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the following NOEL-V FPGA example design ranges
available from Cobham Gaisler. Follow the links for free
bit-streams, DTS/DTB, user's manuals and quick-start guides:
- NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7)
- NOEL-PF-EX (https://www.gaisler.com/NOEL-PF)
- NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU)
Uses the shared GRLIB APBUART console driver "apbuart_termios.c".
APBUART devices are probed using device tree.
Closes#4225.
The ABI flags for the amd64 BSP contain the -Werror=return-type flag. There is no reason for this to be there so it has been removed. The same option has also been removed amd64.cfg file.
- Versal has IO mapped to the upper 64bit address space and
needs full 64bit addresses.
- Add xilinx_versal_aiedge for custom hardware
- Make the hardware settings the defaults and qemu as variants
Closes#4693
This adds the configure option CONFIGURE_POSIX_TIMERS_FACE_BEHAVIOR
which allows the application to choose whether to have the POSIX
timer_create() function follow the behavior defined by POSIX or
the FACE Technical Standard.
Updates #4691.
rtl-mdreloc-arm.c was used as the basis for rtl-mdreloc-aarch64.c. This lead
to some code being shared by the two files. The code was consolidated into
rtl-unwind-arm.c.
Closes#4686
- Support DDRMC0 region 0 up to 2G in size
- Support DDRMC0 region 1 with DDR memory greater than 2G
up to the DDRMC0 max amount
- Extend the heap with region 1's memory
Closes#4684
The uniprocessor schedulers had some special case logic for the
PRIORITY_PSEUDO_ISR priority. Tasks with a priority of PRIORITY_PSEUDO_ISR
were allowed to preempt a not preemptible task. If other higher priority task
are made ready while a PRIORITY_PSEUDO_ISR task preempts a not preemptible
task, then the other tasks run before the not preemptible task. This made the
RTEMS_NO_PREEMPT mode ineffective.
Remove the PRIORITY_PSEUDO_ISR special case logic. This simplifies the
uniprocessor schedulers. Move the uniprocessor-specific scheduler support to
the new header file <rtems/score/scheduleruniimpl.h>.
Close#2365.
The build option definitions were rearranged such that the option
definitions used in the linker script were not available. This caused
linker errors when building.
Sort the .noinit* input sections by name first, then by alignment if two
sections have the same name. This allows the placement of begin/end symbols to
initialize some areas with a special value.
Update #4678.
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
Add BSP options which define the initial values of CPU Interface registers.
There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.
The compiler wraps fork(), etc. system calls if coverage generation is enabled.
These functions must be provided by the system. For RTEMS, they just return an
error status.
Update #4670.
Allow separate optimization flags for the BSP, cpukit, and tests. For example,
the BSP and cpukit may be built without optimization if coverage
instrumentation is enabled, however, the tests may still use optimization.
Update #4670.
