Commit Graph

8 Commits

Author SHA1 Message Date
Sebastian Huber
44fbca379a bsps/arm: Simplify L1 caches support
Delete superfluous/incorrect interrupt disable/enable.
2014-06-05 14:55:16 +02:00
Ralf Kirchner
62fa1ea25e bsp/arm: Add cache size methods
Add new methods which deliver the cache sizes of for supported cache levels.
2014-04-17 13:25:12 +02:00
Ralf Kirchner
bebcfa57a8 bsp/arm: Remove unused cache store methods 2014-04-17 13:25:12 +02:00
Ralf Kirchner
db5a84d0ad bsp/arm: Correct cache misalignment handling
Correct misalignment handling and prepare for locking.
2014-04-17 13:25:11 +02:00
Ralf Kirchner
9ee2ec56b5 bsp/arm: Consistenly same handling for flushing
It is importeant to consistently apply the same handling for flushing within
level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
2014-04-17 13:25:11 +02:00
Ralf Kirchner
e331e69a47 bsp/arm: RTEMS_SMP to arm erratum 764369 detection
Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
2014-04-17 13:25:11 +02:00
Ralf Kirchner
924b47a548 bsp/arm: Cleanup L1 cache 2014-04-17 13:25:10 +02:00
Ralf Kirchner
9fcd1b3556 bsp/arm: Add handling for level 2 L2C-310 cache controller
arm-l2c-310/cache_.h contains the handling for the L2C-310
level 2 cache controller from arm. It references the arm
level 1 cache handling in the new file arm-cache-l1.h.
2014-03-13 16:10:54 +01:00