Commit Graph

230 Commits

Author SHA1 Message Date
Mohd Noor Aman
b57c6541a1 bsp/aarch64: Add new Raspberry Pi 4B BSP
This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently
only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in
64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry
Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM
BSP.

Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently.
Mini-UART is not supported. Mini-UART is default UART on the board so it needs
to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support
for additional 4 PL011-UARTs on the board.

The raspberrypi.h includes many of the address required for the future
development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore
Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
2022-10-04 17:04:44 -05:00
Padmarao Begari
6b0d3c9873 bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
2022-09-20 12:00:51 -05:00
Padmarao Begari
974c6ea9d6 spec/build/bsps: Add dtb support
Add dtb and dtb header path configurable build option
2022-09-20 12:00:51 -05:00
Sebastian Huber
63cf583365 bsp/tms570: Fix TMS570_USE_HWINIT_STARTUP
Make sure only one module is built which defines bsp_start_hook_0().
2022-09-20 10:35:06 +02:00
Sebastian Huber
9a55120420 bsp/tms570: Add -mbe32 to LINKFLAGS
There is not just big-endian on ARM.  We have two variants BE32
(obsolete) and BE8.  The Cortex-R5F processor supports only BE8,
however, some TMS570 variants are BE32 internally.  In GCC 8 and later,
the --be8 option is passed to the linker based on the selected
architecture or CPU.  Use BE32 by default for the TMS570 BSP.

In GCC, see:

commit 63d03dcecdafe34715282a5155cfc2162375feca
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Mon Jul 3 13:22:05 2017 +0000

     [arm] Clean up generation of BE8 format images.
2022-09-20 10:34:35 +02:00
Sebastian Huber
52d566c864 bsp/qoriq: Enable VRSAVE optimization
Close #4712.
2022-09-08 15:54:23 +02:00
Martin Aberg
9ec9be834d bsp/riscv: Add NOEL-V BSP
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
  https://www.gaisler.com/NOELV

Compatible with the following NOEL-V FPGA example design ranges
available from Cobham Gaisler. Follow the links for free
bit-streams, DTS/DTB, user's manuals and quick-start guides:
- NOEL-ARTYA7-EX    (https://www.gaisler.com/NOEL-ARTYA7)
- NOEL-PF-EX        (https://www.gaisler.com/NOEL-PF)
- NOEL-XCKU-EX      (https://www.gaisler.com/NOEL-XCKU)

Uses the shared GRLIB APBUART console driver "apbuart_termios.c".
APBUART devices are probed using device tree.

Closes #4225.
2022-09-06 16:15:58 +02:00
Daniel Cederman
ca07efd571 bsp/riscv: Work area size based on /memory node in fdt
Uses the first entry in the /memory node to determine the end of the
work area. Falls back on linker symbol if unable to parse the node.
2022-09-06 15:51:58 +02:00
Chris Johns
a3b0f7d5a8 bsps/xilinx/versal: Add Cadence I2C driver support 2022-08-25 09:25:03 +10:00
Stephen Clark
c738be92a0 bsps/amd64: remove -Werror from ABI flags
The ABI flags for the amd64 BSP contain the -Werror=return-type flag. There is no reason for this to be there so it has been removed. The same option has also been removed amd64.cfg file.
2022-08-23 11:37:21 -05:00
Chris Johns
dee5ea8147 bsps/xilinx/versal: Remove IPL32 BSPs, add aiedge and change defaults
- Versal has IO mapped to the upper 64bit address space and
  needs full 64bit addresses.

- Add xilinx_versal_aiedge for custom hardware

- Make the hardware settings the defaults and qemu as variants

Closes #4693
2022-08-23 07:55:25 +10:00
Chris Johns
e49a1c9b38 spec/bsps: Do not install tm27.h
Updates #4705
2022-08-22 08:30:00 +10:00
Chris Johns
51ffa21011 aarch64/versal: Support DDRMC0 region 0 and 1
- Support DDRMC0 region 0 up to 2G in size

- Support DDRMC0 region 1 with DDR memory greater than 2G
  up to the DDRMC0 max amount

- Extend the heap with region 1's memory

Closes #4684
2022-07-28 09:04:46 +10:00
Sebastian Huber
4f94d47bc5 build: Move RISCV_MAXIMUM_EXTERNAL_INTERRUPTS 2022-07-26 13:38:33 +02:00
Alex White
c0a4d56b16 bsps/microblaze: Fix build option definition order
The build option definitions were rearranged such that the option
definitions used in the linker script were not available. This caused
linker errors when building.
2022-07-25 09:01:51 -05:00
Sebastian Huber
25ccc19ae9 bsps/riscv: Sort .noinit* sections
Sort the .noinit* input sections by name first, then by alignment if two
sections have the same name.  This allows the placement of begin/end symbols to
initialize some areas with a special value.

Update #4678.
2022-07-20 08:46:13 +02:00
Sebastian Huber
5cc075712e irq/arm-gicv3.h: Customize CPU Interface init
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers.  This fixes the build for the AArch32 target.

Add BSP options which define the initial values of CPU Interface registers.
2022-07-12 08:26:46 +02:00
Kinsey Moore
2f6ee01e9e bsps/aarch64: Use MMU pages appropriately
There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.
2022-07-06 10:22:08 -05:00
Sebastian Huber
5c13a96f36 build: Add RTEMS_GCOV_COVERAGE option
Update #4670.
2022-07-04 08:29:52 +02:00
Sebastian Huber
a13047ca0e build: Allow separate optimization flags
Allow separate optimization flags for the BSP, cpukit, and tests.  For example,
the BSP and cpukit may be built without optimization if coverage
instrumentation is enabled, however, the tests may still use optimization.

Update #4670.
2022-07-04 08:29:52 +02:00
Sebastian Huber
a0aaa394b6 build: Fix optimization flags definition order
OPTIMIZATION_FLAGS must be defined before /build/bsp/bspopts is processed.

Update #4670.
2022-07-04 08:29:52 +02:00
Sebastian Huber
42da08dd9d build: Add cppflags, cflags, cxxflags to groups
Propagate the group defined cppflags, cflags, and cxxflags from parent groups
to child items through the build item context.

Update #4670.
2022-07-04 08:29:52 +02:00
Sebastian Huber
281f39a600 build: Move BSP_INCLUDES split
The goal is to let the build items define as much as possible.
2022-07-04 08:29:52 +02:00
Sebastian Huber
050eaa92ef bsp/stm32h7: Exclude some tests 2022-06-24 13:19:57 +02:00
Sebastian Huber
fea5ed5e7d bsp/rtl22xx: Exclude exit03 2022-06-24 13:15:00 +02:00
Sebastian Huber
58b31af20b tstsmallmem: Exclude exit03 and tftpfs 2022-06-24 13:15:00 +02:00
Chris Johns
4f6c90f40d bsps/versal: Support a 64bit RAM base
Set the constraint to be 64bits to allow the complete address range.
2022-06-16 10:21:46 +10:00
Christian Mauderer
b60d8327ac bsps/atsam: Fix type of options (part 2)
The patch "bsps/atsam: Fix type of options" missed to adapt some parts
of the yml. With that a custom value works well. But if no value is set,
configure doesn't fall back to the default value but instead just causes
an error. This patch fixes that.
2022-06-14 08:14:39 +02:00
Karel Gardas
ae2367c505 bsps/stm32h7: remove external memory initialization from nucleo-h743zi BSP
Nucleo board does not provide any external memory so code does not have
any function here anyway.

Sponsored-By:	Precidata
2022-06-10 11:17:17 +02:00
Karel Gardas
e5e1c00491 bsps/stm32h7: move BSP start hooks into boards subdirectories
The idea here is to prepare for better per-board specialization
of the hooks function code.

Sponsored-By:	Precidata
2022-06-10 11:17:17 +02:00
Karel Gardas
d7f3918d13 bsps/arm: fix installation of core_cm4.h 2022-06-10 11:15:08 +02:00
Christian Mauderer
7ba1503661 bsps/imx: Enable clock of ETH2 2022-06-09 09:04:40 +02:00
Christian Mauderer
8beb1d2fb0 bsps/atsam: Fix type of options
ATSAM_CONSOLE_DEVICE_INDEX and ATSAM_CONSOLE_DEVICE_TYPE have to be
integers like suggested by their description. Otherwise it's not
possible to select (for example) USART2 as console device.
2022-06-07 08:31:26 +02:00
Karel Gardas
c3ad1e3c27 bsps/stm32h7: set SDRAM 1 size to 0 by default on nucleo-h743zi BSP
Nucleo does not have any SDRAM, so 0 size is the only possible right
choice here.

Sponsored-By:	Precidata
2022-06-02 10:44:30 +02:00
Karel Gardas
925bcdb8e8 bsps/stm32h7: set default linkage to flash for nucleo-h743zi BSP
Nucleo does not have any SDRAM so default linkage to SDRAM does not make
any sense here.

Sponsored-By:	Precidata
2022-06-02 10:44:30 +02:00
Karel Gardas
5a1f87a071 bsps/stm32h7: set default printk instance on nucleo-h743zi BSP to USART3
This is the default configuration of the board out of the box.
Any other possible/supported configuration requires soldering,
so definitely not out of the box experience.

Sponsored-By:	Precidata
2022-06-02 10:44:30 +02:00
Karel Gardas
f2cf15b82a bsps/stm32h7: add stm32h747i-disco-m4 BSP variant
This patch adds stm32h747i-disco-m4 BSP variant and puts it in sync
with the stm32h747i-disco BSP variant hardware support. That means,
only USART 1, 2 and UART 8 are enabled. Also SDRAM 2 is set to 32MB,
SDRAM 1 size is set to 0.

Sponsored-By:	Precidata
2022-06-02 10:44:30 +02:00
Karel Gardas
8604b46ab6 bsps/stm32h7: set default SDRAM x sizes on stm32h747i-disco BSP
This means:

SDRAM 1: 0
SDRAM 2: 32 MB

Sponsored-By:	Precidata
2022-06-01 15:49:19 +02:00
Karel Gardas
587ce75111 bsps/stm32h7: disable all unsupported U(S)ARTs on stm32h747i-disco BSP
This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors. That means only USART1 and 2
and UART8 are enabled.

Sponsored-By:	Precidata
2022-06-01 15:49:19 +02:00
Karel Gardas
8abb339640 bsps/stm32h7: add configuration and enable build of stm32h747i-disco BSP
Sponsored-By:	Precidata
2022-06-01 15:49:19 +02:00
Karel Gardas
04fd4ef2b6 bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval-m4 BSP
This means:

SDRAM 1: 0
SDRAM 2: 32 MB

Sponsored-By:   Precidata
2022-06-01 11:20:59 +02:00
Karel Gardas
30b2ad318b bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval-m4 BSP
This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors.

Sponsored-By:   Precidata
2022-06-01 11:20:59 +02:00
Karel Gardas
250254ff8f bsps/stm32h7: add configuration and enable build of stm32h757i-eval-m4 BSP
This is minimalist configuration for the stm32h757i-eval-m4 BSP provided
here. The only general enhancement worth mention is a flash origin address
configuration which is needed for simplification as M4 core boots
from second flash bank which starts at 0x8100000 by default. The boot
address of the core may be changed by using STM32CubeProgrammer. If done
so then also BSP configuration needs to be changed accordingly.

As the BSP variant is running on M4 core, there is also more configuration
changes required here. E.g. boot core and ABI (compilation flags)
in comparison with stm32h757i-eval BSP. On the other hand, C code is shared
completely with this BSP variant.

Sponsored-By:   Precidata
2022-06-01 11:20:59 +02:00
Karel Gardas
bdfc8d8f4d bsps/stm32h7: move cache implementation from obj to BSPs own yml file
This is done in preparation for future Cortex-M4 based BSP variants
which do not provide cache at all.

Sponsored-By:	Precidata
2022-06-01 11:20:59 +02:00
Karel Gardas
186c891182 bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval BSP
This means:

SDRAM 1: 0
SDRAM 2: 32 MB

Sponsored-By:	Precidata
2022-05-27 20:17:32 +02:00
Karel Gardas
42ed4a6338 bsps/stm32h7: provide linkcmds for SRAM, FLASH_SDRAM and SRAM_SDRAM linking
Sponsored-By:	Precidata
2022-05-27 20:17:32 +02:00
Karel Gardas
3aab95f3a7 bsps/stm32h7: add and enable test set exclusion for stm32h757i-eval BSP
Sponsored-By:	Precidata
2022-05-27 20:17:32 +02:00
Karel Gardas
1ea6540c62 bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval BSP
This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors.

Sponsored-By:	Precidata
2022-05-27 20:17:32 +02:00
Karel Gardas
124912445c bsps/stm32h7: add configuration and enable build of stm32h757i-eval BSP
This is minimalist configuration for the stm32h757i-eval BSP provided
here. The only general enhancement worth mention is boot core
configuration which is needed here as this is the first dual-core board
supported by stm32h7 BSP family and we need to choose boot core in order
to get C files compiling well.

Sponsored-By:	Precidata
2022-05-27 20:17:32 +02:00
Karel Gardas
31f756b07c bsp/stm32h7: copy system files to nucleo-h743zi board directory
Also adjust BSP spec file to make it buildable with board files.

Sponsored-By:	Precidata
2022-05-16 10:23:27 +02:00