RTOS/rtems
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Code Pull Requests Activity
34,456 Commits 7 Branches 54 Tags
32f5a195d79ecf49e9b464d3358dd4739ae82203
Commit Graph

19 Commits

Author SHA1 Message Date
Sebastian Huber
32f5a195d7 bsps/irq: bsp_interrupt_vector_disable() 
Return a status code for bsp_interrupt_vector_disable().

Update #3269.
 2021-07-26 19:57:31 +02:00
Sebastian Huber
bc86a5fa84 bsps/irq: bsp_interrupt_vector_enable() 
Return a status code for bsp_interrupt_vector_enable().

Update #3269.
 2021-07-26 19:57:30 +02:00
Sebastian Huber
deb5afb2f2 bsps/irq: Add rtems_interrupt_is_pending() 
Add a default implementation which just returns RTEMS_UNSATISFIED.

Update #3269.
 2021-07-26 17:08:42 +02:00
Sebastian Huber
eebecd09fa bsps/irq: Add rtems_interrupt_get_attributes() 
Add a default implementation which clears the attributes to zero and
just returns RTEMS_SUCCESSFUL for valid parameters.

Update #3269.
 2021-07-26 17:08:42 +02:00
Sebastian Huber
9832652c53 bsps/irq: Add rtems_interrupt_raise() 
Add rtems_interrupt_raise_on() and rtems_interrupt_clear().

Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.

Update #3269.
 2021-07-26 07:54:25 +02:00
Sebastian Huber
781213f9ec bsps/irq: Add rtems_interrupt_vector_is_enabled() 
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.

Update #3269.
 2021-07-26 07:54:25 +02:00
Sebastian Huber
f2b0877642 bsps: Fix GICv3 support for AArch32 
The GICv3 support is shared between AArch32 and AArch64.  For AArch32,
the new AARCH64_IS_NONSECURE is never defined.  Use ARM_MULTILIB_ARCH_V4
instead.

This issue was introduced by 76c6caad52.

There is still a change in bsp_interrupt_vector_enable() for AArch32
compared to the version before 76c6caad52.
 2021-06-30 16:28:52 +02:00
Gedare Bloom
76c6caad52 bsps/aarch64: add non-secure mode and versal support 2021-06-24 09:37:31 -06:00
Gedare Bloom
bcad0aaee6 bsps/aarch64: add mnemonic for ICC_IGRPEN1_EL3 2021-06-24 09:37:31 -06:00
Sebastian Huber
9f3a08ef2d bsps: Use header file for GIC architecture support 
This avoids a function call overhead in the interrupt dispatching.

Update #4202.
 2020-12-23 09:24:49 +01:00
Sebastian Huber
39ef7e5496 bsps: Fix includes 
Update #4202.
 2020-12-22 13:02:41 +01:00
Sebastian Huber
b5aceef5d9 bsps: Remove gicvx_interrupt_dispatch() 
Avoid one level of indirection.

Update #4202.
 2020-12-16 11:00:03 +01:00
Sebastian Huber
747fb65c6e bsps: Add GICv3 arm_gic_irq_processor_count() 
Update #4202.
 2020-12-16 11:00:03 +01:00
Kinsey Moore
9edca35dbe bsps/gicv3: Resolve build warnings on 64bit 2020-12-11 15:32:15 -06:00
Sebastian Huber
105e52032e bsps: Remove ARM GIC SGI target filter 
Remove the target filter for software-generated interrupts since this
feature is not supported by the affinity routing in GICv3.

Update #4202.
 2020-12-10 09:42:50 +01:00
Sebastian Huber
b6925e10c8 bsps: Fix GICv3 arm_gic_trigger_sgi() 
Use the targets parameter to determine the targets of the SGI.  Change
targets parameter type to 32-bit to ease the parameter passing.  GICv3
supports up to 16 targets.

Update #4202.
 2020-12-10 09:42:49 +01:00
Sebastian Huber
9ce47a52a4 bsps: Add SMP support to ARM GICv3 
Update #4202.
 2020-12-09 17:30:52 +01:00
Kinsey Moore
a151ee167e bsps: Move ARM GICv2 driver to bsps/shared 
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
 2020-12-02 18:51:40 -06:00
Kinsey Moore
f8ad5bb2a4 bsps: Break out AArch32 GICv3 support 
This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
 2020-10-05 16:11:39 -05:00