If the bsp is integrated and supported a device tree
blob(dtb) then use dtb instead of using it from
the U-Boot (BSP_START_COPY_FDT_FROM_U_BOOT=False).
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Add the basic Microchip PolarFire SoC device tree source and blob
The mpfs-dtb.h is generated by the bin2hex
https://github.com/padmaraob/bin2hex
1.Compile and build the bin2hex.c
$ gcc -o bin2hex bin2hex.c
2.Generate the mpfs.dtb from the mpfs.dts
$ dtc -O dtb -o mpfs.dtb mpfs.dts
3.Generate the mpfs-dtb.h Header file from the mpfs.dtb.
$ ./bin2hex mpfs.dtb
There is not just big-endian on ARM. We have two variants BE32
(obsolete) and BE8. The Cortex-R5F processor supports only BE8,
however, some TMS570 variants are BE32 internally. In GCC 8 and later,
the --be8 option is passed to the linker based on the selected
architecture or CPU. Use BE32 by default for the TMS570 BSP.
In GCC, see:
commit 63d03dcecdafe34715282a5155cfc2162375feca
Author: Richard Earnshaw <rearnsha@arm.com>
Date: Mon Jul 3 13:22:05 2017 +0000
[arm] Clean up generation of BE8 format images.
Note: Resending after learning how to use git send-email, please disregard previous message.
This fixes the riscv fe310 console driver fe310_uart_read function. The function
reads the RX status/data register to check if data is available, but discards
the data and reads it a seconds time.
Also cleared the interrupt enable bit in the first_open function.
Close#4719
All CPU ports used the same _CPU_Counter_difference() implementation. Remove
this CPU port interface and mandate a monotonically increasing CPU counter.
Close#3456.
context after they are finialized after r336539, so do not do it.
Submitted by: David CARLIER <devnexen gmail com>
MFC after: 1 month (after r336539)
Differential Revision: https://reviews.freebsd.org/D16059
copied_key and copied_salt are assigned with NULL and never used
otherwise. Remove the two variables and related code.
Reviewed by: pfg
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D16314
Mainly focus on files that use BSD 2-Clause license, however the tool I
was using mis-identified many licenses so this was mostly a manual - error
prone - task.
The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
Mainly focus on files that use BSD 3-Clause license.
The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.
and when doing it, consistently use explicit_bzero().
Update manual pages to match the behavior.
Reviewed by: pfg, allanjude, jmg
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D16316
C99 allows array function parameters to use the static keyword for their
sizes. This tells the compiler that the parameter will have at least the
specified size, and calling code will fail to compile if that guarantee is
not met. However, this syntax is not legal in C++.
This commit reverts r300824, which worked around the problem for
sys/sys/md5.h only, and introduces a new macro: min_size(). min_size(x) can
be used in headers as a static array size, but will still compile in C++
mode.
Reviewed by: cem, ed
MFC after: 4 weeks
Sponsored by: Spectra Logic Corp
Differential Revision: https://reviews.freebsd.org/D8277
with more ILP and a preference for memory load instructions over large code
footprints with embedded immediate variables.
On amd64 CPUs from 2007-2008 there is not a significant change, but
amd64 CPUs from 2009-2010 get roughly 10% more throughput with this
code; amd64 CPUs from 2011-2012 get roughly 15% more throughput; and
AMD64 CPUs from 2013-2015 get 20-25% more throughput. The Raspberry
Pi 2 increases its throughput by 6-8%.
Sponsored by: Tarsnap Backup Inc.
Performance tested by: allanjude
MFC after: 3 weeks
This implements SHA-512/256, which generates a 256 bit hash by
calculating the SHA-512 then truncating the result. A different initial
value is used, making the result different from the first 256 bits of
the SHA-512 of the same input. SHA-512 is ~50% faster than SHA-256 on
64bit platforms, so the result is a faster 256 bit hash.
The main goal of this implementation is to enable support for this
faster hashing algorithm in ZFS. The feature was introduced into ZFS
in r289422, but is disconnected because SHA-512/256 support was missing.
A further commit will enable it in ZFS.
This is the follow on to r292782
Reviewed by: cem
Sponsored by: ScaleEngine Inc.
Differential Revision: https://reviews.freebsd.org/D6061
Use the C99 'static' keyword to hint to the compiler IVs and output digest
sizes. The keyword informs the compiler of the minimum valid size for a given
array. Obviously not every pointer can be validated (i.e., the compiler can
produce false negative but not false positive reports).
No functional change. No ABI change.
Sponsored by: EMC / Isilon Storage Division
cperciva's libmd implementation is 5-30% faster
The same was done for SHA256 previously in r263218
cperciva's implementation was lacking SHA-384 which I implemented, validated against OpenSSL and the NIST documentation
Extend sbin/md5 to create sha384(1)
Chase dependancies on sys/crypto/sha2/sha2.{c,h} and replace them with sha512{c.c,.h}
Reviewed by: cperciva, des, delphij
Approved by: secteam, bapt (mentor)
MFC after: 2 weeks
Sponsored by: ScaleEngine Inc.
Differential Revision: https://reviews.freebsd.org/D3929
The VRSAVE feature of the Altivec unit can be used to reduce the amount of
Altivec registers which need to be saved/restored during interrupt processing
and context switches.
In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is
required, see GCC configuration. The -mvrsave option must be added to the
ABI_FLAGS of the BSP.
Currently only the -mcpu=e6500 based QorIQ BSP support this optimization.
Update #4712.
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the following NOEL-V FPGA example design ranges
available from Cobham Gaisler. Follow the links for free
bit-streams, DTS/DTB, user's manuals and quick-start guides:
- NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7)
- NOEL-PF-EX (https://www.gaisler.com/NOEL-PF)
- NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU)
Uses the shared GRLIB APBUART console driver "apbuart_termios.c".
APBUART devices are probed using device tree.
Closes#4225.
Issue an error message if an SMP-specific scheduler is used and
RTEMS_SMP is disabled. This might be a more informative compared to
compiler or linker errors.
