A new option RTEMS_INTERRUPT_REPLACE is introduced that permits updating
the first interrupt handler for the registered interrupt vector and
matching argument. If no match is found, the install function fails
with RTEMS_UNSATISFIED.
The Interrupt Manager Extension offers interrupt handlers with an
argument pointer. It is impossible to update two words (handler and
argument) atomically on most architectures. In order to avoid an SMP
lock in bsp_interrupt_handler_dispatch() which would degrade the
interrupt response time an alternative must be provided that makes it
possible to tear-down interrupt sources without an SMP lock.
Add RTEMS_INTERRUPT_REPLACE option to Interrupt Manager Extension. This
enables a clean tear-down of interrupt sources on SMP configurations.
Instead of an interrupt handler removal a replacement handler can be
installed to silence an interrupt source. This can be used in contexts
that allow no sophisticated synchronization (e.g. in atexit() or fatal
handlers).
Rename _SMP_Request_other_cores_to_perform_first_context_switch() into
_SMP_Request_start_multitasking() since this requests now a multitasking
start on all configured and available processors. The name corresponds
_Thread_Start_multitasking() and
_SMP_Start_multitasking_on_secondary_processor() actions issued in
response to this request. Move in source file to right place.
Rename PER_CPU_STATE_READY_TO_BEGIN_MULTITASKING into
PER_CPU_STATE_READY_TO_START_MULTITASKING.
Rename PER_CPU_STATE_BEGIN_MULTITASKING into
PER_CPU_STATE_REQUEST_START_MULTITASKING.
Rename _SMP_Request_other_cores_to_shutdown() into
_SMP_Request_shutdown().
Add a per-CPU state lock to protect all changes. This was necessary to
offer a controlled shutdown of the system (atomic read/writes alone are
not sufficient for this kind of synchronization).
Add documentation for Per_CPU_State.
Delete debug output.
New tests smptests/smpfatal01 and smptests/smpfatal02.
The previous implementation used an instruction cache line size of 0,
this is a bogus value. Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64. A greater value should
cause no harm.
Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().
This is a preperation step to support the L2 cache.
The SPARC processors supported by RTEMS have no built-in CPU counter
support. We have to use some hardware counter module for this purpose.
The BSP must provide a 32-bit register which contains the current CPU
counter value and a function for the difference calculation. It can use
for example the GPTIMER instance used for the clock driver.
The 32-bit ABIs for thread-local storage (TLS) and EABI read-only
small-data area have a conflicting register (r2) usage. Use the System
V small-data instead (here r2 is system reserved).
Remove RTEMS_COMPILER_PURE_ATTRIBUTE from _SMP_Get_current_processor()
and all _CPU_SMP_Get_current_processor(). Make inline ASM statements
volatile again. Test smptests/smpmigration01 showed that GCC optimizes
too much otherwise.
Wait for per-CPU changes into PER_CPU_STATE_READY_TO_BEGIN_MULTITASKING
later. There is no need to delay the initialization of the main
processor at this point.
Since the per-CPU SMP lock must be acquired and released to send the
message a single interrupt broadcast operations offers no benefits. If
synchronization is required, then a SMP barrier must be used anyway.
