Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
According with comment in
rtems_cache_invalidate_multiple_instruction_lines(), final_address
indicates the last address which needs to be invalidated. But if in
while loop we got final_address == i_addr condition then loop breaks and
final_address will not be invalidated.
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
* shared/src/cache_manager.c
(rtems_cache_invalidate_multiple_instruction_lines): If
CPU_INSTRUCTION_CACHE_ALIGNMENT is defined but 0, then there is
an instruction cache but no notion of line size.
* shared/src/cache_manager.c (rtems_cache_flush_multiple_data_lines,
rtems_cache_invalidate_multiple_data_lines): Do not operate on the
entire address space when flushing zero bytes.
now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.
