Add a local context structure to the SMP lock API for acquire and
release pairs. This context can be used to store the ISR level and
profiling information. It may be later used to enable more
sophisticated lock algorithms, e.g. MCS locks.
There is only one lock that cannot be used with a local context. This
is the per-CPU lock since here we would have to transfer the local
context through a context switch which is very complicated.
Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
ISR locks are low-level locks to protect critical sections accessed by
threads and interrupt service routines.
On single processor configurations the ISR locks degrade to simple ISR
disable/enable sequences. No additional storage or objects are
required.
This synchronization primitive is supported on SMP configurations. Here
SMP locks are used.
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
This PR was about a warning for no previous prototype for
rtems_interrupt_level_attribute. This method exists (like
a few others) to have real bodies for Classic API services
implemented as macros. These macros are not available from
anything but C and C++. The most explicit use was in the Ada
binding but these would be needed from assembly language
or any other non-C based language.
On top of needing a prototype, the methods were misnamed.
They were related to modes. This renames them, moves the
file, fixes test code, etc.
* sp28/init.c: Corrections to configuration.
* sp37/init.c: Correctly invoke rtems_interrupt_disable() body.
* spsize/size.c: _ISR_Vector_table only exists on architectures
which use the Simple Vectored Interrupt Model.
* sp09/screen07.c, sp09/sp09.scn: Add test for
rtems_message_queue_broadcast for bad buffer and count pointers.
* sp30/init.c, sp30/sp30.scn: Add test for initiating timer server
with bad priority or initiating twice.
* sp37/sp37.scn, sp37/system.h: Add test for rtems_clock_tick when
it forces a dispatch.
* sp37/init.c: New file.
* Makefile.am, configure.ac: Add new tests for interrupt disable,
enable, flash, and is in progress. These are normally inlines but
also have bodies for non-C code. This test also exercises the odd
case of calling clock tick from outside an ISR.
* sp37/.cvsignore, sp37/Makefile.am, sp37/sp37.scn, sp37/system.h: New files.
