Since the per-CPU SMP lock must be acquired and released to send the
message a single interrupt broadcast operations offers no benefits. If
synchronization is required, then a SMP barrier must be used anyway.
Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC
into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to
figure out the code position given a fatal source and code.
Instead of SPRG0 (= special purpose register 272) use the new global
symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask.
The benefit is that it is now possible to disable interrupts without
further run-time initialization in boot_card().
At least on Freescale e500 cores this leads also to a faster execution
since the mfmsr and mfspr instruction require four cycles to complete.
The instructions to load the mask value can execute while the mfmsr is
in progress.
Add a CPU counter interface to allow access to a free-running counter.
It is useful to measure short time intervals. This can be used for
example to enable profiling of critical low-level functions.
Add two busy wait functions rtems_counter_delay_ticks() and
rtems_counter_delay_nanoseconds() implemented via the CPU counter.
Rename rtems_internal_error_description() to
rtems_internal_error_text(). Rename rtems_fatal_source_description() to
rtems_fatal_source_text(). Rename rtems_status_code_description() to
rtems_status_text(). Remove previous implementation of
rtems_status_text().
The _CPU_Context_switch() is a normal function call. The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5. Drop these registers from the context.
Ensure that offset defines match the structure offsets.
Use the Global Timer for the Cortex-A9 MPCore clock driver instead of
the Private Timer. This enables a consistent nanoseconds since last
context switch value across all processors.
Install inter-processor interrupt (IPI) handler before secondary CPUs
are started. This ensures that secondary CPUs fetch the newly installed
handler.
Remove superfluous return statement.
Generate a linker command file from configure letting the user override the
defaults to suite their custom needs. Refer to configure.ac for the details.
Remove the SMP variants and let --enable-smp control if a BSP is built for
SMP.
Make USE_FAST_IDLE 1 only for the realview qemu BSP.
