The NOR driver was not written with SMP systems and caching in mind.
This makes the IsBusy flag volatile for updates across cores and
introduces cache flushing and invalidation where necessary for data
manipulated by the DMA engine in the QSPI peripheral.
This change causes NOR writes to be broken according to page boundaries.
Writes across page boundaries cause the writes beyond the boundary to
fail silently. This also introduces a new function that will explicitly
write pages.
This adds helper functions for working with NOR flash connected to the
Xilinx GQSPI controller. The helper functions are based on Xilinx's
QSPIPSU flash interrupt example.
This adds Xilinx's driver for the Xilinx GQSPI controller embedded in
the ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files
are and should be able to remain unmodified. Import information is kept
in bsps/shared/dev/spi/VERSION.
