Add a local context structure to the SMP lock API for acquire and
release pairs. This context can be used to store the ISR level and
profiling information. It may be later used to enable more
sophisticated lock algorithms, e.g. MCS locks.
There is only one lock that cannot be used with a local context. This
is the per-CPU lock since here we would have to transfer the local
context through a context switch which is very complicated.
This partially reverts commit 1215fd4d94.
In order to support profiling of SMP locks and provide a future
compatible SMP locks API it is necessary to add an SMP lock destroy
function. Since the commit above adds an SMP lock to each chain control
we would have to add a rtems_chain_destroy() function as well. This
complicates the chain usage dramatically. Thus revert the patch above.
A global SMP lock for all chains is used to implement the protected
chain operations.
Advantages:
* The SAPI chain API is now identical on SMP and non-SMP
configurations.
* The size of the chain control is reduced and is then equal to the
Score chains.
* The protected chain operations work correctly on SMP.
Disadvantage:
* Applications using many different chains and the protected operations
may notice lock contention.
The chain control size drop is a huge benefit (SAPI chain controls are
66% larger than the Score chain controls). The only disadvantage is not
really a problem since these applications can use specific interrupt
locks and unprotected chain operations to avoid this issue.
A new option RTEMS_INTERRUPT_REPLACE is introduced that permits updating
the first interrupt handler for the registered interrupt vector and
matching argument. If no match is found, the install function fails
with RTEMS_UNSATISFIED.
The Interrupt Manager Extension offers interrupt handlers with an
argument pointer. It is impossible to update two words (handler and
argument) atomically on most architectures. In order to avoid an SMP
lock in bsp_interrupt_handler_dispatch() which would degrade the
interrupt response time an alternative must be provided that makes it
possible to tear-down interrupt sources without an SMP lock.
Add RTEMS_INTERRUPT_REPLACE option to Interrupt Manager Extension. This
enables a clean tear-down of interrupt sources on SMP configurations.
Instead of an interrupt handler removal a replacement handler can be
installed to silence an interrupt source. This can be used in contexts
that allow no sophisticated synchronization (e.g. in atexit() or fatal
handlers).
The previous implementation used an instruction cache line size of 0,
this is a bogus value. Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64. A greater value should
cause no harm.
Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().
This is a preperation step to support the L2 cache.
The SPARC processors supported by RTEMS have no built-in CPU counter
support. We have to use some hardware counter module for this purpose.
The BSP must provide a 32-bit register which contains the current CPU
counter value and a function for the difference calculation. It can use
for example the GPTIMER instance used for the clock driver.
The 32-bit ABIs for thread-local storage (TLS) and EABI read-only
small-data area have a conflicting register (r2) usage. Use the System
V small-data instead (here r2 is system reserved).
Since the per-CPU SMP lock must be acquired and released to send the
message a single interrupt broadcast operations offers no benefits. If
synchronization is required, then a SMP barrier must be used anyway.
Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC
into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to
figure out the code position given a fatal source and code.
Instead of SPRG0 (= special purpose register 272) use the new global
symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask.
The benefit is that it is now possible to disable interrupts without
further run-time initialization in boot_card().
At least on Freescale e500 cores this leads also to a faster execution
since the mfmsr and mfspr instruction require four cycles to complete.
The instructions to load the mask value can execute while the mfmsr is
in progress.
Add a CPU counter interface to allow access to a free-running counter.
It is useful to measure short time intervals. This can be used for
example to enable profiling of critical low-level functions.
Add two busy wait functions rtems_counter_delay_ticks() and
rtems_counter_delay_nanoseconds() implemented via the CPU counter.
Rename rtems_internal_error_description() to
rtems_internal_error_text(). Rename rtems_fatal_source_description() to
rtems_fatal_source_text(). Rename rtems_status_code_description() to
rtems_status_text(). Remove previous implementation of
rtems_status_text().
The _CPU_Context_switch() is a normal function call. The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5. Drop these registers from the context.
Ensure that offset defines match the structure offsets.
Use the Global Timer for the Cortex-A9 MPCore clock driver instead of
the Private Timer. This enables a consistent nanoseconds since last
context switch value across all processors.
