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9,397 Commits 7 Branches 54 Tags
0cd196b7f9e2fc7b6be6038fbfe7e57aeb7881ed
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5 Commits

Author SHA1 Message Date
Ralf Corsepius
0cd196b7f9 2004-04-02 Ralf Corsepius <ralf_corsepius@rtems.org> 
* clock/clock.S, mongoosev/vectorisrs/vectorisrs.c,
	shared/interrupts/isr_entries.S,
	shared/interrupts/vectorexceptions.c, timer/gettime.S: Include
	<rtems/mips/iregdef.h> instead of <iregdef.h>.
	* clock/clock.S, mongoosev/vectorisrs/vectorisrs.c,
	shared/interrupts/installisrentries.c,
	shared/interrupts/isr_entries.S,
	shared/interrupts/vectorexceptions.c, timer/gettime.S: Include
	<rtems/mips/idtcpu.h> instead of <idtcpu.h>.
 2004-04-03 00:15:56 +00:00
Joel Sherrill
17ed00e431 2002-11-01 Joel Sherrill <joel@OARcorp.com> 
* shared/interrupts/installisrentries.c,
	shared/interrupts/vectorexceptions.c: Removed warnings.
 2002-11-01 21:58:25 +00:00
Joel Sherrill
34f5067fef 2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov> 
* shared/interrupts/installisrentries.c: Added support for debug
	exception vector.
	* shared/interrupts/isr_entries.S: Added support for debug exception
	vector.
 2002-03-08 16:32:39 +00:00
Joel Sherrill
b03f4f2c9d 2001-01-08 Joel Sherrill <joel@OARcorp.com> 
* Added r46xx directory.
	* Makefile.am, configure.in: Modified to reflect addition of r46xx.
	* shared/interrupts/installisrentries.c: Fixed typo.
	* r46xx/.cvsignore, r46xx/Makefile.am,
	r46xx/vectorisrs/.cvsignore, r46xx/vectorisrs/Makefile.am,
	r46xx/vectorisrs/vectorisrs.c: New files.
 2001-01-08 18:11:35 +00:00
Joel Sherrill
b4d0d18eed 2000-12-13 Joel Sherrill <joel@OARcorp.com> 
* shared/.cvsignore, shared/Makefile.am,
	shared/cache/.cvsignore, shared/cache/Makefile.am,
	shared/cache/cache.c, shared/cache/cache_.h,
	shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
	shared/interrupts/installisrentries.c,
	shared/interrupts/isr_entries.S,
	shared/interrupts/maxvectors.c, tx39/.cvsignore,
	tx39/Makefile.am, tx39/include/.cvsignore,
	tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
	Moved some pieces of interrupt processing from score/cpu to
	libcpu/mips since many interrupt servicing characteristics are
	CPU model dependent.  This patch addresses the number of interrupt
	sources and where the ISR prologues are located.  The only way to
	currently install the ISR prologues requires that the prologues
	be installed into RAM.
 2000-12-13 17:52:53 +00:00