Interrupts must be disabled during MMU remapping since the majority of
RTEMS including interrupts expects normal memory mapping semantics such
as unaligned accesses.
The whole cache invalidation and flushing functions only ended up
flusing the first N-1 levels of cache due to an off by one error. This
resovles that issue and makes consistent the usage of levels as they
relate to caching.
To ensure data consistency, the cache much be flushed before disabling
the MMU. When the MMU is disabled, all accesses are treated as
non-cachced and thus will bypass the cache.
The LEON3_Boot_Cpu global object is only used by start.S. Move the definition
of this object to start.S and use a local symbol .Lbootcpuindex for it.
Use a compare-and-swap instruction to assign the boot CPU. This allows a
concurrent initialization.
Close#4845.
This imports the full xil_exception.h instead of an empty stub. This is
required for some Xilinx drivers. The imported files adhere to the
current VERSION file.
This makes xil/sleep.h a stub to prevent multiple differing definitions
of sleep functions from toolchain and local headers. The non-standard
sleep definitions were not in use and can be added later if needed.
The QSPI memory is initialized and used only when the BSP configure file
sets QSPI memory size to non-zero value. Currently QSPI is run in memory
mapped mode which allows future RTEMS binary linkage and upload into QSPI
memory.
Sponsored-By: Precidata
This adds helper functions for working with NOR flash connected to the
Xilinx GQSPI controller. The helper functions are based on Xilinx's
QSPIPSU flash interrupt example.
This adds Xilinx's driver for the Xilinx GQSPI controller embedded in
the ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files
are and should be able to remain unmodified. Import information is kept
in bsps/shared/dev/spi/VERSION.
Low-end configurations may want to have the HTIF support removed.
Enable the option by default. Fix formatting. Fix node validity
checks.
Updates #4779.
Xilinx's upstream ILP32 xil_cache.h header is out of date and broken.
This provides a copy of the LP64 header in place of the ILP32 header
since the LP64 header includes all the correct types to work with either
data model.
The address of the nandpsu peripheral is specific to the ZynqMP SoC and
not relevant to other devices that might have one or more instances of
this peripheral.
This adds Xilinx's driver for the Xilinx NAND controller embedded in the
ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added
to the hardware ZynqMP BSPs since QEMU does not support emulation of
this peripheral. This driver supports polled operation only. The
imported files are and should be able to remain unmodified. Import
information is kept in bsps/shared/dev/nand/VERSION.
This support code is necessary for many Xilinx-provided bare metal device
drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for
all of these architectures is kept under bsps/include due to multiple
architecture variants being supported which requires complex logic in
the build system. The imported files are and should be able to remain
unmodified. Import information is kept in bsps/shared/xil/VERSION.
With the old build system in RTEMS 5 that was possible by just
overwriting BOARD_Sdram_Config and setting a custom
ATSAM_MEMORY_SDRAM_SIZE during building the BSP. In the new build system
that ATSAM_MEMORY_SDRAM_SIZE is set exclusively by the selected SDRAM
chip.
This patch adds the possibility to specify a "custom-0x100000" or
similar as SDRAM type where the number gives the SDRAM size.
A SPI transfer where the Rx or Tx buffer is set to NULL currently
transfers or overwrites data starting from address 0x00000000 via DMA.
This patch changes the DMA setup so that dummy transfers are done.
Just reading / writing to a single location is simpler than changing the
whole logic of the transfer depending on the passed buffers.
Add ref-clock-num identifiers to the device tree to ensure that
interfaces use the correct clocks even when some are not used due to
unconnected MII busses. This also adjusts the default ZynqMP PHY
attachment to RGMII-ID which was the default before device trees were
introduced.
This enables the tracing of interrupt entry/exit events through an
application configuration option. The interrupt processing can be
viewed with Trace Compass using rtems-record-lttng from the RTEMS Tools.
Update #4769.
This fixes build errors seen when building with console interrupts
enabled. A few places were missing bspopts.h includes, and one of the
UART functions was not defined.
