Separate the Interrupt Manager implementation from the generic Arm GICv3
support. Move parts of the Arm GICv3 support into a new header file. This
helps to support systems with a clustered structure in which multiple GICv3
instances are present. For example, two clusters of two Cortex-R52 cores where
each cluster has a dedicated GICv3 instance.
Restrict the affinity set to the set of online processors. Make sure
the affinity set for an interrupt vector contains at least one online
processor.
Update #3269.
Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
The BSPs provide memory for the separate C Program Heap initialization
via _Memory_Get(). Most BSPs provide exactly one memory area. Only two
BSPs provide more than one memory area (arm/altera-cyclone-v and
bsps/powerpc/mpc55xxevb). Only if more than one memory area is
provided, there is a need to use _Heap_Extend(). Provide two
implementations to initialize the separate C Program Heap and let the
BSP select one of the implementations based on the number of provided
memory areas. This gets rid of a dependency on _Heap_Extend(). It
also avoids dead code sections for most BSPs.
Change licence to BSD-2-Clause according to file history.
Update #3053.
The BSPs provide memory for the workspace initialization via
_Memory_Get(). Most BSPs provide exactly one memory area. Only two
BSPs provide more than one memory area (arm/altera-cyclone-v and
bsps/powerpc/mpc55xxevb). Only if more than one memory area is
provided, there is a need to use _Heap_Extend(). Provide two
implementations to initialize the workspace handler and let the BSP
select one of the implementations based on the number of provided memory
areas. This gets rid of a dependency on _Heap_Extend(). It also avoids
dead code sections for most BSPs.
ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
This adds the SMP function that supports spinup of additional CPU cores
using the ARM standard PSCI inteface. This interface is provided by QEMU
as well as ARM Trusted Firmware running in monitor mode (EL3) on ARMv7 and
AArch64 CPUs. This supports activation va SMC or HVC instructions
depending on BSP configuration.
Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well.
Moved these files to shared directory in anticipation of I2C support for ZynqMP.
Do not return a status code in bsp_interrupt_facility_initialize() since this
leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG
assertions in bsp_interrupt_facility_initialize() if necessary.
Add rtems_interrupt_entry_remove(). Split up irq-generic.c into several files.
In particular, place all functions which use dynamic memory into their own
file.
Add optional macros to let the BSP customize the vector installation after
installing the first entry and the vector removal before removing the last
entry:
* bsp_interrupt_vector_install()
* bsp_interrupt_vector_remove()
Use these new customization options in the m68k/genmcf548x BSP so re-use the
generic interrupt controller support.
Update #3269.
Return RTEMS_INCORRECT_STATE instead of RTEMS_INTERNAL_ERROR in case the
interrupt support is not initialized. This is similar to
rtems_timer_server_fire_after() for example.
Update #3269.
Add rtems_interrupt_raise_on() and rtems_interrupt_clear().
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
Add RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT as the fatal source for
spurious interrupts. Use the interrupt vector number of the spurious
interrupt for the fatal code.
Update #3269.
