Commit Graph

24 Commits

Author SHA1 Message Date
Sebastian Huber
03b7789ec7 score: Statically initialize _ISR_Vector_table 2014-04-29 09:51:22 +02:00
Sebastian Huber
7c0bd74c87 sparc: Add _CPU_Get_current_per_CPU_control()
Use register g6 for the per-CPU control of the current processor.  The
register g6 is reserved for the operating system by the SPARC ABI.  On
Linux register g6 is used for a similar purpose with the same method
since 1996.

The register g6 must be initialized during system startup and then must
remain unchanged.

Since the per-CPU control is used in all critical sections of the
operating system, this is a performance optimization for the operating
system core procedures.  An additional benefit is that the low-level
context switch and interrupt processing code is now identical on non-SMP
and SMP configurations.
2014-04-28 09:26:19 +02:00
Sebastian Huber
b2ec2d1597 sparc: Optimize context switch
The registers g2 through g4 are reserved for applications.  GCC uses
them as volatile registers by default.  So they are treated like
volatile registers in RTEMS as well.
2014-04-28 09:26:19 +02:00
Chris Johns
c49985691f Change all references of rtems.com to rtems.org. 2014-03-21 08:10:47 +11:00
Sebastian Huber
de5d6d048d sparc: Add support for interrupt profiling 2014-03-14 08:46:50 +01:00
Sebastian Huber
f4accfd466 bsps/sparc: Remove fix for ERC32 with FPU rev. B/C 2014-03-10 08:03:45 +01:00
Sebastian Huber
ad563618ca sparc: Add LEON3_ASR17_PROCESSOR_INDEX_SHIFT
Add _LEON3_Get_current_processor().
2014-02-14 10:28:30 +01:00
Sebastian Huber
97cf623d4a sparc: Save/restore only non-volatile context
The _CPU_Context_switch() is a normal function call.  The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5.  Drop these registers from the context.

Ensure that offset defines match the structure offsets.
2014-02-12 09:18:00 +01:00
Sebastian Huber
558cc8ddb7 score: _CPU_Context_switch_to_first_task_smp()
Delete _CPU_Context_switch_to_first_task_smp() and use
_CPU_Context_restore() instead.
2014-02-05 15:46:30 +01:00
Sebastian Huber
2082809919 bsps/sparc: Fix comment 2014-02-05 11:43:32 +01:00
Sebastian Huber
5ff6a9ca62 bsps/sparc: Remove confusing nop 2014-02-04 16:57:59 +01:00
Sebastian Huber
f715433ae9 bsps/sparc: Order load/store by increasing offsets
This may increase the cache hit performance.
2014-02-04 16:57:58 +01:00
Sebastian Huber
a54179d2ba bsps/sparc: Fix comments 2014-02-04 16:57:58 +01:00
Daniel Hellstrom
2d3eb23349 sparc/shared/irq_asm.S: Get pointer to self per-CPU control
_CPU_Context_switch_to_first_task_smp() branches to
done_flushing which requires o3 to be initalized with
"self per-CPU control", this adds initialization of
o3. This problem only affects SMP, see commit
f8ad6c6f7f were usage of o3 was intruduced.
2013-11-30 09:28:28 -06:00
Sebastian Huber
f8ad6c6f7f sparc: Make _CPU_ISR_Dispatch_disable per-CPU
This variable must be available for each processor in the system.
2013-08-09 23:02:45 +02:00
Sebastian Huber
88f6c4fc5a sparc: Move _CPU_Context_switch(), etc.
Move the _CPU_Context_switch(), _CPU_Context_restore() and
_CPU_Context_switch_to_first_task_smp() code since the method to obtain
the processor index is BSP specific.
2013-08-09 23:02:44 +02:00
Sebastian Huber
8b077ca0e4 bsps/sparc: SMP and per-CPU thread dispatch disable
Interrupt support for SMP and per-CPU thread dispatch disable level.
2013-08-09 23:02:44 +02:00
Sebastian Huber
849bb7a332 bsps/sparc: Revert most SMP related changes
As a side-effect the PR2082 is fixed with this and later changes.

The commit restores the _ISR_Handler code to the original version in
"cpukit/score/sparc/cpu_asm.S" in commit
6d42b4c60a.  A list of reverted changes
follows.

commit c236082873
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date:   Tue Jul 30 15:54:53 2013 +0200

    smp: Provide cache optimized Per_CPU_Control

    Delete _Per_CPU_Information_p.

This commit was completely reverted.

commit e517714b7c
Author: Jennifer Averett <jennifer.averett@oarcorp.com>
Date:   Tue Feb 26 12:31:23 2013 -0600

    sparc: Remove dead code that was leftover from SMP development.

This commit was completely reverted.

commit 47a61aa16f
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date:   Fri Oct 7 14:35:03 2011 +0000

    2011-10-07	Daniel Hellstrom <daniel@gaisler.com>

    	PR 1933/cpukit
    	* shared/irq_asm.S: From code inspection I have found the following
    	issues (most SMP), and some improvements in irq_asm.S. I would need a
    	long test with interrupts to verify the interrupt handler better,
    	however I can not see that these patches hurt. Please see comment per
    	hunk below, One should go through the file to indent delay-slots
    	correctly, I have fixed some in the patch areas. An extra space is
    	added in front of delay slots to indicate a delay slot.

This commit was completely reverted.

commit 0bd3f7e5d1
Author: Jennifer Averett <Jennifer.Averett@OARcorp.com>
Date:   Thu Jul 28 17:33:07 2011 +0000

    2011-07-28	Jennifer Averett <Jennifer.Averett@OARcorp.com>

    	PR 1801
    	* shared/irq_asm.S: Modifications to synch the sparc with the smp
    	working tree.

This commit was completely reverted.

commit 5d69cd33e9
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date:   Wed Mar 16 20:05:30 2011 +0000

    2011-03-16	Jennifer Averett <jennifer.averett@OARcorp.com>

    	PR 1729/cpukit
    	* shared/irq_asm.S: New file.

The parts modifying the original code of _ISR_Handler were reverted.
Only the content move remains.
2013-08-09 23:02:44 +02:00
Sebastian Huber
c236082873 smp: Provide cache optimized Per_CPU_Control
Delete _Per_CPU_Information_p.
2013-07-31 15:09:04 +02:00
Jennifer Averett
e517714b7c sparc: Remove dead code that was leftover from SMP development. 2013-02-26 12:31:23 -06:00
Joel Sherrill
9b4422a251 Remove All CVS Id Strings Possible Using a Script
Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines
  next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
  contain CVS Ids
+ If the processing left a blank line at the top of
  a file, it was removed.
2012-05-11 08:44:13 -05:00
Joel Sherrill
47a61aa16f 2011-10-07 Daniel Hellstrom <daniel@gaisler.com>
PR 1933/cpukit
	* shared/irq_asm.S: From code inspection I have found the following
	issues (most SMP), and some improvements in irq_asm.S. I would need a
	long test with interrupts to verify the interrupt handler better,
	however I can not see that these patches hurt. Please see comment per
	hunk below, One should go through the file to indent delay-slots
	correctly, I have fixed some in the patch areas. An extra space is
	added in front of delay slots to indicate a delay slot.
2011-10-07 14:35:03 +00:00
Jennifer Averett
0bd3f7e5d1 2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com>
PR 1801
	* shared/irq_asm.S: Modifications to synch the sparc with the smp
	working tree.
2011-07-28 17:33:07 +00:00
Joel Sherrill
5d69cd33e9 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>
PR 1729/cpukit
	* shared/irq_asm.S: New file.
2011-03-16 20:05:30 +00:00