It is importeant to consistently apply the same handling for flushing within
level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
The baud rate of the altera cyclone-V U-Boot can not be changed at the
u-Boot console prompt. Thus we use the same baud rate as the U-Boot for
the BSP.
Add and use _CPU_SMP_Start_processor(). Add and use
_CPU_SMP_Finalize_initialization(). This makes most
_CPU_SMP_Initialize() functions a bit simpler since we can calculate the
minimum value of the count of processors requested by the application
configuration and the count of physically or virtually available
processors in the high-level code.
The CPU port has now the ability to signal a processor start failure.
With the support for clustered/partitioned scheduling the presence of
particular processors can be configured to be optional or mandatory.
There will be a fatal error only in case mandatory processors are not
present.
The CPU port may use a timeout to monitor the start of a processor.
Rename rtems_smp_get_current_processor() in
rtems_get_current_processor(). Make rtems_get_current_processor() a
function in uni-processor configurations to enable ABI compatibility
with SMP configurations.
arm-l2c-310/cache_.h contains the handling for the L2C-310
level 2 cache controller from arm. It references the arm
level 1 cache handling in the new file arm-cache-l1.h.
Since the per-CPU SMP lock must be acquired and released to send the
message a single interrupt broadcast operations offers no benefits. If
synchronization is required, then a SMP barrier must be used anyway.
Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC
into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to
figure out the code position given a fatal source and code.
Add a CPU counter interface to allow access to a free-running counter.
It is useful to measure short time intervals. This can be used for
example to enable profiling of critical low-level functions.
Add two busy wait functions rtems_counter_delay_ticks() and
rtems_counter_delay_nanoseconds() implemented via the CPU counter.
Use the Global Timer for the Cortex-A9 MPCore clock driver instead of
the Private Timer. This enables a consistent nanoseconds since last
context switch value across all processors.
