With this, it is possible to use GPIOs as CS pins in the LPSPI. To avoid
additional complexity, the GPIOs will have the same limitations as the
native (hardware) CS pins.
The GPIO CS feature adds a number of extra code when starting SPI
transfers on this controller. Therefore it is possible to disable the
additional code by just setting the IMXRT_LPSPI_MAX_CS option to 0. In
that case only native CS pins are supported.
At the moment, this feature is only enabled on i.MXRT1166 by default
because it is not tested on i.MXRT1050. But it should work there too.
Device trees allow mixing different kinds of GPIOs in one property. For
that it is usefull to only provide a pointer to an arbitrary location in
the property and initialize a GPIO from that.
For uniprocessor configurations, the selection of
RTEMS_MULTIPROCESSOR_RESOURCE_SHARING results in a priority ceiling
mutex.
Build the MrsP validation tests only if RTEMS_SMP is enabled.
Update #3716.
This imports the TTC hardware definitions for the triple timer counters
on various Xilinx platforms. This was imported as specified in the
VERSION file in this commit.
The code coverage build is usually done without compiler optimizations.
This results in long performance test runtimes and useless performance
results.
Enable an individual testsuite only through the corresponding enable.
Use BUILD_TESTS to change the default value of the individual testsuite
enable options. This allows the user to enable all testsuites with
specific exceptions.
For example, this builds all testsuites except the benchmarks:
[arch/bsp]
BUILD_TESTS = True
BUILD_BENCHMARKS = False
Thread_Life_state is used as a bitfield, but is declared as an enum.
This converts the enum typedef to a uint32_t typedef and associated bit
definitions.
The xnandpsu driver conditionally tries to wrap page index to NAND chip
size causing an off-by-one error where the first page of the second chip
is not wrapped correctly. This removes the conditional so that page
index is always wrapped.
On configurations where multiple NAND chips are in use, the erasure
loop in XNandPsu_Erase() can reset the loop counter variable once it
gets to blocks in the second chip causing an infinite loop overwriting
parts of the first chip. This change ensures that the loop counter is
not accidentally reset.
Prefer use of XNandPsu_Erase instead of XNandPsu_EraseBlock since the
XNandPsu driver does not expose the primitives necessary to ensure
device readiness after the operation is complete.
This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
Merge the timecounter and CPU counter support for the leon3 BSP family.
Remove now unused functions from the CPU counter support of the erc32
and leon3 BSPs.
Update #4954.
Share the timecounter instance between the clock and the CPU counter.
This greatly simplifies the clock driver since we have to do the device
selection only in one place, the CPU counter support.
Update #4954.
Using the auto reload counter which generates the clock ticks for the
timecounter or CPU counter is quite difficult and only works in
uniprocessor configurations.
Update #4954.
This improves the standard compatibility of API headers. It fixes
errors like this if RTEMS_MULTIPROCESSING is enabled:
cpukit/include/rtems/score/processormask.h: In function 'uint32_t _Processor_mask_Find_last_set(const Processor_mask*)':
cpukit/include/rtems/score/processormask.h:339:21: error: 'flsl' was not declared in this scope
339 | return (uint32_t) __BIT_FLS( CPU_MAXIMUM_PROCESSORS, a );
| ^~~~~~~~~
Force use of addresses that would be translated by TTBR1 to cause a
translation fault. RTEMS on AArch64 does not use TTBR1 and so attempted
translation of that address range could cause unexpected behavior in the
form of other exception types since TTBR1 is never set.
This provides a non-noop implementation of spinlocks for JFFS2 in terms
of RTEMS mutexes. POSIX spinlocks are not appropriate for the types of
actions that occur during a held JFFS2 spinlock and can cause bad
dispatch level conditions.
Ensure that a single locking session is carried over OOB writes
including the OOB read that is sometimes required. This removes the
possibility of another write occurring between the read and write that
would make the write incorrect.
