The _VBR is a symbol defined by linker scripts. You cannot change this
value at runtime. The BSP initialization has to ensure that
m68k_set_vbr() is only set to _VBR.
Close#5210.
For the application configuration option
CONFIGURE_RECORD_INTERRUPTS_ENABLED, define
bsp_interrupt_get_dispatch_table_slot() in the application configuration
to avoid issues with the object link order within the RTEMS libraries.
Enable this option in an associated test.
Close#5244.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
When AArch64 exception support was first written, nested exceptions were
configured using the wrong stack. This happened to work since any
changes were unwound from the stack before dispatch occurred. This
implements correct behavior for all SP0 interrupt vectors.
Closes#5140
The sp0 IRQ and lel32 SError exception targets were left in a bad state
following the exception rework to avoid use of mutable code pages. The
lel32 SError exception is entirely unused by RTEMS. This points the two
erroneous exception vectors at the correct targets.
The block of embedded assembly language which creates a section
to add auto-loading of the Python pretty printing scripts was
getting this warning on all ARM BSPs.
/tmp/ccMGaqij.s: Assembler messages:
/tmp/ccMGaqij.s:19: missing merge / string entity size, 1 assumed
This was because the @ symbol is a comment on ARM. Changing to
a % as suggested on the binutils mailing list resolved the problem.
This also moves the header from <utf8proc/utf8proc.h> to <utf8proc.h> This
follows what the upstream project uses and keeps us from having to modify
upstream source to put it in a subdirectory.
Incorrect format specifier: printf() adjusted to be clean on both 32
and 64 bit PowerPCs.
Defined but not used: Adjusted _ARCH_PPC64 ifdef's to properly
eliminate code not used on 64 bit PowerPCs.
The DBG_PRINTF() macro was using the GNU extension variadic macro
style. Switched to standard C style variadic macro, printk() so
safer for debug than printf(), and included needed files.
This adds support for the "vGetTLSAddr" GDB query which retrieves the
address of a TLS variable by offset from the beginning of the TLS memory
space for the given thread. This offset does not include the size of the
thread control block which is at the beginning of every TLS area as used
by RTEMS. Notably, the returned address is big-endian rather than the
little-endian typical with other responses.
This functionality does not include retrieval of addresses for TLS
variables hosted in loadable modules, only TLS variables in the host
binary.
According to the Posix specification:
Upon successful completion pthread_sigmask() shall return 0;
otherwise, it shall return the corresponding error number.
On some BSP builds, the variable q was reported as used before
it was initialized. This is a false positive. The variable is now
initialized to NULL to prevent this.
This was warning about the FP context not being restored
when a thread is restarted. The current and long standing
execution path is through _Thread_Handler() which does restore
the FP context.
This function was static inline which means that it must compile
cleanly for all versions of C and C++. Newer C standards make it
an error to cast between incompatible function types. Moving this
function to cpu.c from cpu.h allows the C standard version required
to be narrowed from "whatever the user wants" to the one version
that is used to compile RTEMS.
GCC gave the warning that "ISO C restricts enumerator values to
range of 'int' before C23 [-Wpedantic]."
Changed place holder value from 0xffffffff to 0x7fffffff.
The Moxie does not implement the interrupt disable/enable functions
and this led to an unused variable warning. Just added proper
annotation to let GCC know it is intentionally unused.
This refactors the AArch64 exception handling to remove the mutable code
sections that are generally flagged as a bad idea by code analysis
tools. This also removes any casting between data pointers and function
pointers to avoid the need to use pragmas to disable warnings about such
casting.
Some fixes where necessary to not handle ARMv8M identical to (for
example) ARMv8A. ARMv8M is more similar to ARMv7M.
Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
If the Double Trap Extension is implemented, the
MDT bit of the mstatus (or mstatush in RV32)
register will be set when a trap is to be taken.
The MIE (Machine Interrupt Enable) bit can only
be set to 1 if the MDT bit is zero.
Thus, we need to clear MDT first if we want to
enable interrupts when dispatching a thread.
MDT is also cleared in register a1 before
restoring the interrupt frame as writing 1 to MDT
will cause MIE to be set to 0. In RV64 this
happens regardless of the value written to MIE in
the same write.
In RV32, MDT is in the mstatush so we do not need
to clear during restore as this register is not
restored.
With this change all 60 SMP tests pass (compared
to 20/60 before the fix). The tests have been run
on hardware using two RV64 CPUs that implement
the double trap extension.
Update #5274
