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bsps/shared/xqspipsu: Read correct status bits

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When resetting the QSPI FIFOs, the driver was reading write-only bits of
a register for status information when it was actually in a different
register. This corrects the driver so that it reads the correct status
bits.
This commit is contained in:
Kinsey Moore
2024-03-05 14:07:35 -06:00
committed by Joel Sherrill
parent 33379dcfc4
commit fd790b3431
1 changed files with 15 additions and 0 deletions
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15
bsps/shared/dev/spi/xqspipsu.c
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@@ -278,6 +278,12 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
u32 IntrStatus, ConfigReg, FifoStatus;
u32 DelayCount = 0U;
#ifdef __rtems__
u32 FifoStatusMask = XQSPIPSU_ISR_RXEMPTY_MASK;
FifoStatusMask |= XQSPIPSU_ISR_TXEMPTY_MASK;
FifoStatusMask |= XQSPIPSU_ISR_GENFIFOEMPTY_MASK;
#endif
Xil_AssertVoid(InstancePtr != NULL);
#ifdef DEBUG
xil_printf("\nXQspiPsu_Abort\r\n");
@@ -329,8 +335,13 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
*/
FifoStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
#ifdef __rtems__
XQSPIPSU_ISR_OFFSET) & FifoStatusMask;
while(FifoStatus != FifoStatusMask) {
#else
XQSPIPSU_FIFO_CTRL_OFFSET);
while(FifoStatus != 0U) {
#endif
if (DelayCount == MAX_DELAY_CNT) {
#ifdef DEBUG
xil_printf("Timeout error, FIFO reset failed.\r\n");
@@ -340,7 +351,11 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
usleep(1);
DelayCount++;
FifoStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
#ifdef __rtems__
XQSPIPSU_ISR_OFFSET) & FifoStatusMask;
#else
XQSPIPSU_FIFO_CTRL_OFFSET);
#endif
}
}