forked from Imagelibrary/rtems
bsps: Import Xilinx GQSPI driver
This adds Xilinx's driver for the Xilinx GQSPI controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/spi/VERSION.
This commit is contained in:
Alex White
committed by
Joel Sherrill
Joel Sherrill
parent
1da87d6293
commit
fd2f9d40b5
29
bsps/shared/dev/spi/VERSION
Normal file
29
bsps/shared/dev/spi/VERSION
Normal file
@@ -0,0 +1,29 @@
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The information in this file describes the source of the following files in
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bsps/shared/dev/spi/ and bsps/include/dev/spi/:
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- xqspipsu_control.c
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- xqspipsu_control.h
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- xqspipsu_flash_config.h
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- xqspipsu_hw.c
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- xqspipsu_hw.h
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- xqspipsu_options.c
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- xqspipsu.c
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- xqspipsu.h
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Import from:
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https://github.com/Xilinx/embeddedsw.git
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commit 8a89579489c88ea5acd23d7d439ac928659c26cf
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Author: msreeram <manikanta.sreeram@xilinx.com>
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AuthorDate: Wed Apr 6 23:24:38 2022 -0600
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Commit: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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CommitDate: Fri Apr 8 16:47:15 2022 +0530
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update license file for EmbeddedSW 2022.1 release
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Update license file for EmbeddedSW 2022.1 release
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Signed-off-by: Manikanta Sreeram <msreeram@xilinx.com>
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Acked-by : Meena Paleti <meena.paleti@xilinx.com>
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1048
bsps/shared/dev/spi/xqspipsu.c
Normal file
1048
bsps/shared/dev/spi/xqspipsu.c
Normal file
File diff suppressed because it is too large
Load Diff
282
bsps/shared/dev/spi/xqspipsu_control.c
Normal file
282
bsps/shared/dev/spi/xqspipsu_control.c
Normal file
@@ -0,0 +1,282 @@
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/******************************************************************************
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* Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xqspipsu_control.c
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* @addtogroup Overview
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* @{
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*
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* This file contains intermediate control functions used by functions
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* in xqspipsu.c and xqspipsu_options.c files.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- -------- -----------------------------------------------
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* 1.11 akm 03/09/20 First release
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* 1.13 akm 01/04/21 Fix MISRA-C violations.
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* 1.15 akm 10/21/21 Fix MISRA-C violations.
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* 1.15 akm 03/03/22 Enable tapdelay settings for applications on
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* Microblaze platform.
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xqspipsu_control.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/*****************************************************************************/
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/**
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*
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* This function writes the GENFIFO entries to transmit the messages requested.
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*
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* @param InstancePtr is a pointer to the XQspiPsu instance.
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* @param Msg is a pointer to the structure containing transfer data.
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*
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* @return
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* - XST_SUCCESS if successful.
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* - XST_FAILURE if transfer fails.
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* - XST_DEVICE_BUSY if a transfer is already in progress.
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*
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* @note None.
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*
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******************************************************************************/
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void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg)
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{
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u32 GenFifoEntry;
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(Msg != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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#ifdef DEBUG
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xil_printf("\nXQspiPsu_GenFifoEntryData\r\n");
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#endif
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GenFifoEntry = 0x0U;
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/* Bus width */
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GenFifoEntry &= ~(u32)XQSPIPSU_GENFIFO_MODE_MASK;
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GenFifoEntry |= XQspiPsu_SelectSpiMode((u8)Msg->BusWidth);
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GenFifoEntry |= InstancePtr->GenFifoCS;
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GenFifoEntry &= ~(u32)XQSPIPSU_GENFIFO_BUS_MASK;
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GenFifoEntry |= InstancePtr->GenFifoBus;
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/* Data */
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if (((Msg->Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != (u32)FALSE) {
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GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
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} else {
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GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
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}
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/* If Byte Count is less than 8 bytes do the transfer in IO mode */
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if ((Msg->ByteCount < 8U) &&
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(InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)) {
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InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
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(XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) &
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~XQSPIPSU_CFG_MODE_EN_MASK));
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InstancePtr->IsUnaligned = 1;
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}
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XQspiPsu_TXRXSetup(InstancePtr, Msg, &GenFifoEntry);
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XQspiPsu_GenFifoEntryDataLen(InstancePtr, Msg, &GenFifoEntry);
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/* One dummy GenFifo entry in case of IO mode */
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if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) &&
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((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != (u32)FALSE)) {
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GenFifoEntry = 0x0U;
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#ifdef DEBUG
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xil_printf("\nDummy FifoEntry=%08x\r\n", GenFifoEntry);
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#endif
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
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}
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}
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/*****************************************************************************/
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/**
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*
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* This function enables the polling functionality of controller
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*
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* @param InstancePtr is a pointer to the XQspiPsu instance.
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*
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*
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* @param FlashMsg is a pointer to the structure containing transfer data
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*
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* @return None
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*
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* @note None.
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*
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******************************************************************************/
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void XQspiPsu_PollDataConfig(XQspiPsu *InstancePtr, XQspiPsu_Msg *FlashMsg)
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{
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u32 GenFifoEntry;
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u32 Value;
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(FlashMsg != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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#ifdef DEBUG
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xil_printf("\nXQspiPsu_PollDataConfig\r\n");
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#endif
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Value = XQspiPsu_CreatePollDataConfig(InstancePtr, FlashMsg);
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_POLL_CFG_OFFSET, Value);
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_P_TO_OFFSET, FlashMsg->PollTimeout);
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XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
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GenFifoEntry = (u32)0;
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GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_TX;
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GenFifoEntry |= InstancePtr->GenFifoBus;
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GenFifoEntry |= InstancePtr->GenFifoCS;
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GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
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GenFifoEntry |= (u32)FlashMsg->PollStatusCmd;
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
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GenFifoEntry = (u32)0;
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GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_POLL;
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GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_RX;
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GenFifoEntry |= InstancePtr->GenFifoBus;
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GenFifoEntry |= InstancePtr->GenFifoCS;
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GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
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if (((FlashMsg->Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != (u32)FALSE) {
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GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
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} else {
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GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
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}
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
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GenFifoEntry);
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/* One Dummy entry required for IO mode */
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GenFifoEntry = 0x0U;
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
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GenFifoEntry);
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InstancePtr->Msg = FlashMsg;
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InstancePtr->NumMsg = (s32)1;
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InstancePtr->MsgCnt = 0;
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Value = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_CFG_OFFSET);
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Value &= ~XQSPIPSU_CFG_MODE_EN_MASK;
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Value |= (XQSPIPSU_CFG_START_GEN_FIFO_MASK |
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XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK |
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XQSPIPSU_CFG_EN_POLL_TO_MASK);
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
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Value);
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/* Enable interrupts */
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Value = ((u32)XQSPIPSU_IER_RXNEMPTY_MASK |
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(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_IER_OFFSET,
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Value);
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}
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#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
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/*****************************************************************************/
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/**
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*
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* Configures the clock according to the prescaler passed.
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*
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*
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* @param InstancePtr is a pointer to the XQspiPsu instance.
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* @param Prescaler - clock prescaler.
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*
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* @return
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* - XST_SUCCESS if successful.
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* - XST_DEVICE_BUSY if the device is currently transferring data.
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* The transfer must complete or be aborted before setting Tapdelay.
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*
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* @note None.
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*
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******************************************************************************/
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s32 XQspipsu_Calculate_Tapdelay(const XQspiPsu *InstancePtr, u8 Prescaler)
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{
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u32 FreqDiv, Divider;
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u32 Tapdelay = 0;
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u32 LBkModeReg = 0;
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u32 delayReg = 0;
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s32 Status;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(Prescaler <= XQSPIPSU_CR_PRESC_MAXIMUM);
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/*
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* Do not allow the slave select to change while a transfer is in
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* progress. Not thread-safe.
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*/
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if (InstancePtr->IsBusy == (u32)TRUE) {
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Status = (s32)XST_DEVICE_BUSY;
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goto END;
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} else {
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Divider = (u32)1U << (Prescaler+1U);
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FreqDiv = (InstancePtr->Config.InputClockHz)/Divider;
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#if defined (versal)
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if (FreqDiv <= XQSPIPSU_FREQ_37_5MHZ) {
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#else
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if (FreqDiv <= XQSPIPSU_FREQ_40MHZ) {
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#endif
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Tapdelay |= (TAPDLY_BYPASS_VALVE_40MHZ <<
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IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
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} else if (FreqDiv <= XQSPIPSU_FREQ_100MHZ) {
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Tapdelay |= (TAPDLY_BYPASS_VALVE_100MHZ <<
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IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
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LBkModeReg |= (USE_DLY_LPBK << XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT);
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#if defined (versal)
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delayReg |= (u32)USE_DATA_DLY_ADJ <<
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XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT;
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#else
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delayReg |= ((u32)USE_DATA_DLY_ADJ <<
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XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT) |
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((u32)DATA_DLY_ADJ_DLY << XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT);
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#endif
|
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} else if (FreqDiv <= XQSPIPSU_FREQ_150MHZ) {
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#if defined (versal)
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LBkModeReg |= (USE_DLY_LPBK << XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT) |
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(LPBK_DLY_ADJ_DLY1 << XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT);
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#else
|
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LBkModeReg |= USE_DLY_LPBK << XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT;
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#endif
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} else {
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Status = (s32)XST_FAILURE;
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goto END;
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}
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|
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Status = XQspipsu_Set_TapDelay(InstancePtr, Tapdelay, LBkModeReg, delayReg);
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||||
}
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|
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END:
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return Status;
|
||||
}
|
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#endif
|
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/** @} */
|
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768
bsps/shared/dev/spi/xqspipsu_hw.c
Normal file
768
bsps/shared/dev/spi/xqspipsu_hw.c
Normal file
@@ -0,0 +1,768 @@
|
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/******************************************************************************
|
||||
* Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
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|
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|
||||
/*****************************************************************************/
|
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/**
|
||||
*
|
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* @file xqspipsu_hw.c
|
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* @addtogroup Overview
|
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* @{
|
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*
|
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* This file contains functions to reads RXFifo, writes TXFifo and setup
|
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* RX DMA operation, used by xqspipsu_control.c and xqspipsu_lowlevel.c files.
|
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*
|
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* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- -----------------------------------------------
|
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* 1.11 akm 03/09/20 First release
|
||||
* mn 03/30/20 Add xil_smc.h include for Xil_Smc calls
|
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* 1.13 akm 01/04/21 Fix MISRA-C violations.
|
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* 1.15 akm 10/21/21 Fix MISRA-C violations.
|
||||
* 1.15 akm 11/16/21 Typecast function parameter with appropriate
|
||||
* data type.
|
||||
* 1.15 akm 11/30/21 Fix compilation warnings reported with -Wundef flag
|
||||
* 1.15 akm 03/03/22 Enable tapdelay settings for applications on
|
||||
* Microblaze platform.
|
||||
*
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xqspipsu.h"
|
||||
#include "xqspipsu_control.h"
|
||||
#if defined (__aarch64__)
|
||||
#include "xil_smc.h"
|
||||
#endif
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Fills the TX FIFO as long as there is room in the FIFO or the bytes required
|
||||
* to be transmitted.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
* @param Size is the number of bytes to be transmitted.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 Size)
|
||||
{
|
||||
u32 Count = 0;
|
||||
u32 Data = 0U;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(Size != 0U);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_FillTxFifo\r\n");
|
||||
#endif
|
||||
while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
|
||||
if (InstancePtr->TxBytes >= 4) {
|
||||
(void)Xil_MemCpy((u8 *)&Data, Msg->TxBfrPtr, 4);
|
||||
Msg->TxBfrPtr += 4;
|
||||
InstancePtr->TxBytes -= 4;
|
||||
Count += 4U;
|
||||
} else {
|
||||
(void)Xil_MemCpy((u8 *)&Data, Msg->TxBfrPtr,
|
||||
(u32)InstancePtr->TxBytes);
|
||||
Msg->TxBfrPtr += InstancePtr->TxBytes;
|
||||
Count += (u32)InstancePtr->TxBytes;
|
||||
InstancePtr->TxBytes = 0;
|
||||
}
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_TXD_OFFSET, Data);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nData is %08x\r\n", Data);
|
||||
#endif
|
||||
|
||||
}
|
||||
if (InstancePtr->TxBytes < 0) {
|
||||
InstancePtr->TxBytes = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function checks the TX buffer in the message and setup the
|
||||
* TX FIFO as required.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_TXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg)
|
||||
{
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_TXSetup\r\n");
|
||||
#endif
|
||||
InstancePtr->TxBytes = (s32)Msg->ByteCount;
|
||||
InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
|
||||
|
||||
XQspiPsu_FillTxFifo(InstancePtr, Msg, (u32)XQSPIPSU_TXD_DEPTH);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets up the RX DMA operation.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_SetupRxDma(const XQspiPsu *InstancePtr,
|
||||
XQspiPsu_Msg *Msg)
|
||||
{
|
||||
s32 Remainder;
|
||||
s32 DmaRxBytes;
|
||||
UINTPTR AddrTemp;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_SetupRxDma\r\n");
|
||||
#endif
|
||||
|
||||
AddrTemp = ((UINTPTR)(Msg->RxBfrPtr) & XQSPIPSU_QSPIDMA_DST_ADDR_MASK);
|
||||
/* Check for RXBfrPtr to be word aligned */
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, (u32)AddrTemp);
|
||||
|
||||
#if defined(__aarch64__) || defined(__arch64__)
|
||||
AddrTemp = ((UINTPTR)(Msg->RxBfrPtr) >> 32U);
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, (u32)AddrTemp &
|
||||
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
|
||||
#else
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, 0U);
|
||||
#endif
|
||||
|
||||
Remainder = InstancePtr->RxBytes % 4;
|
||||
DmaRxBytes = InstancePtr->RxBytes;
|
||||
if (Remainder != 0) {
|
||||
/* This is done to make Dma bytes aligned */
|
||||
DmaRxBytes = InstancePtr->RxBytes - Remainder;
|
||||
Msg->ByteCount = (u32)DmaRxBytes;
|
||||
}
|
||||
if (InstancePtr->Config.IsCacheCoherent == 0U) {
|
||||
Xil_DCacheInvalidateRange((INTPTR)Msg->RxBfrPtr, (INTPTR)Msg->ByteCount);
|
||||
}
|
||||
/* Write no. of words to DMA DST SIZE */
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets up the RX DMA operation on a 32bit Machine
|
||||
* For 64bit Dma transfers.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_Setup64BRxDma(const XQspiPsu *InstancePtr,
|
||||
XQspiPsu_Msg *Msg)
|
||||
{
|
||||
s32 Remainder;
|
||||
s32 DmaRxBytes;
|
||||
u64 AddrTemp;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_Setup64BRxDma\r\n");
|
||||
#endif
|
||||
AddrTemp = Msg->RxAddr64bit & XQSPIPSU_QSPIDMA_DST_ADDR_MASK;
|
||||
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, (u32)AddrTemp);
|
||||
|
||||
AddrTemp = (Msg->RxAddr64bit >> 32);
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, (u32)AddrTemp &
|
||||
XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
|
||||
|
||||
Remainder = InstancePtr->RxBytes % 4;
|
||||
DmaRxBytes = InstancePtr->RxBytes;
|
||||
if (Remainder != 0) {
|
||||
/* This is done to make Dma bytes aligned */
|
||||
DmaRxBytes = InstancePtr->RxBytes - Remainder;
|
||||
Msg->ByteCount = (u32)DmaRxBytes;
|
||||
}
|
||||
|
||||
/* Write no. of words to DMA DST SIZE */
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function reads remaining bytes, after the completion of a DMA transfer,
|
||||
* using IO mode
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if successful.
|
||||
* - XST_FAILURE if transfer fails.
|
||||
* - XST_DEVICE_BUSY if a transfer is already in progress.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 XQspiPsu_SetIOMode(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg)
|
||||
{
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(Msg != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_DMARXComplete\r\n");
|
||||
#endif
|
||||
|
||||
/* Read remaining bytes using IO mode */
|
||||
if ((InstancePtr->RxBytes % 4) != 0) {
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
|
||||
(XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET) &
|
||||
~XQSPIPSU_CFG_MODE_EN_MASK));
|
||||
InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
|
||||
Msg->ByteCount = (u32)InstancePtr->RxBytes % 4U;
|
||||
Msg->RxBfrPtr += (InstancePtr->RxBytes - (InstancePtr->RxBytes % 4));
|
||||
InstancePtr->IsUnaligned = 1;
|
||||
return (u32) TRUE;
|
||||
}
|
||||
return (u32) FALSE;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function checks the RX buffers in the message and setup the
|
||||
* RX DMA as required.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_RXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg)
|
||||
{
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_RXSetup\r\n");
|
||||
#endif
|
||||
InstancePtr->RxBytes = (s32)Msg->ByteCount;
|
||||
|
||||
if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
|
||||
if ((Msg->RxAddr64bit >= XQSPIPSU_RXADDR_OVER_32BIT) ||
|
||||
(Msg->Xfer64bit != (u8)0U)) {
|
||||
XQspiPsu_Setup64BRxDma(InstancePtr, Msg);
|
||||
} else {
|
||||
XQspiPsu_SetupRxDma(InstancePtr, Msg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function checks the TX/RX buffers in the message and setups up the
|
||||
* GENFIFO entries, TX FIFO or RX DMA as required.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
* @param GenFifoEntry is pointer to the variable in which GENFIFO mask
|
||||
* is returned to calling function
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
|
||||
u32 *GenFifoEntry)
|
||||
{
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(GenFifoEntry != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_TXRXSetup\r\n");
|
||||
#endif
|
||||
/* Transmit */
|
||||
if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != (u32)FALSE) &&
|
||||
((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == (u32)FALSE)) {
|
||||
|
||||
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
|
||||
*GenFifoEntry |= XQSPIPSU_GENFIFO_TX;
|
||||
/* Discard RX data */
|
||||
*GenFifoEntry &= ~XQSPIPSU_GENFIFO_RX;
|
||||
|
||||
/* Setup data to be TXed */
|
||||
XQspiPsu_TXSetup(InstancePtr, Msg);
|
||||
|
||||
InstancePtr->RecvBufferPtr = NULL;
|
||||
InstancePtr->RxBytes = 0;
|
||||
}
|
||||
/*Receive*/
|
||||
if (((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != (u32)FALSE) &&
|
||||
((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == (u32)FALSE)) {
|
||||
|
||||
/* TX auto fill */
|
||||
*GenFifoEntry &= ~XQSPIPSU_GENFIFO_TX;
|
||||
/* Setup RX */
|
||||
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
|
||||
*GenFifoEntry |= XQSPIPSU_GENFIFO_RX;
|
||||
|
||||
/* Setup DMA for data to be RXed */
|
||||
XQspiPsu_RXSetup(InstancePtr, Msg);
|
||||
|
||||
InstancePtr->SendBufferPtr = NULL;
|
||||
InstancePtr->TxBytes = 0;
|
||||
}
|
||||
/* If only dummy is requested as a separate entry */
|
||||
if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == (u32)FALSE) &&
|
||||
((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == (u32)FALSE)) {
|
||||
|
||||
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
|
||||
*GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
|
||||
InstancePtr->TxBytes = 0;
|
||||
InstancePtr->RxBytes = 0;
|
||||
InstancePtr->SendBufferPtr = NULL;
|
||||
InstancePtr->RecvBufferPtr = NULL;
|
||||
}
|
||||
/* Dummy and cmd sent by upper layer to received data */
|
||||
if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != (u32)FALSE) &&
|
||||
((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != (u32)FALSE)) {
|
||||
*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
|
||||
*GenFifoEntry |= (XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
|
||||
|
||||
/* Setup data to be TXed */
|
||||
XQspiPsu_TXSetup(InstancePtr, Msg);
|
||||
/* Setup DMA for data to be RXed */
|
||||
XQspiPsu_RXSetup(InstancePtr, Msg);
|
||||
}
|
||||
}
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function writes the Data length to GENFIFO entries that need to be
|
||||
* transmitted or received.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
* @param GenFifoEntry is index of the current message to be handled.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if successful.
|
||||
* - XST_FAILURE if transfer fails.
|
||||
* - XST_DEVICE_BUSY if a transfer is already in progress.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_GenFifoEntryDataLen(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
|
||||
u32 *GenFifoEntry)
|
||||
{
|
||||
u32 TempCount;
|
||||
u32 ImmData;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(GenFifoEntry != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_GenFifoEntryDataLen\r\n");
|
||||
#endif
|
||||
|
||||
if (Msg->ByteCount <= XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
|
||||
*GenFifoEntry &= ~(u32)XQSPIPSU_GENFIFO_IMM_DATA_MASK;
|
||||
*GenFifoEntry |= Msg->ByteCount;
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nFifoEntry=%08x\r\n", *GenFifoEntry);
|
||||
#endif
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
|
||||
*GenFifoEntry);
|
||||
} else {
|
||||
TempCount = Msg->ByteCount;
|
||||
u32 Exponent = 8; /* 2^8 = 256 */
|
||||
ImmData = TempCount & 0xFFU;
|
||||
/* Exponent entries */
|
||||
*GenFifoEntry |= XQSPIPSU_GENFIFO_EXP;
|
||||
while (TempCount != 0U) {
|
||||
if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != (u32)FALSE) {
|
||||
*GenFifoEntry &= ~(u32)XQSPIPSU_GENFIFO_IMM_DATA_MASK;
|
||||
*GenFifoEntry |= Exponent;
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nFifoEntry=%08x\r\n",
|
||||
*GenFifoEntry);
|
||||
#endif
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
|
||||
*GenFifoEntry);
|
||||
}
|
||||
TempCount = TempCount >> 1;
|
||||
Exponent++;
|
||||
}
|
||||
/* Immediate entry */
|
||||
*GenFifoEntry &= ~(u32)XQSPIPSU_GENFIFO_EXP;
|
||||
if ((ImmData & 0xFFU) != (u32)FALSE) {
|
||||
*GenFifoEntry &= ~(u32)XQSPIPSU_GENFIFO_IMM_DATA_MASK;
|
||||
*GenFifoEntry |= ImmData & 0xFFU;
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nFifoEntry=%08x\r\n", *GenFifoEntry);
|
||||
#endif
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
|
||||
*GenFifoEntry);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function creates Poll config register data to write
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
*
|
||||
* @param FlashMsg is a pointer to the structure containing transfer data.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 XQspiPsu_CreatePollDataConfig(const XQspiPsu *InstancePtr,
|
||||
const XQspiPsu_Msg *FlashMsg)
|
||||
{
|
||||
u32 ConfigData = 0;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(FlashMsg != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_CreatePollDataConfig\r\n");
|
||||
#endif
|
||||
|
||||
if ((InstancePtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_UPPER) != (u32)FALSE) {
|
||||
ConfigData = (u32)XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
|
||||
XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT;
|
||||
}
|
||||
if ((InstancePtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_LOWER) != (u32)FALSE) {
|
||||
ConfigData |= (u32)XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
|
||||
XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT;
|
||||
}
|
||||
ConfigData |= (u32)(((u32)FlashMsg->PollBusMask <<
|
||||
XQSPIPSU_POLL_CFG_MASK_EN_SHIFT) & XQSPIPSU_POLL_CFG_MASK_EN_MASK);
|
||||
ConfigData |= (u32)(((u32)FlashMsg->PollData <<
|
||||
XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT)
|
||||
& XQSPIPSU_POLL_CFG_DATA_VALUE_MASK);
|
||||
return ConfigData;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Selects SPI mode - x1 or x2 or x4.
|
||||
*
|
||||
* @param SpiMode - spi or dual or quad.
|
||||
* @return Mask to set desired SPI mode in GENFIFO entry.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
|
||||
{
|
||||
u32 Mask;
|
||||
|
||||
Xil_AssertNonvoid(SpiMode > 0U);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_SelectSpiMode\r\n");
|
||||
#endif
|
||||
|
||||
switch (SpiMode) {
|
||||
case XQSPIPSU_SELECT_MODE_DUALSPI:
|
||||
Mask = XQSPIPSU_GENFIFO_MODE_DUALSPI;
|
||||
break;
|
||||
case XQSPIPSU_SELECT_MODE_QUADSPI:
|
||||
Mask = XQSPIPSU_GENFIFO_MODE_QUADSPI;
|
||||
break;
|
||||
case XQSPIPSU_SELECT_MODE_SPI:
|
||||
Mask = XQSPIPSU_GENFIFO_MODE_SPI;
|
||||
break;
|
||||
default:
|
||||
Mask = XQSPIPSU_GENFIFO_MODE_SPI;
|
||||
break;
|
||||
}
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nSPIMode is %08x\r\n", SpiMode);
|
||||
#endif
|
||||
return Mask;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Enable and initialize DMA Mode, set little endain, disable poll timeout,
|
||||
* clear prescalar bits and reset thresholds
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_SetDefaultConfig(XQspiPsu *InstancePtr)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_SetDefaultConfig\r\n");
|
||||
#endif
|
||||
|
||||
/* Default value to config register */
|
||||
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_CFG_OFFSET);
|
||||
|
||||
/* DMA mode */
|
||||
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
|
||||
ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
|
||||
/* Manual start */
|
||||
ConfigReg |= XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK;
|
||||
/* Little endain by default */
|
||||
ConfigReg &= ~XQSPIPSU_CFG_ENDIAN_MASK;
|
||||
/* Disable poll timeout */
|
||||
ConfigReg &= ~XQSPIPSU_CFG_EN_POLL_TO_MASK;
|
||||
/* Set hold bit */
|
||||
ConfigReg |= XQSPIPSU_CFG_WP_HOLD_MASK;
|
||||
/* Clear prescalar by default */
|
||||
ConfigReg &= ~(u32)XQSPIPSU_CFG_BAUD_RATE_DIV_MASK;
|
||||
/* CPOL CPHA 00 */
|
||||
ConfigReg &= ~(u32)XQSPIPSU_CFG_CLK_PHA_MASK;
|
||||
ConfigReg &= ~(u32)XQSPIPSU_CFG_CLK_POL_MASK;
|
||||
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_CFG_OFFSET, ConfigReg);
|
||||
|
||||
/* Set by default to allow for high frequencies */
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_LPBK_DLY_ADJ_OFFSET,
|
||||
XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_LPBK_DLY_ADJ_OFFSET) |
|
||||
XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK);
|
||||
|
||||
/* Reset thresholds */
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_TX_THRESHOLD_OFFSET, XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL);
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_RX_THRESHOLD_OFFSET, XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL);
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_GF_THRESHOLD_OFFSET, XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL);
|
||||
|
||||
/* DMA init */
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET,
|
||||
XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the specified number of bytes from RX FIFO
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
* @param Size is the number of bytes to be read.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, s32 Size)
|
||||
{
|
||||
s32 Count = 0;
|
||||
u32 Data;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(Size > 0);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_ReadRxFifo\r\n");
|
||||
#endif
|
||||
while ((InstancePtr->RxBytes != 0) && (Count < Size)) {
|
||||
Data = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_RXD_OFFSET);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nData is %08x\r\n", Data);
|
||||
#endif
|
||||
if (InstancePtr->RxBytes >= 4) {
|
||||
(void)Xil_MemCpy(Msg->RxBfrPtr, (u8 *)&Data, 4);
|
||||
InstancePtr->RxBytes -= 4;
|
||||
Msg->RxBfrPtr += 4;
|
||||
Count += 4;
|
||||
} else {
|
||||
/* Read unaligned bytes (< 4 bytes) */
|
||||
(void)Xil_MemCpy(Msg->RxBfrPtr, (u8 *)&Data,
|
||||
(u32)InstancePtr->RxBytes);
|
||||
Msg->RxBfrPtr += InstancePtr->RxBytes;
|
||||
Count += InstancePtr->RxBytes;
|
||||
InstancePtr->RxBytes = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function reads data from RXFifo in IO mode.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Msg is a pointer to the structure containing transfer data.
|
||||
* @param StatusReg is the Interrupt status Register value.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_IORead(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
|
||||
u32 StatusReg)
|
||||
{
|
||||
s32 RxThr;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Msg != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_IORXComplete\r\n");
|
||||
#endif
|
||||
|
||||
if ((StatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK) != 0U) {
|
||||
/*
|
||||
* Check if PIO RX is complete and
|
||||
* update RxBytes
|
||||
*/
|
||||
RxThr = (s32)XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_RX_THRESHOLD_OFFSET);
|
||||
RxThr = RxThr*4;
|
||||
XQspiPsu_ReadRxFifo(InstancePtr, Msg, RxThr);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if ((StatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0U) {
|
||||
XQspiPsu_ReadRxFifo(InstancePtr, Msg, InstancePtr->RxBytes);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the Tapdelay values for the QSPIPSU device driver.The device
|
||||
* must be idle rather than busy transferring data before setting Tapdelay.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param TapdelayBypss contains the IOU_TAPDLY_BYPASS register value.
|
||||
* @param LPBKDelay contains the GQSPI_LPBK_DLY_ADJ register value.
|
||||
* @param Datadelay contains the QSPI_DATA_DLY_ADJ register value.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if options are successfully set.
|
||||
* - XST_DEVICE_BUSY if the device is currently transferring data.
|
||||
* The transfer must complete or be aborted before setting TapDelay.
|
||||
*
|
||||
* @note
|
||||
* This function is not thread-safe.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass,
|
||||
u32 LPBKDelay, u32 Datadelay)
|
||||
{
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Do not allow to modify the Control Register while a transfer is in
|
||||
* progress. Not thread-safe.
|
||||
*/
|
||||
if (InstancePtr->IsBusy == (u32)TRUE) {
|
||||
Status = (s32)XST_DEVICE_BUSY;
|
||||
} else {
|
||||
#if defined (__aarch64__) && (EL1_NONSECURE == 1) && !defined (versal)
|
||||
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
|
||||
IOU_TAPDLY_BYPASS_OFFSET) | ((u64)(0x4) << 32),
|
||||
(u64)TapdelayBypass, 0, 0, 0, 0, 0);
|
||||
#elif defined (versal)
|
||||
XQspiPsu_WriteReg(XQSPIPS_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,
|
||||
TapdelayBypass);
|
||||
#else
|
||||
XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,
|
||||
TapdelayBypass);
|
||||
#endif
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_LPBK_DLY_ADJ_OFFSET, LPBKDelay);
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_DATA_DLY_ADJ_OFFSET, Datadelay);
|
||||
|
||||
Status = (s32)XST_SUCCESS;
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
#endif
|
||||
/** @} */
|
||||
532
bsps/shared/dev/spi/xqspipsu_options.c
Normal file
532
bsps/shared/dev/spi/xqspipsu_options.c
Normal file
@@ -0,0 +1,532 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xqspipsu_options.c
|
||||
* @addtogroup Overview
|
||||
* @{
|
||||
*
|
||||
* This file implements functions to configure the QSPIPSU component,
|
||||
* specifically some optional settings, clock and flash related information.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- -----------------------------------------------
|
||||
* 1.0 hk 08/21/14 First release
|
||||
* sk 03/13/15 Added IO mode support.
|
||||
* sk 04/24/15 Modified the code according to MISRAC-2012.
|
||||
* 1.1 sk 04/12/16 Added debug message prints.
|
||||
* 1.2 nsk 07/01/16 Modified XQspiPsu_SetOptions() to support
|
||||
* LQSPI options and updated OptionsTable
|
||||
* rk 07/15/16 Added support for TapDelays at different frequencies.
|
||||
* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448)
|
||||
* 1.7 tjs 03/14/18 Added support in EL1 NS mode. (CR#974882)
|
||||
* 1.8 tjs 05/02/18 Added support for IS25LP064 and IS25WP064.
|
||||
* 1.8 tjs 07/26/18 Resolved cppcheck errors. (CR#1006336)
|
||||
* 1.9 tjs 04/17/18 Updated register addresses as per the latest revision
|
||||
* of versal (CR#999610)
|
||||
* 1.9 aru 01/17/19 Fixes violations according to MISRAC-2012
|
||||
* in safety mode and modified the code such as
|
||||
* Added Xil_MemCpy inplace of memcpy,Declared the pointer param
|
||||
* as Pointer to const, declared XQspi_Set_TapDelay() as static.
|
||||
* 1.9 akm 03/08/19 Set recommended clock and data tap delay values for 40MHZ,
|
||||
* 100MHZ and 150MHZ frequencies(CR#1023187)
|
||||
* 1.10 akm 08/22/19 Set recommended tap delay values for 37.5MHZ, 100MHZ and
|
||||
* 150MHZ frequencies in Versal.
|
||||
* 1.11 akm 11/07/19 Removed LQSPI register access in Versal.
|
||||
* 1.11 akm 11/15/19 Fixed Coverity deadcode warning in
|
||||
* XQspipsu_Calculate_Tapdelay().
|
||||
* 1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and
|
||||
* interrupts in XQspiPsu_CfgInitialize() API.
|
||||
* 1.13 akm 01/04/21 Fix MISRA-C violations.
|
||||
* 1.15 akm 03/03/22 Enable tapdelay settings for applications on Microblaze
|
||||
* platform.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xqspipsu_control.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/**
|
||||
* Create the table of options which are processed to get/set the device
|
||||
* options. These options are table driven to allow easy maintenance and
|
||||
* expansion of the options.
|
||||
*/
|
||||
typedef struct {
|
||||
u32 Option; /**< Get/Set the device option */
|
||||
u32 Mask; /**< Mask */
|
||||
} OptionsMap;
|
||||
|
||||
static OptionsMap OptionsTable[] = {
|
||||
{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
|
||||
{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
|
||||
{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
|
||||
#if !defined (versal)
|
||||
{XQSPIPSU_LQSPI_MODE_OPTION, XQSPIPSU_CFG_WP_HOLD_MASK},
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* Number of options in option table
|
||||
*/
|
||||
#define XQSPIPSU_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the options for the QSPIPSU device driver.The options
|
||||
* control how the device behaves relative to the QSPIPSU bus. The device must be
|
||||
* idle rather than busy transferring data before setting these device options.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Options contains the specified options to be set. This is a bit
|
||||
* mask where a 1 indicates the option should be turned ON and
|
||||
* a 0 indicates no action. One or more bit values may be
|
||||
* contained in the mask. See the bit definitions named
|
||||
* XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if options are successfully set.
|
||||
* - XST_DEVICE_BUSY if the device is currently transferring data.
|
||||
* The transfer must complete or be aborted before setting options.
|
||||
*
|
||||
* @note
|
||||
* This function is not thread-safe.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
u32 Index;
|
||||
#if !defined (versal)
|
||||
u32 QspiPsuOptions;
|
||||
#endif
|
||||
s32 Status;
|
||||
u32 OptionsVal;
|
||||
OptionsVal = Options;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Do not allow to modify the Control Register while a transfer is in
|
||||
* progress. Not thread-safe.
|
||||
*/
|
||||
if (InstancePtr->IsBusy == (u32)TRUE) {
|
||||
Status = (s32)XST_DEVICE_BUSY;
|
||||
} else {
|
||||
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_CFG_OFFSET);
|
||||
#if !defined (versal)
|
||||
QspiPsuOptions = OptionsVal & XQSPIPSU_LQSPI_MODE_OPTION;
|
||||
OptionsVal &= (~XQSPIPSU_LQSPI_MODE_OPTION);
|
||||
#endif
|
||||
/*
|
||||
* Loop through the options table, turning the option on
|
||||
* depending on whether the bit is set in the incoming options flag.
|
||||
*/
|
||||
for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
|
||||
if ((OptionsVal & OptionsTable[Index].Option) ==
|
||||
OptionsTable[Index].Option) {
|
||||
/* Turn it on */
|
||||
ConfigReg |= OptionsTable[Index].Mask;
|
||||
} else {
|
||||
/* Turn it off */
|
||||
ConfigReg &= ~(OptionsTable[Index].Mask);
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Now write the control register. Leave it to the upper layers
|
||||
* to restart the device.
|
||||
*/
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
|
||||
ConfigReg);
|
||||
|
||||
if ((OptionsVal & XQSPIPSU_MANUAL_START_OPTION) != (u32)FALSE) {
|
||||
InstancePtr->IsManualstart = (u8)TRUE;
|
||||
}
|
||||
#if !defined (versal)
|
||||
if ((QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) != (u32)FALSE) {
|
||||
if ((Options & XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB) != (u32)FALSE) {
|
||||
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE);
|
||||
} else {
|
||||
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_4_BYTE_STATE);
|
||||
}
|
||||
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_CFG_OFFSET,XQSPIPS_LQSPI_CFG_RST_STATE);
|
||||
/* Enable the QSPI controller */
|
||||
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_EN_OFFSET,XQSPIPSU_EN_MASK);
|
||||
} else {
|
||||
/*
|
||||
* Check for the LQSPI configuration options.
|
||||
*/
|
||||
ConfigReg = XQspiPsu_ReadReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET);
|
||||
ConfigReg &= ~(XQSPIPSU_LQSPI_CR_LINEAR_MASK);
|
||||
XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET, ConfigReg);
|
||||
}
|
||||
#endif
|
||||
Status = (s32)XST_SUCCESS;
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function resets the options for the QSPIPSU device driver.The options
|
||||
* control how the device behaves relative to the QSPIPSU bus. The device must be
|
||||
* idle rather than busy transferring data before setting these device options.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Options contains the specified options to be set. This is a bit
|
||||
* mask where a 1 indicates the option should be turned OFF and
|
||||
* a 0 indicates no action. One or more bit values may be
|
||||
* contained in the mask. See the bit definitions named
|
||||
* XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if options are successfully set.
|
||||
* - XST_DEVICE_BUSY if the device is currently transferring data.
|
||||
* The transfer must complete or be aborted before setting options.
|
||||
*
|
||||
* @note
|
||||
* This function is not thread-safe.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
u32 Index;
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Do not allow to modify the Control Register while a transfer is in
|
||||
* progress. Not thread-safe.
|
||||
*/
|
||||
if (InstancePtr->IsBusy == (u32)TRUE) {
|
||||
Status = (s32)XST_DEVICE_BUSY;
|
||||
} else {
|
||||
|
||||
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_CFG_OFFSET);
|
||||
|
||||
/*
|
||||
* Loop through the options table, turning the option on
|
||||
* depending on whether the bit is set in the incoming options flag.
|
||||
*/
|
||||
for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
|
||||
if ((Options & OptionsTable[Index].Option) != (u32)FALSE) {
|
||||
/* Turn it off */
|
||||
ConfigReg &= ~OptionsTable[Index].Mask;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Now write the control register. Leave it to the upper layers
|
||||
* to restart the device.
|
||||
*/
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
|
||||
ConfigReg);
|
||||
|
||||
if ((Options & XQSPIPSU_MANUAL_START_OPTION) != (u32)FALSE) {
|
||||
InstancePtr->IsManualstart = (u8)FALSE;
|
||||
}
|
||||
|
||||
Status = (s32)XST_SUCCESS;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function gets the options for the QSPIPSU device. The options control how
|
||||
* the device behaves relative to the QSPIPSU bus.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* Options contains the specified options currently set. This is a bit value
|
||||
* where a 1 means the option is on, and a 0 means the option is off.
|
||||
* See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 XQspiPsu_GetOptions(const XQspiPsu *InstancePtr)
|
||||
{
|
||||
u32 OptionsFlag = 0;
|
||||
u32 ConfigReg;
|
||||
u32 Index;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/* Loop through the options table to grab options */
|
||||
for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
|
||||
/*
|
||||
* Get the current options from QSPIPSU configuration register.
|
||||
*/
|
||||
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_CFG_OFFSET);
|
||||
if ((ConfigReg & OptionsTable[Index].Mask) != (u32)FALSE) {
|
||||
OptionsFlag |= OptionsTable[Index].Option;
|
||||
}
|
||||
}
|
||||
return OptionsFlag;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Configures the clock according to the prescaler passed.
|
||||
*
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Prescaler - clock prescaler to be set.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if successful.
|
||||
* - XST_DEVICE_IS_STARTED if the device is already started.
|
||||
* - XST_DEVICE_BUSY if the device is currently transferring data.
|
||||
* It must be stopped to re-initialize.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XQspiPsu_SetClkPrescaler(const XQspiPsu *InstancePtr, u8 Prescaler)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertNonvoid(Prescaler <= XQSPIPSU_CR_PRESC_MAXIMUM);
|
||||
|
||||
/*
|
||||
* Do not allow the slave select to change while a transfer is in
|
||||
* progress. Not thread-safe.
|
||||
*/
|
||||
if (InstancePtr->IsBusy == (u32)TRUE) {
|
||||
Status = (s32)XST_DEVICE_BUSY;
|
||||
} else {
|
||||
/*
|
||||
* Read the configuration register, mask out the relevant bits, and set
|
||||
* them with the shifted value passed into the function. Write the
|
||||
* results back to the configuration register.
|
||||
*/
|
||||
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_CFG_OFFSET);
|
||||
|
||||
ConfigReg &= ~(u32)XQSPIPSU_CFG_BAUD_RATE_DIV_MASK;
|
||||
ConfigReg |= (u32) ((u32)Prescaler & (u32)XQSPIPSU_CR_PRESC_MAXIMUM) <<
|
||||
XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT;
|
||||
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
|
||||
ConfigReg);
|
||||
|
||||
#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__)
|
||||
Status = XQspipsu_Calculate_Tapdelay(InstancePtr,Prescaler);
|
||||
#else
|
||||
Status = (s32)XST_SUCCESS;
|
||||
#endif
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function should be used to tell the QSPIPSU driver the HW flash
|
||||
* configuration being used. This API should be called at least once in the
|
||||
* application. If desired, it can be called multiple times when switching
|
||||
* between communicating to different flahs devices/using different configs.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param FlashCS - Flash Chip Select.
|
||||
* @param FlashBus - Flash Bus (Upper, Lower or Both).
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if successful.
|
||||
* - XST_DEVICE_IS_STARTED if the device is already started.
|
||||
* It must be stopped to re-initialize.
|
||||
*
|
||||
* @note If this function is not called at least once in the application,
|
||||
* the driver assumes there is a single flash connected to the
|
||||
* lower bus and CS line.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
|
||||
{
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(FlashCS > 0U);
|
||||
Xil_AssertVoid(FlashBus > 0U);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_SelectFlash\r\n");
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Bus and CS lines selected here will be updated in the instance and
|
||||
* used for subsequent GENFIFO entries during transfer.
|
||||
*/
|
||||
|
||||
/* Choose slave select line */
|
||||
switch (FlashCS) {
|
||||
case XQSPIPSU_SELECT_FLASH_CS_BOTH:
|
||||
InstancePtr->GenFifoCS = (u32)XQSPIPSU_GENFIFO_CS_LOWER |
|
||||
(u32)XQSPIPSU_GENFIFO_CS_UPPER;
|
||||
break;
|
||||
case XQSPIPSU_SELECT_FLASH_CS_UPPER:
|
||||
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_UPPER;
|
||||
break;
|
||||
case XQSPIPSU_SELECT_FLASH_CS_LOWER:
|
||||
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
|
||||
break;
|
||||
default:
|
||||
InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Choose bus */
|
||||
switch (FlashBus) {
|
||||
case XQSPIPSU_SELECT_FLASH_BUS_BOTH:
|
||||
InstancePtr->GenFifoBus = (u32)XQSPIPSU_GENFIFO_BUS_LOWER |
|
||||
(u32)XQSPIPSU_GENFIFO_BUS_UPPER;
|
||||
break;
|
||||
case XQSPIPSU_SELECT_FLASH_BUS_UPPER:
|
||||
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_UPPER;
|
||||
break;
|
||||
case XQSPIPSU_SELECT_FLASH_BUS_LOWER:
|
||||
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
|
||||
break;
|
||||
default:
|
||||
InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
|
||||
break;
|
||||
}
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nGenFifoCS is %08x and GenFifoBus is %08x\r\n",
|
||||
InstancePtr->GenFifoCS, InstancePtr->GenFifoBus);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the Read mode for the QSPIPSU device driver.The device
|
||||
* must be idle rather than busy transferring data before setting Read mode
|
||||
* options.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Mode contains the specified Mode to be set. See the
|
||||
* bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if options are successfully set.
|
||||
* - XST_DEVICE_BUSY if the device is currently transferring data.
|
||||
* The transfer must complete or be aborted before setting Mode.
|
||||
*
|
||||
* @note
|
||||
* This function is not thread-safe.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
s32 Status;
|
||||
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nXQspiPsu_SetReadMode\r\n");
|
||||
#endif
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertNonvoid((Mode == XQSPIPSU_READMODE_DMA) || (Mode == XQSPIPSU_READMODE_IO));
|
||||
|
||||
/*
|
||||
* Do not allow to modify the Control Register while a transfer is in
|
||||
* progress. Not thread-safe.
|
||||
*/
|
||||
if (InstancePtr->IsBusy == (u32)TRUE) {
|
||||
Status = (s32)XST_DEVICE_BUSY;
|
||||
} else {
|
||||
|
||||
InstancePtr->ReadMode = Mode;
|
||||
|
||||
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_CFG_OFFSET);
|
||||
|
||||
if (Mode == XQSPIPSU_READMODE_DMA) {
|
||||
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
|
||||
ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
|
||||
} else {
|
||||
ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
|
||||
}
|
||||
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
|
||||
ConfigReg);
|
||||
|
||||
Status = (s32)XST_SUCCESS;
|
||||
}
|
||||
#ifdef DEBUG
|
||||
xil_printf("\nRead Mode is %08x\r\n", InstancePtr->ReadMode);
|
||||
#endif
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the Write Protect and Hold options for the QSPIPSU device
|
||||
* driver.The device must be idle rather than busy transferring data before
|
||||
* setting Write Protect and Hold options.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XQspiPsu instance.
|
||||
* @param Value of the WP_HOLD bit in configuration register
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note
|
||||
* This function is not thread-safe. This function can only be used with single
|
||||
* flash configuration and x1/x2 data mode. This function cannot be used with
|
||||
* x4 data mode and dual parallel and stacked flash configuration.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XQspiPsu_SetWP(const XQspiPsu *InstancePtr, u8 Value)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid(InstancePtr->IsBusy != TRUE);
|
||||
|
||||
ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XQSPIPSU_CFG_OFFSET);
|
||||
ConfigReg |= (u32)((u32)Value << XQSPIPSU_CFG_WP_HOLD_SHIFT);
|
||||
XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
|
||||
ConfigReg);
|
||||
}
|
||||
/** @} */
|
||||
Reference in New Issue
Block a user