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bsps: Move start files to bsps

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This patch is a part of the BSP source reorganization.

Update #3285.
This commit is contained in:
Sebastian Huber
2018-04-20 10:19:28 +02:00
parent d7d66d7d45
commit fbcd7c8fa6
152 changed files with 112 additions and 112 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am
View File

@@ -33,7 +33,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/atsam/Makefile.am
View File

@@ -9,7 +9,7 @@ include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = startup/bsp_specs
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/beagle/Makefile.am
View File

@@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/csb336/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/csb336/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

166
c/src/lib/libbsp/arm/csb336/start/start.S
View File

@@ -1,166 +0,0 @@
/*
* Cogent CSB336 startup code
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/linker-symbols.h>
/* Some standard definitions...*/
.equ PSR_MODE_USR, 0x10
.equ PSR_MODE_FIQ, 0x11
.equ PSR_MODE_IRQ, 0x12
.equ PSR_MODE_SVC, 0x13
.equ PSR_MODE_ABT, 0x17
.equ PSR_MODE_UNDEF, 0x1B
.equ PSR_MODE_SYS, 0x1F
.equ PSR_I, 0x80
.equ PSR_F, 0x40
.equ PSR_T, 0x20
.section .bsp_start_text,"ax"
.code 32
_start_jump_at_origin:
ldr pc, _start_address
_start_address:
.word _start
.text
.globl _start
_start:
/*
* Since I don't plan to return to the bootloader,
* I don't have to save the registers.
*
* I'll just set the CPSR for SVC mode, interrupts
* off, and ARM instructions.
*/
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
msr cpsr, r0
/* zero the bss */
ldr r1, =bsp_section_bss_end
ldr r0, =bsp_section_bss_begin
_bss_init:
mov r2, #0
cmp r0, r1
strlot r2, [r0], #4
blo _bss_init /* loop while r0 < r1 */
/* --- Initialize stack pointer registers */
/* Enter IRQ mode and set up the IRQ stack pointer */
mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_irq_size
ldr sp, =bsp_stack_irq_begin
add sp, sp, r1
/* Enter FIQ mode and set up the FIQ stack pointer */
mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_fiq_size
ldr sp, =bsp_stack_fiq_begin
add sp, sp, r1
/* Enter ABT mode and set up the ABT stack pointer */
mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_abt_size
ldr sp, =bsp_stack_abt_begin
add sp, sp, r1
/* Enter UNDEF mode and set up the UNDEF stack pointer */
mov r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_und_size
ldr sp, =bsp_stack_und_begin
add sp, sp, r1
/* Set up the SVC stack pointer last and stay in SVC mode */
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_svc_size
ldr sp, =bsp_stack_svc_begin
add sp, sp, r1
sub sp, sp, #0x64
/*
* Initialize the MMU. After we return, the MMU is enabled,
* and memory may be remapped. I hope we don't remap this
* memory away.
*/
ldr r0, =mem_map
bl mmu_init
/*
* Initialize the exception vectors. This includes the
* exceptions vectors (0x00000000-0x0000001c), and the
* pointers to the exception handlers (0x00000020-0x0000003c).
*/
mov r0, #0
adr r1, vector_block
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
/* Now we are prepared to start the BSP's C code */
mov r0, #0
bl boot_card
/*
* Theoretically, we could return to what started us up,
* but we'd have to have saved the registers and stacks.
* Instead, we'll just reset.
*/
bl bsp_reset
/* We shouldn't get here. If we do, hang */
_hang: b _hang
/*
* This is the exception vector table and the pointers to
* the functions that handle the exceptions. It's a total
* of 16 words (64 bytes)
*/
vector_block:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
handler_addr_reset:
.word bsp_reset
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

2
c/src/lib/libbsp/arm/csb337/Makefile.am
View File

@@ -14,7 +14,7 @@ noinst_PROGRAMS =
if ENABLE_LCD
endif
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/csb337/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

152
c/src/lib/libbsp/arm/csb337/start/start.S
View File

@@ -1,152 +0,0 @@
/*
* Cogent CSB337 startup code
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/linker-symbols.h>
/* Some standard definitions...*/
.equ PSR_MODE_USR, 0x10
.equ PSR_MODE_FIQ, 0x11
.equ PSR_MODE_IRQ, 0x12
.equ PSR_MODE_SVC, 0x13
.equ PSR_MODE_ABT, 0x17
.equ PSR_MODE_UNDEF, 0x1B
.equ PSR_MODE_SYS, 0x1F
.equ PSR_I, 0x80
.equ PSR_F, 0x40
.equ PSR_T, 0x20
.text
.globl _start
_start:
/*
* Since I don't plan to return to the bootloader,
* I don't have to save the registers.
*
* I'll just set the CPSR for SVC mode, interrupts
* off, and ARM instructions.
*/
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
msr cpsr, r0
/* zero the bss */
ldr r1, =bsp_section_bss_end
ldr r0, =bsp_section_bss_begin
_bss_init:
mov r2, #0
cmp r0, r1
strlot r2, [r0], #4
blo _bss_init /* loop while r0 < r1 */
/* --- Initialize stack pointer registers */
/* Enter IRQ mode and set up the IRQ stack pointer */
mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_irq_size
ldr sp, =bsp_stack_irq_begin
add sp, sp, r1
/* Enter FIQ mode and set up the FIQ stack pointer */
mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_fiq_size
ldr sp, =bsp_stack_fiq_begin
add sp, sp, r1
/* Enter ABT mode and set up the ABT stack pointer */
mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_abt_size
ldr sp, =bsp_stack_abt_begin
add sp, sp, r1
/* Set up the SVC stack pointer last and stay in SVC mode */
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_svc_size
ldr sp, =bsp_stack_svc_begin
add sp, sp, r1
sub sp, sp, #0x64
/*
* Initialize the MMU. After we return, the MMU is enabled,
* and memory may be remapped. I hope we don't remap this
* memory away.
*/
ldr r0, =mem_map
bl mmu_init
/*
* Initialize the exception vectors. This includes the
* exceptions vectors (0x00000000-0x0000001c), and the
* pointers to the exception handlers (0x00000020-0x0000003c).
*/
mov r0, #0
adr r1, vector_block
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
/* Now we are prepared to start the BSP's C code */
mov r0, #0
bl boot_card
/*
* Theoretically, we could return to what started us up,
* but we'd have to have saved the registers and stacks.
* Instead, we'll just reset.
*/
bl bsp_reset
/* We shouldn't get here. If we do, hang */
_hang: b _hang
/*
* This is the exception vector table and the pointers to
* the functions that handle the exceptions. It's a total
* of 16 words (64 bytes)
*/
vector_block:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
handler_addr_reset:
.word bsp_reset
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

2
c/src/lib/libbsp/arm/edb7312/Makefile.am
View File

@@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/edb7312/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

136
c/src/lib/libbsp/arm/edb7312/start/start.S
View File

@@ -1,136 +0,0 @@
/*
* Cirrus EP7312 Startup code
*
* Copyright (c) 2010 embedded brains GmbH.
*
* Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
*
* Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/linker-symbols.h>
/* Some standard definitions...*/
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_ABORT, 0x17
.equ Mode_UNDEF, 0x1B
.equ Mode_SYS, 0x1F /*only available on ARM Arch. v4*/
.equ I_Bit, 0x80
.equ F_Bit, 0x40
.section ".bsp_start_text", "ax"
.arm
/*******************************************************
standard exception vectors table
*** Must be located at address 0
********************************************************/
Vector_Init_Block:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
handler_addr_reset:
.word _start
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default
.globl _start
_start:
/* store the sp */
mov r12, sp
/*
* Here is the code to initialize the low-level BSP environment
* (Chip Select, PLL, ....?)
*/
/* zero the bss */
LDR r1, =bsp_section_bss_end /* get end of ZI region */
LDR r0, =bsp_section_bss_begin /* load base address of ZI region */
zi_init:
MOV r2, #0
CMP r0, r1 /* loop whilst r0 < r1 */
STRLOT r2, [r0], #4
BLO zi_init
/* --- Initialise stack pointer registers */
/* Enter IRQ mode and set up the IRQ stack pointer */
MOV r0, #Mode_IRQ | I_Bit | F_Bit /* No interrupts */
MSR cpsr, r0
ldr r1, =bsp_stack_irq_size
LDR sp, =bsp_stack_irq_begin
add sp, sp, r1
sub sp, sp, #0x64
/* Enter FIQ mode and set up the FIQ stack pointer */
MOV r0, #Mode_FIQ | I_Bit | F_Bit /* No interrupts */
MSR cpsr, r0
ldr r1, =bsp_stack_fiq_size
LDR sp, =bsp_stack_fiq_begin
add sp, sp, r1
sub sp, sp, #0x64
/* Enter ABT mode and set up the ABT stack pointer */
MOV r0, #Mode_ABT | I_Bit | F_Bit /* No interrupts */
MSR cpsr, r0
ldr r1, =bsp_stack_abt_size
LDR sp, =bsp_stack_abt_begin
add sp, sp, r1
sub sp, sp, #0x64
/* Set up the SVC stack pointer last and stay in SVC mode */
MOV r0, #Mode_SVC | I_Bit | F_Bit /* No interrupts */
MSR cpsr, r0
ldr r1, =bsp_stack_svc_size
LDR sp, =bsp_stack_svc_begin
add sp, sp, r1
sub sp, sp, #0x64
/* save the original registers */
stmdb sp!, {r4-r12, lr}
/* --- Now we enter the C code */
mov r0, #0
bl boot_card
ldmia sp!, {r4-r12, lr}
mov sp, r12
mov pc, lr

2
c/src/lib/libbsp/arm/gdbarmsim/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/gumstix/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/gumstix/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

156
c/src/lib/libbsp/arm/gumstix/start/start.S
View File

@@ -1,156 +0,0 @@
/*
* By Yang Xi <hiyangxi@gmail.com>.
* Based upon CSB337
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/linker-symbols.h>
/* Some standard definitions...*/
.equ PSR_MODE_USR, 0x10
.equ PSR_MODE_FIQ, 0x11
.equ PSR_MODE_IRQ, 0x12
.equ PSR_MODE_SVC, 0x13
.equ PSR_MODE_ABT, 0x17
.equ PSR_MODE_UNDEF, 0x1B
.equ PSR_MODE_SYS, 0x1F
.equ PSR_I, 0x80
.equ PSR_F, 0x40
.equ PSR_T, 0x20
.text
.globl _start
_start:
/*
* Since I don't plan to return to the bootloader,
* I don't have to save the registers.
*
* I'll just set the CPSR for SVC mode, interrupts
* off, and ARM instructions.
*/
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
msr cpsr, r0
/* zero the bss */
ldr r1, =bsp_section_bss_end
ldr r0, =bsp_section_bss_begin
_bss_init:
mov r2, #0
cmp r0, r1
strlot r2, [r0], #4
blo _bss_init /* loop while r0 < r1 */
/* --- Initialize stack pointer registers */
/* Enter IRQ mode and set up the IRQ stack pointer */
mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_irq_size
ldr sp, =bsp_stack_irq_begin
add sp, sp, r1
/* Enter FIQ mode and set up the FIQ stack pointer */
mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_fiq_size
ldr sp, =bsp_stack_fiq_begin
add sp, sp, r1
/* Enter ABT mode and set up the ABT stack pointer */
mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_abt_size
ldr sp, =bsp_stack_abt_begin
add sp, sp, r1
/* Set up the SVC stack pointer last and stay in SVC mode */
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_und_size
ldr sp, =bsp_stack_und_begin
add sp, sp, r1
sub sp, sp, #0x64
/*
* Initialize the MMU. After we return, the MMU is enabled,
* and memory may be remapped. I hope we don't remap this
* memory away.
*/
ldr r0, =mem_map
bl mmu_init
/*
* Initialize the exception vectors. This includes the
* exceptions vectors (0x00000000-0x0000001c), and the
* pointers to the exception handlers (0x00000020-0x0000003c).
*/
mov r0, #0
adr r1, vector_block
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
/* Now we are prepared to start the BSP's C code */
mov r0, #0
bl boot_card
/*
* Theoretically, we could return to what started us up,
* but we'd have to have saved the registers and stacks.
* Instead, we'll just reset.
*/
bl bsp_reset
/* We shouldn't get here. If we do, hang */
_hang: b _hang
/*
* This is the exception vector table and the pointers to
* the functions that handle the exceptions. It's a total
* of 16 words (64 bytes)
*/
vector_block:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
handler_addr_reset:
.word bsp_reset
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

2
c/src/lib/libbsp/arm/imx/Makefile.am
View File

@@ -13,7 +13,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/lm3s69xx/Makefile.am
View File

@@ -9,7 +9,7 @@ include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = startup/bsp_specs
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/lpc176x/Makefile.am
View File

@@ -22,7 +22,7 @@ dist_project_lib_DATA = startup/bsp_specs
# ------ Data
# ----------------------------
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/lpc24xx/Makefile.am
View File

@@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/lpc32xx/Makefile.am
View File

@@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/raspberrypi/Makefile.am
View File

@@ -22,7 +22,7 @@ noinst_HEADERS = ../../../../../../bsps/arm/raspberrypi/console/font_data.h
# Data #
###############################################################################
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
View File

@@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/rtl22xx/Makefile.am
View File

@@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/rtl22xx/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

157
c/src/lib/libbsp/arm/rtl22xx/start/start.S
View File

@@ -1,157 +0,0 @@
/*
* Philips LPC22XX/LPC21xx Startup code
*
* Copyright (c) 2007 Ray Xu<rayx.cn@gmail.com>
* Change from CSB337's code by Jay Monkman <jtm@lopingdog.com>
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/linker-symbols.h>
/* Some standard definitions...*/
.equ PSR_MODE_USR, 0x10
.equ PSR_MODE_FIQ, 0x11
.equ PSR_MODE_IRQ, 0x12
.equ PSR_MODE_SVC, 0x13
.equ PSR_MODE_ABT, 0x17
.equ PSR_MODE_UNDEF, 0x1B
.equ PSR_MODE_SYS, 0x1F
.equ PSR_I, 0x80
.equ PSR_F, 0x40
.equ PSR_T, 0x20
.text
.code 32
.globl _start
_start:
/*
* Since I don't plan to return to the bootloader,
* I don't have to save the registers.
*
* I'll just set the CPSR for SVC mode, interrupts
* off, and ARM instructions.
*/
/* --- Initialize stack pointer registers */
/* Enter IRQ mode and set up the IRQ stack pointer */
mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */
bic r0, r0, #PSR_T
msr cpsr, r0
ldr r1, =bsp_stack_irq_size
ldr sp, =bsp_stack_irq_begin
add sp, sp, r1
/* Enter FIQ mode and set up the FIQ stack pointer */
mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */
bic r0, r0, #PSR_T
msr cpsr, r0
ldr r1, =bsp_stack_fiq_size
ldr sp, =bsp_stack_fiq_begin
add sp, sp, r1
/* Enter ABT mode and set up the ABT stack pointer */
mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */
bic r0, r0, #PSR_T
msr cpsr, r0
bic r0, r0, #PSR_T
ldr r1, =bsp_stack_abt_size
ldr sp, =bsp_stack_abt_begin
add sp, sp, r1
/* Set up the SVC stack pointer last and stay in SVC mode */
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */
bic r0, r0, #PSR_T
msr cpsr, r0
ldr r1, =bsp_stack_svc_size
ldr sp, =bsp_stack_svc_begin
add sp, sp, r1
sub sp, sp, #0x64
/*
* Initialize the exception vectors. This includes the
* exceptions vectors (0x00000000-0x0000001c), and the
* pointers to the exception handlers (0x00000020-0x0000003c).
*/
mov r0, #0
adr r1, vector_block
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
/* zero the bss */
ldr r1, =bsp_section_bss_end
ldr r0, =bsp_section_bss_begin
_bss_init:
mov r2, #0
cmp r0, r1
strlot r2, [r0], #4
blo _bss_init /* loop while r0 < r1 */
/* Now we are prepared to start the BSP's C code */
mov r0, #0
#ifdef __thumb__
ldr r3, =boot_card
bx r3
#else
bl boot_card
/*
* Theoretically, we could return to what started us up,
* but we'd have to have saved the registers and stacks.
* Instead, we'll just reset.
*/
bl bsp_reset
#endif
.code 32
/* We shouldn't get here. If we do, hang */
_hang: b _hang
/*******************************************************
standard exception vectors table
*** Must be located at address 0
********************************************************/
vector_block:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
handler_addr_reset:
.word _start
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

462
c/src/lib/libbsp/arm/shared/start/start.S
View File

@@ -1,462 +0,0 @@
/**
* @file
*
* @brief Boot and system start code.
*/
/*
* Copyright (c) 2008, 2016 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
#include <rtems/system.h>
#include <rtems/score/percpu.h>
#include <bspopts.h>
#include <bsp/irq.h>
#include <bsp/linker-symbols.h>
/* External symbols */
.extern bsp_reset
.extern boot_card
.extern bsp_start_hook_0
.extern bsp_start_hook_1
.extern bsp_stack_irq_end
.extern bsp_stack_fiq_end
.extern bsp_stack_abt_end
.extern bsp_stack_und_end
.extern bsp_stack_svc_end
#ifdef RTEMS_SMP
.extern bsp_stack_all_size
#endif
.extern _ARMV4_Exception_undef_default
.extern _ARMV4_Exception_swi_default
.extern _ARMV4_Exception_data_abort_default
.extern _ARMV4_Exception_pref_abort_default
.extern _ARMV4_Exception_reserved_default
.extern _ARMV4_Exception_interrupt
.extern _ARMV4_Exception_fiq_default
.extern _ARMV7M_Exception_default
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
.extern bsp_start_init_registers_core
.extern bsp_start_init_registers_banked_fiq
.extern bsp_start_init_registers_vfp
#endif
#ifdef BSP_START_IN_HYP_SUPPORT
.extern bsp_start_arm_drop_hyp_mode
.globl bsp_start_hyp_vector_table_begin
#endif
/* Global symbols */
.globl _start
.globl bsp_start_vector_table_begin
.globl bsp_start_vector_table_end
.globl bsp_start_vector_table_size
.globl bsp_vector_table_size
.globl bsp_start_hook_0_done
.section ".bsp_start_text", "ax"
#if defined(ARM_MULTILIB_ARCH_V4)
.arm
/*
* This is the exception vector table and the pointers to the default
* exceptions handlers.
*/
bsp_start_vector_table_begin:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
/* Program signature checked by boot loader */
.word 0xb8a06f58
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
handler_addr_reset:
#ifdef BSP_START_RESET_VECTOR
.word BSP_START_RESET_VECTOR
#else
.word _start
#endif
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default
bsp_start_vector_table_end:
#ifdef BSP_START_IN_HYP_SUPPORT
bsp_start_hyp_vector_table_begin:
ldr pc, handler_addr_hyp_reset
ldr pc, handler_addr_hyp_undef
ldr pc, handler_addr_hyp_swi
ldr pc, handler_addr_hyp_prefetch
ldr pc, handler_addr_hyp_abort
ldr pc, handler_addr_hyp_hyp
ldr pc, handler_addr_hyp_irq
ldr pc, handler_addr_hyp_fiq
handler_addr_hyp_reset:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_undef:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_swi:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_prefetch:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_abort:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_hyp:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_irq:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_fiq:
.word _ARMV4_Exception_reserved_default
bsp_start_hyp_vector_table_end:
#endif
/* Start entry */
_start:
/*
* We do not save the context since we do not return to the boot
* loader but preserve r1 and r2 to allow access to bootloader parameters
*/
#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
mov r5, r1 /* machine type number or ~0 for DT boot */
mov r6, r2 /* physical address of ATAGs or DTB */
#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
bl bsp_start_init_registers_core
#endif
#ifdef RTEMS_SMP
/* Read MPIDR and get current processor index */
mrc p15, 0, r7, c0, c0, 5
and r7, #0xff
#endif
#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
#ifdef RTEMS_SMP
cmp r7, #0
bne 1f
#endif
mov r0, r6
bl bsp_fdt_copy
1:
#endif
#ifdef RTEMS_SMP
/*
* Get current per-CPU control and store it in PL1 only Thread ID
* Register (TPIDRPRW).
*/
ldr r1, =_Per_CPU_Information
add r1, r1, r7, asl #PER_CPU_CONTROL_SIZE_LOG2
mcr p15, 0, r1, c13, c0, 4
/* Calculate stack offset */
ldr r1, =bsp_stack_all_size
mul r1, r7
#endif
mrs r4, cpsr /* save original procesor status value */
#ifdef BSP_START_IN_HYP_SUPPORT
orr r0, r4, #(ARM_PSR_I | ARM_PSR_F)
msr cpsr, r4
and r0, r4, #ARM_PSR_M_MASK
cmp r0, #ARM_PSR_M_HYP
bne bsp_start_skip_hyp_svc_switch
/* Boot loader stats kernel in HYP mode, switch to SVC necessary */
ldr sp, =bsp_stack_hyp_end
#ifdef RTEMS_SMP
add sp, r1
#endif
bl bsp_start_arm_drop_hyp_mode
bsp_start_skip_hyp_svc_switch:
#endif
/*
* Set SVC mode, disable interrupts and enable ARM instructions.
*/
mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
/* Initialize stack pointer registers for the various modes */
/* Enter IRQ mode and set up the IRQ stack pointer */
mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr sp, =bsp_stack_irq_end
#ifdef RTEMS_SMP
add sp, r1
#endif
/* Enter FIQ mode and set up the FIQ stack pointer */
mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr sp, =bsp_stack_fiq_end
#ifdef RTEMS_SMP
add sp, r1
#endif
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_banked_fiq
#endif
/* Enter ABT mode and set up the ABT stack pointer */
mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr sp, =bsp_stack_abt_end
#ifdef RTEMS_SMP
add sp, r1
#endif
/* Enter UND mode and set up the UND stack pointer */
mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr sp, =bsp_stack_und_end
#ifdef RTEMS_SMP
add sp, r1
#endif
/* Enter SVC mode and set up the SVC stack pointer */
mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr sp, =bsp_stack_svc_end
#ifdef RTEMS_SMP
add sp, r1
#endif
/* Stay in SVC mode */
#ifdef ARM_MULTILIB_VFP
#ifdef ARM_MULTILIB_HAS_CPACR
/* Read CPACR */
mrc p15, 0, r0, c1, c0, 2
/* Enable CP10 and CP11 */
orr r0, r0, #(1 << 20)
orr r0, r0, #(1 << 22)
/*
* Clear ASEDIS and D32DIS. Writes to D32DIS are ignored for VFP-D16.
*/
bic r0, r0, #(3 << 30)
/* Write CPACR */
mcr p15, 0, r0, c1, c0, 2
isb
#endif
/* Enable FPU */
mov r0, #(1 << 30)
vmsr FPEXC, r0
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_vfp
#endif
#endif /* ARM_MULTILIB_VFP */
/*
* Branch to start hook 0.
*
* The previous code and parts of the start hook 0 may run with an
* address offset. This implies that only branches relative to the
* program counter are allowed. After the start hook 0 it is assumed
* that the code can run at its intended position. Thus the link
* register will be loaded with the absolute address. In THUMB mode
* the start hook 0 must be within a 2kByte range due to the branch
* instruction limitation.
*/
ldr lr, =bsp_start_hook_0_done
#ifdef __thumb__
orr lr, #1
#endif
SWITCH_FROM_ARM_TO_THUMB r0
mov r0, r4 /* original cpsr value */
mov r1, r5 /* machine type number or ~0 for DT boot */
mov r2, r6 /* physical address of ATAGs or DTB */
b bsp_start_hook_0
bsp_start_hook_0_done:
SWITCH_FROM_THUMB_TO_ARM
/*
* Initialize the exception vectors. This includes the exceptions
* vectors and the pointers to the default exception handlers.
*/
stmdb sp!, {r4, r5, r6}
ldr r0, =bsp_vector_table_begin
adr r1, bsp_start_vector_table_begin
cmp r0, r1
beq bsp_vector_table_copy_done
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
bsp_vector_table_copy_done:
ldmia sp!, {r0, r1, r2}
SWITCH_FROM_ARM_TO_THUMB r3
/* Branch to start hook 1 */
bl bsp_start_hook_1
/* Branch to boot card */
mov r0, #0
bl boot_card
twiddle:
/* Branch to reset function */
bl bsp_reset
b twiddle
#elif defined(ARM_MULTILIB_ARCH_V7M)
#include <rtems/score/armv7m.h>
.syntax unified
.extern bsp_stack_main_end
.thumb
bsp_start_vector_table_begin:
.word bsp_stack_main_end
.word _start /* Reset */
.word _ARMV7M_Exception_default /* NMI */
.word _ARMV7M_Exception_default /* Hard Fault */
.word _ARMV7M_Exception_default /* MPU Fault */
.word _ARMV7M_Exception_default /* Bus Fault */
.word _ARMV7M_Exception_default /* Usage Fault */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* SVC */
.word _ARMV7M_Exception_default /* Debug Monitor */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* PendSV */
.word _ARMV7M_Exception_default /* SysTick */
.rept BSP_INTERRUPT_VECTOR_MAX + 1
.word _ARMV7M_Exception_default /* IRQ */
.endr
bsp_start_vector_table_end:
.thumb_func
_start:
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_core
#endif
#ifdef ARM_MULTILIB_VFP
#ifdef ARM_MULTILIB_HAS_CPACR
/*
* Enable CP10 and CP11 coprocessors for privileged and user mode in
* CPACR (bits 20-23). Ensure that write to register completes.
*/
ldr r0, =ARMV7M_CPACR
ldr r1, [r0]
orr r1, r1, #(0xf << 20)
str r1, [r0]
dsb
isb
#endif
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_vfp
#endif
#endif /* ARM_MULTILIB_VFP */
ldr sp, =bsp_stack_main_end
ldr lr, =bsp_start_hook_0_done + 1
b bsp_start_hook_0
bsp_start_hook_0_done:
bl bsp_start_hook_1
movs r0, #0
bl boot_card
twiddle:
bl bsp_reset
b twiddle
#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
.set bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin
.set bsp_vector_table_size, bsp_start_vector_table_size

2
c/src/lib/libbsp/arm/smdk2410/Makefile.am
View File

@@ -6,7 +6,7 @@ include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = startup/bsp_specs
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/smdk2410/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

205
c/src/lib/libbsp/arm/smdk2410/start/start.S
View File

@@ -1,205 +0,0 @@
/*
* SMDK2410 startup code
*/
/*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/linker-symbols.h>
/* Some standard definitions...*/
.equ PSR_MODE_USR, 0x10
.equ PSR_MODE_FIQ, 0x11
.equ PSR_MODE_IRQ, 0x12
.equ PSR_MODE_SVC, 0x13
.equ PSR_MODE_ABT, 0x17
.equ PSR_MODE_UNDEF, 0x1B
.equ PSR_MODE_SYS, 0x1F
.equ PSR_I, 0x80
.equ PSR_F, 0x40
.equ PSR_T, 0x20
.text
.globl _start
_start:
b _start2
@---------------------------------------------------------------------------------
@ AXF addresses
@---------------------------------------------------------------------------------
.word bsp_section_text_begin
.word bsp_section_rodata_end
.word bsp_section_data_begin
.word bsp_section_bss_end
.word bsp_section_bss_begin
.word bsp_section_bss_end
@---------------------------------------------------------------------------------
@ GamePark magic sequence
@---------------------------------------------------------------------------------
.word 0x44450011
.word 0x44450011
.word 0x01234567
.word 0x12345678
.word 0x23456789
.word 0x34567890
.word 0x45678901
.word 0x56789012
.word 0x23456789
.word 0x34567890
.word 0x45678901
.word 0x56789012
.word 0x23456789
.word 0x34567890
.word 0x45678901
.word 0x56789012
@---------------------------------------------------------------------------------
_start2:
@---------------------------------------------------------------------------------
/*
* Since I don't plan to return to the bootloader,
* I don't have to save the registers.
*
* I'll just set the CPSR for SVC mode, interrupts
* off, and ARM instructions.
*/
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
msr cpsr, r0
/* --- Initialize stack pointer registers */
/* Enter IRQ mode and set up the IRQ stack pointer */
mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_irq_size
ldr sp, =bsp_stack_irq_begin
add sp, sp, r1
/* Enter FIQ mode and set up the FIQ stack pointer */
mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_fiq_size
ldr sp, =bsp_stack_fiq_begin
add sp, sp, r1
/* Enter ABT mode and set up the ABT stack pointer */
mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_abt_size
ldr sp, =bsp_stack_abt_begin
add sp, sp, r1
/* Set up the SVC stack pointer last and stay in SVC mode */
mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */
msr cpsr, r0
ldr r1, =bsp_stack_svc_size
ldr sp, =bsp_stack_svc_begin
add sp, sp, r1
sub sp, sp, #0x64
/* disable mmu, I and D caches*/
nop
nop
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x01
bic r0, r0, #0x04
bic r0, r0, #0x01000
mcr p15, 0, r0, c1, c0, 0
nop
nop
/* clean data cache */
mov r1,#0x00
Loop1:
mov r2,#0x00
Loop2:
mov r3, r2, lsl#26
orr r3, r3, r1, lsl#5
mcr p15, 0, r3, c7, c14, 2
add r2, r2, #0x01
cmp r2, #64
bne Loop2
add r1, r1, #0x01
cmp r1, #8
bne Loop1
/*
* Initialize the MMU. After we return, the MMU is enabled,
* and memory may be remapped. I hope we don't remap this
* memory away.
*/
ldr r0, =mem_map
bl mmu_init
/*
* Initialize the exception vectors. This includes the
* exceptions vectors (0x00000000-0x0000001c), and the
* pointers to the exception handlers (0x00000020-0x0000003c).
*/
mov r0, #0
adr r1, vector_block
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
/* Now we are prepared to start the BSP's C code */
mov r0, #0
bl boot_card
/*
* Theoretically, we could return to what started us up,
* but we'd have to have saved the registers and stacks.
* Instead, we'll just reset.
*/
bl bsp_reset
/* We shouldn't get here. If we do, hang */
_hang: b _hang
/*
* This is the exception vector table and the pointers to
* the functions that handle the exceptions. It's a total
* of 16 words (64 bytes)
*/
vector_block:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
nop
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
handler_addr_reset:
.word bsp_reset
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default

2
c/src/lib/libbsp/arm/stm32f4/Makefile.am
View File

@@ -9,7 +9,7 @@ include $(top_srcdir)/../../bsp.am
dist_project_lib_DATA = startup/bsp_specs
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/tms570/Makefile.am
View File

@@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs
# ------ Data
# ----------------------------
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
View File

@@ -20,7 +20,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/bfin/TLL6527M/Makefile.am
View File

@@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/bfin/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/bfin/bf537Stamp/Makefile.am
View File

@@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/bfin/bf537Stamp/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

115
c/src/lib/libbsp/bfin/bf537Stamp/start/start.S
View File

@@ -1,115 +0,0 @@
#include <libcpu/bf537.h>
#include <libcpu/sicRegs.h>
#include <libcpu/cecRegs.h>
#include <libcpu/dmaRegs.h>
#include <libcpu/coreTimerRegs.h>
#ifndef LO
#define LO(con32) ((con32) & 0xFFFF)
#endif
#ifndef HI
#define HI(con32) (((con32) >> 16) & 0xFFFF)
#endif
.section .start
.align 4
.global __start
__start:
cli r0;
/* setup an initial stack */
sp.h = 0xFFB0;
sp.l = 0x0F00;
/* disable timer interrupts */
p0.h = HI(TCNTL);
p0.l = LO(TCNTL);
r0 = 0;
[p0] = r0;
/* disable all interrupts routed through sic */
p0.h = HI(SIC_IMASK);
p0.l = LO(SIC_IMASK);
[p0] = r0;
/* clear any pending interrupts */
p0.h = HI(CEC_ILAT);
p0.l = LO(CEC_ILAT);
r0 = 0xffff (z);
[p0] = r0;
/* disable all dma channels */
p0.h = HI(DMA0_BASE_ADDRESS + DMA_CONFIG_OFFSET);
p0.l = LO(DMA0_BASE_ADDRESS + DMA_CONFIG_OFFSET);
p1 = DMA_PITCH;
p2 = DMA_CHANNELS;
r0 = ~DMA_CONFIG_DMAEN;
lsetup(loop1,loop2) lc0 = p2;
loop1: r1 = w[p0];
r1 = r0 & r1;
loop2: w[p0 ++ p1] = r1.l;
/* this is so we can stay in supervisor mode and still be able to
accept interrupts later. */
p0.h = start;
p0.l = start;
p1.h = HI(CEC_EVT15);
p1.l = LO(CEC_EVT15);
[p1] = p0;
r0 = 0x8000 (z);
sti r0;
raise 15;
p0.h = wait;
p0.l = wait;
reti = p0;
rti;
/* wait for event 15 */
wait:
jump wait;
start:
[--sp] = reti; /* allow us to process interrupts later */
/* mask interrupts for now */
cli r0;
p0.h = _bss_start;
p0.l = _bss_start;
p1.h = _end;
p1.l = _end;
r0 = p0;
r1 = p1;
r1 = r1 - r0;
p1 = r1;
r0 = 0;
/* Set _bss_start until _end to zero */
lsetup(loop3,loop4) lc0 = p1;
loop3: b[p0] = r0;
loop4: p0 +=1;
l0 = 0;
l1 = 0;
l2 = 0;
l3 = 0;
sp += -12;
/* r0 == const char *cmdline (currently null) */
p0.h = _boot_card;
p0.l = _boot_card;
call (p0);
sp += 12;
.global _bsp_reset
_bsp_reset:
HLT
p0.h = _exit;
p0.l = _exit;
jump (p0);

2
c/src/lib/libbsp/bfin/eZKit533/Makefile.am
View File

@@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/bfin/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

95
c/src/lib/libbsp/bfin/shared/start/start.S
View File

@@ -1,95 +0,0 @@
#include <rtems/bfin/bfin.h>
#include <bsp.h>
#include <bspopts.h>
#ifndef LO
#define LO(con32) ((con32) & 0xFFFF)
#endif
#ifndef HI
#define HI(con32) (((con32) >> 16) & 0xFFFF)
#endif
#if (BFIN_ON_SKYEYE)
.section .init
#else
.section .l1code
#endif
.align 4
.global __start
__start:
/* Start by setting up a stack */
sp.h = 0xFFB0;
sp.l = 0x0F00;
/* Maybe we should zero the memory in the .bss section. */
/* This changes to the supervisor mode */
p0.l = START;
p0.h = START;
p1.l = LO(EVT15);
p1.h = HI(EVT15);
[P1] = P0;
P0.h = HI(IMASK);
P0.l = LO(IMASK);
R0 = [P0];
/* R1.l = EVT_IVG15 & 0xFFFF; */
R1.l = 0x8000;
R0 = R0 | R1;
[P0] = R0;
RAISE 15;
P0.l = WAIT;
P0.h = WAIT;
RETI = P0;
RTI;
/* endless loop to wait */
WAIT:
jump WAIT;
START:
[--SP] = RETI;
p0.h = _bss_start;
p0.l = _bss_start;
p1.h = _end;
p1.l = _end;
r0 = p0;
r1 = p1;
r1 = r1 - r0;
p1 = r1;
r0 = 0;
/* Set _bss_start until _end to zero */
lsetup(loop1,loop2) LC0 = p1;
loop1: b[p0] = r0;
loop2: p0 +=1;
/* call boot_card( 0, 0 ) */
r0 = 0;
r1 = 0;
p0.l = _boot_card;
p0.h = _boot_card;
call (p0);
HLT
p0.l = _exit;
p0.h = _exit;
P3 = P4;
jump (p0) /* Should not return. */
.global _bfin_null_isr
_bfin_null_isr:
rti;

2
c/src/lib/libbsp/epiphany/epiphany_sim/Makefile.am
View File

@@ -18,7 +18,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/epiphany/epiphany_sim/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

167
c/src/lib/libbsp/epiphany/epiphany_sim/start/start.S
View File

@@ -1,167 +0,0 @@
/*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <bsp/linker-symbols.h>
#include <rtems/asm.h>
EXTERN(bsp_section_bss_begin)
EXTERN(bsp_section_bss_end)
EXTERN(_ISR_Handler)
EXTERN(bsp_start_vector_table_end)
EXTERN(bsp_start_vector_table_size)
EXTERN(bsp_vector_table_size)
EXTERN(bsp_section_stack_begin)
PUBLIC(_EPIPHANY_Exception_default)
PUBLIC(bsp_start_vector_table_begin)
PUBLIC(_start)
.section .vector, "wax"
TYPE_FUNC(_start)
SYM(_start):
.balign 4 ;
b .normal_start
.balign 4 ; 0x4
b .sw_exception
.balign 4 ; 0x8
b .normal_start
.balign 4 ; 0xc
b .clock_isr
.balign 4 ; 0x10
b .timer1_isr
.balign 4 ; 0x14
b _EPIPHANY_Exception_default
.balign 4 ; 0x18
b _EPIPHANY_Exception_default
.balign 4 ; 0x1c
b _EPIPHANY_Exception_default
.balign 4 ; 0x20
b _EPIPHANY_Exception_default
.balign 4 ; 0x24
b _EPIPHANY_Exception_default
bsp_start_vector_table_begin:
.word .normal_start /* Reset */
.word _EPIPHANY_Exception_default /* SW exception */
.word _EPIPHANY_Exception_default /* Data Page Fault */
.word _EPIPHANY_Exception_default /* Timer 0 */
.word _EPIPHANY_Exception_default /* Timer 1 */
.word _EPIPHANY_Exception_default /* Message int */
.word _EPIPHANY_Exception_default /* DMA0 int */
.word _EPIPHANY_Exception_default /* DMA1 int */
.word _EPIPHANY_Exception_default /* WAND */
.word _EPIPHANY_Exception_default /* User interrupt */
_bsp_start_vector_table_end:
.size _start, .-_start
.section .start,"ax"
.align 4
.type _external_start, %function
.normal_start:
/* Initialize the stack and frame pointers */
mov sp, %low(bsp_section_stack_begin)
movt sp, %high(bsp_section_stack_begin)
mov fp, sp
cpu0:
/* Zero .bss section */
mov r0, %low(bsp_section_bss_begin)
movt r0, %high(bsp_section_bss_begin)
mov r1, sp
mov r2,#0
mov r3,#0
_bss_clear_loop:
strd r2, [r0], +#1
sub r5, r1, r0
bne _bss_clear_loop
/* Clear the reset interrupt flag */
mov r0, %low(_jump_to_c)
movt r0, %high(_jump_to_c)
movts iret, r0
rti
_jump_to_c:
/* Jump to bootcard */
mov r3, %low(boot_card)
movt r3, %high(boot_card)
jalr r3
/* Should never reach here */
idle
.size .normal_start, .-.normal_start
.balign 4
.type .sw_exception, %function
.sw_exception:
idle
.balign 4
.type .clock_isr, %function
.clock_isr:
/*
* r62 and r63 are saved here, and restored from _ISR_Handler, they
* and hold vector number and _ISR_Handler address repsectively.
*/
add sp, sp, #-8
str r62, [sp, #0]
str r63, [sp, #4]
mov r62, 3
mov r63, %low(_ISR_Handler)
movt r63, %high(_ISR_Handler)
jr r6
.balign 4
.type .timer1_isr, %function
.timer1_isr:
/*
* r62 and r63 are saved here, and restored from _ISR_Handler, they
* and hold vector number and _ISR_Handler address repsectively.
*/
add sp, sp, #-8
str r62, [sp, 0]
str r63, [sp, 4]
mov r62, 4
mov r63, %low(_ISR_Handler)
movt r63, %high(_ISR_Handler)
jr r63
.balign 4
TYPE_FUNC(_EPIPHANY_Exception_default)
SYM(_EPIPHANY_Exception_default):
idle

6
c/src/lib/libbsp/i386/pc386/Makefile.am
View File

@@ -20,11 +20,11 @@ _SUBDIRS = . tools
TMPINSTALL_FILES =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/i386/pc386/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
start16.$(OBJEXT): start/start16.S
start16.$(OBJEXT): ../../../../../../bsps/i386/pc386/start/start16.S
$(CPPASCOMPILE) $(AM_CPPFLAGS) -DHEADERADDR=$(HEADERADDR) -o $@ -c $<
start16-elf32.$(OBJEXT): start16.$(OBJEXT)
@@ -136,7 +136,7 @@ librtemsbsp_a_SOURCES += ../shared/smp/getcpuid.c
librtemsbsp_a_SOURCES += ../shared/smp/smp-imps.c
project_lib_DATA += appstart.$(OBJEXT)
appcpustart.$(OBJEXT): start/start16.S
appcpustart.$(OBJEXT): ../../../../../../bsps/i386/pc386/start/start16.S
$(CPPASCOMPILE) $(AM_CPPFLAGS) -DSMP_SECONDARY_CORE -o $@ -c $<
appstart.$(OBJEXT): appcpustart.$(OBJEXT)

345
c/src/lib/libbsp/i386/pc386/start/start.S
View File

@@ -1,345 +0,0 @@
/*-------------------------------------------------------------------------+
| start.s v1.1 - PC386 BSP - 1997/08/07
+--------------------------------------------------------------------------+
| This file contains the entry point for the application.
| The name of this entry point is compiler dependent.
| It jumps to the BSP which is responsible for performing all initialization.
+--------------------------------------------------------------------------+
| (C) Copyright 1997 -
| - NavIST Group - Real-Time Distributed Systems and Industrial Automation
|
| http://pandora.ist.utl.pt
|
| Instituto Superior Tecnico * Lisboa * PORTUGAL
+--------------------------------------------------------------------------+
| Modified the 20/05/1998 by valette@crf.canon.fr in order to give a working
| example of eraly stage debugging via the DEBUG_EARLY_START define.
+--------------------------------------------------------------------------+
| Disclaimer:
|
| This file is provided "AS IS" without warranty of any kind, either
| expressed or implied.
+--------------------------------------------------------------------------+
| This code is based on an earlier generation RTEMS i386 start.s and the
| following copyright applies:
|
| **************************************************************************
| * COPYRIGHT (c) 1989-2012.
| * On-Line Applications Research Corporation (OAR).
| *
| * The license and distribution terms for this file may be
| * found in the file LICENSE in this distribution or at
| * http://www.rtems.org/license/LICENSE.
| **************************************************************************
+--------------------------------------------------------------------------*/
/*
* The most trivial start.s possible. It does not know anything
* about system it is running on, so it will jump to appropriate
* place in BSP specific place to do things it knows nothing about
*/
#include <rtems/asm.h>
#include <rtems/score/cpu.h>
#include <bspopts.h>
/*----------------------------------------------------------------------------+
| Size of heap and stack:
+----------------------------------------------------------------------------*/
#ifndef CPU_STACK_ALIGNMENT
#error "Missing header ? CPU_STACK_ALIGNMENT NOT DEFINED"
#endif
.set STACK_SIZE, 0x1000
/*----------------------------------------------------------------------------+
| CODE section
+----------------------------------------------------------------------------*/
BEGIN_CODE
PUBLIC (start) # GNU default entry point
EXTERN (boot_card)
#if USE_VBE_RM
EXTERN (vesa_realmode_bootup_init)
#endif
EXTERN (_load_segments)
EXTERN (_return_to_monitor)
EXTERN (_IBMPC_initVideo)
EXTERN (debugPollingGetChar)
EXTERN (checkCPUtypeSetCr0)
EXTERN (printk)
#ifdef __SSE__
EXTERN (x86_capability)
#ifdef __SSE3__
EXTERN (x86_capability_x)
#endif
#endif
/*
* In case this crashes on your machine and this is not due
* to video mode set by the loader, you may try to define
* the following variable:
*/
/* #define DEBUG_EARLY_START */
SYM (start):
/*
* When things are really, REALLY!, bad -- turn on the speaker and
* lock up. This shows whether or not we make it to a certain
* location.
*/
#if 0
inb $0x61, al
orb $0x03, al
outb al, $0x61 # enable the speaker
speakl: jmp speakl # and SPIN!!!
#endif
nop
cli # DISABLE INTERRUPTS!!!
cld
/* Save multiboot info if we detect a multiboot loader */
cmp $0x2badb002,eax
jne 2f
/* We have multiboot info; let's hope DS and ES are OK... */
movl ebx, SYM(_boot_multiboot_info_p)
/* Check for memory size info and save */
movl ebx, esi
movl (esi), eax
movl eax, ebx
movl $SYM(_boot_multiboot_info), edi
/* save flags, always present */
movsd
/* flag 1 is memory */
and $1, eax
je 1f
movl $2, ecx
rep movsd
/* flag 2 is the command line */
1: movl ebx, eax
and $4, eax
je 3f
movl (_boot_multiboot_info_p), eax
movl 16(eax), esi
movl $255, ecx
2: movzbl (esi), eax
test al, al
je 3f
movb al, (edi)
inc edi
inc esi
dec ecx
je 3f
jmp 2b
3: xor al, al
movb al, (edi)
#ifdef DEBUG_EARLY_START
/*
* Must get video attribute to have a working printk.
* Note that the following code assume we already have
* valid segments and a stack. It should be true for
* any loader starting RTEMS in protected mode (or
* at least I hope so : -)).
*/
call _IBMPC_initVideo
/*
* try printk and a getchar in polling mode ASAP
*/
movl $welcome_msg, 0(esp)
call printk
addl $4, esp
/* call debugPollingGetChar */
#endif
/*----------------------------------------------------------------------------+
| Load the segment registers (this is done by the board's BSP) and perform any
| other board specific initialization procedures, this piece of code
| does not know anything about
|
| NOTE: Upon return, gs will contain the segment descriptor for a segment which
| maps directly to all of physical memory.
+----------------------------------------------------------------------------*/
jmp SYM (_load_segments) # load board dependent segments
/*----------------------------------------------------------------------------+
| Set up the stack
+----------------------------------------------------------------------------*/
PUBLIC (_establish_stack)
SYM (_establish_stack):
movl $_end, eax # eax = end of bss/start of heap
addl $STACK_SIZE, eax # make room for stack
subl $4, eax # reserve room for arg to 'boot_card'
andl $ - CPU_STACK_ALIGNMENT, eax # align SP on CPU_STACK_ALIGNMENT boundary
movl eax, esp # set stack pointer
movl eax, ebp # set base pointer
/*----------------------------------------------------------------------------+
| Zero out the BSS segment
+----------------------------------------------------------------------------*/
SYM (zero_bss):
cld # make direction flag count up
movl $ SYM (_end), ecx # find end of .bss
movl $ SYM (__bss_start), edi # edi = beginning of .bss
subl edi, ecx # ecx = size of .bss in bytes
shrl ecx # size of .bss in longs
shrl ecx
xorl eax, eax # value to clear out memory
repne # while ecx != 0
stosl # clear a long in the bss
#if BSP_ENABLE_VGA
/*-------------------------------------------------------------------+
| Initialize the video because zero_bss has cleared initVideo parameters
| if it was called earlier
| So from now we can use printk
+-------------------------------------------------------------------*/
call _IBMPC_initVideo
#if USE_VBE_RM
call vesa_realmode_bootup_init
#endif
#endif
/*---------------------------------------------------------------------+
| Check CPU type. Enable Cache and init coprocessor if needed.
+---------------------------------------------------------------------*/
call checkCPUtypeSetCr0
#ifdef __SSE__
call SYM(enable_sse)
#endif
/*---------------------------------------------------------------------+
| Transfer control to User's Board Support Package
| Note: at the top we reserved space for the argument
| so that
| initial_esp = ( TOS - 4 ) & ~(CPU_STACK_ALIGNMENT-1)
| this ensures that
| 1) esp is now aligned
| 2) there is space for the cmdline pointer which we just
| may store at *(esp)
+---------------------------------------------------------------------*/
movl $SYM(_boot_multiboot_cmdline), (esp)
call SYM (boot_card)
cli # stops interrupts from being processed after hlt!
hlt # shutdown
#ifdef __SSE__
/*--------------------------------------------------------------------+
| Enable SSE; we really only care about fxsave/fxrstor and leave
| The only feature *we* (as an OS) use is fxsave/fxrstor.
| But as a courtesy we make sure we don't execute on hardware
| that doesn't support features possibly used by the compiler.
+---------------------------------------------------------------------*/
PUBLIC (enable_sse)
SYM(enable_sse):
movl SYM (x86_capability), eax
testl $0x01000000, eax
jne 1f
movl $SYM (no_fxsave_msg), 0(esp)
jmp SYM(_sse_panic)
1:
testl $0x02000000, eax
jne 1f
movl $SYM (no_sse_msg), 0(esp)
jmp SYM(_sse_panic)
1:
#ifdef __SSE2__
testl $0x04000000, eax
jne 1f
movl $SYM (no_sse2_msg), 0(esp)
jmp SYM(_sse_panic)
1:
#endif
#ifdef __SSE3__
movl SYM (x86_capability_x), eax
testl $1, eax
jne 1f
movl $SYM (no_sse3_msg), 0(esp)
jmp SYM(_sse_panic)
1:
#endif
mov cr4, eax # OK to enable now
or $0x600, eax
mov eax, cr4
ret
SYM(_sse_panic):
call SYM(printk)
1: hlt
jmp 1b
#endif
END_CODE
BEGIN_DATA
PUBLIC(_boot_multiboot_info_p)
SYM(_boot_multiboot_info_p):
.long 0
PUBLIC(_boot_multiboot_info)
PUBLIC(_boot_multiboot_flags)
PUBLIC(_boot_multiboot_memory)
PUBLIC(_boot_multiboot_cmdline)
SYM(_boot_multiboot_info):
SYM(_boot_multiboot_flags):
.long 0 /* flags */
SYM(_boot_multiboot_memory):
.long 0 /* mem_lower */
.long 0 /* mem_upper */
SYM(_boot_multiboot_cmdline):
.rept 256 /* cmd line */
.byte 0
.endr
PUBLIC(_stack_size)
SYM(_stack_size):
.long STACK_SIZE
#ifdef DEBUG_EARLY_START
PUBLIC (welcome_msg)
SYM (welcome_msg) :
.string "Ready to debug RTEMS ?\nEnter <CR>\n"
PUBLIC (hex_msg)
SYM (hex_msg) :
.string "0x%x\n"
PUBLIC (made_it_msg)
SYM (made_it_msg) :
.string "made it to %d\n"
#endif
#ifdef __SSE__
SYM (no_fxsave_msg) :
.string "PANIC: compiled for SSE but CPU seems to have no FXSAVE/FXRSTOR support (which I need)\n"
SYM (no_sse_msg) :
.string "PANIC: compiled for SSE but your CPU seems to have no SSE support\n"
#ifdef __SSE2__
SYM (no_sse2_msg) :
.string "PANIC: compiled for SSE2 but your CPU seems to have no SSE2 support\n"
#endif
#ifdef __SSE3__
SYM (no_sse3_msg) :
.string "PANIC: compiled for SSE3 but your CPU seems to have no SSE3 support\n"
#endif
#endif
END_DATA
END

254
c/src/lib/libbsp/i386/pc386/start/start16.S
View File

@@ -1,254 +0,0 @@
/*--------------------------------------------------------------------------+
* start16.s v1.0 - PC386 BSP - 1998/04/13
*--------------------------------------------------------------------------+
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing all initialization.
*--------------------------------------------------------------------------+
* (C) Copyright 1997 -
* - NavIST Group - Real-Time Distributed Systems and Industrial Automation
*
* http://pandora.ist.utl.pt
*
* Instituto Superior Tecnico * Lisboa * PORTUGAL
*--------------------------------------------------------------------------+
* Disclaimer:
*
* This file is provided "AS IS" without warranty of any kind, either
* expressed or implied.
*--------------------------------------------------------------------------+
*/
/*
* COPYRIGHT (c) 2011.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bspopts.h>
/*---------------------------------------------------------------------------+
| Constants
+----------------------------------------------------------------------------*/
#if defined(SMP_SECONDARY_CORE)
.set PROT_CODE_SEG, 0x08 # offset of code segment descriptor into GDT
#else
.set PROT_CODE_SEG, 0x0 # offset of code segment descriptor into GDT
#endif
.set PROT_DATA_SEG, 0x10 # offset of code segment descriptor into GDT
.set CR0_PE, 1 # protected mode flag on CR0 register
.set HDRSTART, HEADERADDR # address of start of bin2boot header
.set HDROFF, 0x24 # offset into bin2boot header of start32 addr
.set STACKOFF, 0x200-0x10 # offset to load into %esp, from start of image
/* #define NEW_GAS */
#ifdef NEW_GAS
#define LJMPL ljmpl
#else
#define LJMPL ljmp
#endif
/*----------------------------------------------------------------------------+
| CODE section
+----------------------------------------------------------------------------*/
.text
#if defined(SMP_SECONDARY_CORE)
.globl app_processor_start # entry point
app_processor_start:
#else
.globl _start16 # entry point
.globl start16
start16:
_start16:
#endif
.code16
cli # DISABLE INTERRUPTS!!!
#if defined(SMP_SECONDARY_CORE)
jmp 1f
.align 4
app_cpu_start:
.long 0
app_cpu_stack:
.long 0
1:
#endif
movw %cs, %ax # Initialize the rest of
movw %ax, %ds # segment registers
movw %ax, %es
movw %ax, %ss
#if !defined(SMP_SECONDARY_CODE) && (RTEMS_VIDEO_80x50 == 1)
movl $0x0040,%eax # use 32 bit constant to ensure 16 MSB=0
mov %ax,%es
movw %es:0x4a, %ax # get 16 bit number of columns
cmpw $0, %ax # or 0 if no video adapter
je 1f # if no video, skip touching it
/*---------------------------------------------------------------------+
| Switch VGA video to 80 lines x 50 columns mode. Has to be done before
| turning protected mode on since it uses BIOS int 10h (video) services.
+---------------------------------------------------------------------*/
movw $0x0003, %ax # forced set
int $0x10
movw $0x1112, %ax # use 8x8 font
xorb %bl, %bl
int $0x10
movw $0x1201, %ax # turn off cursor emulation
movb $0x34, %bl
int $0x10
movb $0x01, %ah # define cursor (scan lines 0 to 7)
movw $0x0007, %cx
int $0x10
1:
#endif /* !SMP_SECONDARY_CODE and RTEMS_VIDEO_80x50 */
/*---------------------------------------------------------------------+
| Bare PC machines boot in real mode! We have to turn protected mode on.
+---------------------------------------------------------------------*/
#if defined(SMP_SECONDARY_CORE)
lgdt gdtptr - app_processor_start # load Global Descriptor Table
#else
lgdt gdtptr - start16 # load Global Descriptor Table
#endif /* SMP_SECONDARY_CORE */
movl %cr0, %eax
orl $CR0_PE, %eax
movl %eax, %cr0 # turn on protected mode
#if defined(SMP_SECONDARY_CORE)
LJMPL $PROT_CODE_SEG, $2f # flush prefetch queue, and reload %cs
#else
LJMPL $PROT_CODE_SEG, $2f # flush prefetch queue, and reload %cs
#endif
.code32
2:
/*---------------------------------------------------------------------+
| load the other segment registers
+---------------------------------------------------------------------*/
movl $PROT_DATA_SEG, %eax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
#if defined(SMP_SECONDARY_CORE)
movl app_cpu_stack, %esp # stack pointer
movl app_cpu_stack, %ebp # base pointer
#else
movl $start16 + STACKOFF, %esp # set up stack pointer
addl $start16 + STACKOFF, %ebp # set up stack pointer
#endif /* SMP_SECONDARY_CORE */
/*---------------------------------------------------------------------+
| we have to enable A20 in order to access memory above 1MByte
+---------------------------------------------------------------------*/
call empty_8042
movb $0xD1, %al # command write
outb %al, $0x64
call empty_8042
movb $0xDF, %al # A20 on
outb %al, $0x60
call empty_8042
call pc386_delay
call pc386_delay
call pc386_delay
#if defined(SMP_SECONDARY_CORE)
movl app_cpu_start, %eax # jump to app CPU start
#else
movl %cs:HDRSTART + HDROFF, %eax # jump to start of 32 bit code
#endif /* SMP_SECONDARY_CORE */
pushl %eax
ret
/*----------------------------------------------------------------------------+
| pc386_delay
+------------------------------------------------------------------------------
| Delay is needed after doing I/O.
|
| The outb version is OK on most machines BUT the loop version ...
|
| will delay for 1us on 1Gz machine, it will take a little bit
| longer on slower machines, however, it does not matter because we
| are going to call this function only a few times
!
| NOTE: Saving the content of the EAX register just in case. - Rosimildo.
+----------------------------------------------------------------------------*/
.p2align 4
.globl _pc386_delay
.globl pc386_delay
pc386_delay:
_pc386_delay:
pushl %eax
#if defined(USE_OUTB_FOR_DELAY)
outb %al, $0x80 # about 1uS delay on most machines
#else
movl $0x200, %eax
pc386_delay1:
dec %eax
jnz pc386_delay1
#endif
popl %eax
ret
/*----------------------------------------------------------------------------+
| empty_8042
+------------------------------------------------------------------------------
| This routine checks that the keyboard command queue is empty (after emptying
| the output buffers).
| No timeout is used - if this hangs there is something wrong with the machine,
| and we probably couldn't proceed anyway.
+----------------------------------------------------------------------------*/
.p2align 4
.globl _empty_8042
.globl empty_8042
empty_8042:
_empty_8042:
call pc386_delay
inb $0x64, %al # 8042 status port
testb $0x01, %al # output buffer?
jz no_output
call pc386_delay
in $0x60, %al # read it
jmp empty_8042
no_output:
test $0x02, %al # is input buffer full?
jnz empty_8042 # yes - loop
ret
/*----------------------------------------------------------------------------+
| DATA section
+----------------------------------------------------------------------------*/
/**************************
* GLOBAL DESCRIPTOR TABLE *
**************************/
.p2align 4
gdtptr:
/* we use the NULL descriptor to store the GDT pointer - a trick quite
nifty due to: Robert Collins (rcollins@x86.org) */
.word gdtlen - 1
.long gdtptr
.word 0x0000
/* code segment */
.word 0xffff, 0
.byte 0, 0x9f, 0xcf, 0
/* data segment */
.word 0xffff, 0
.byte 0, 0x93, 0xcf, 0
.set gdtlen, . - gdtptr # length of GDT

2
c/src/lib/libbsp/lm32/lm32_evr/Makefile.am
View File

@@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/lm32/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/lm32/milkymist/Makefile.am
View File

@@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/lm32/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

160
c/src/lib/libbsp/lm32/shared/start/start.S
View File

@@ -1,160 +0,0 @@
/* LM32 startup code
*
* This is the entry point on reset and when loading the
* executive from a bootloader.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
* Micro-Research Finland Oy
*/
#include "bspopts.h"
.section .boot,"a",@progbits
.align 4
.globl start
.type start,@function
.globl _start
.type _start,@function
.globl __start
.type __start,@function
.globl LatticeDDInit
.type LatticeDDInit,@function
.globl crt0
.type crt0,@function
LatticeDDInit:
__start:
_start:
start:
/* Clear r0 */
xor r0,r0,r0
/* Disable interrupts */
wcsr IE, r0
/* Mask all interrupts */
wcsr IM,r0
/* Set exception base address */
mvhi r1, hi(start)
ori r1, r1, lo(start)
wcsr EBA, r1
bi crt0
nop
/*
* Unused handlers call debug handlers
*/
breakpoint_handler:
rcsr r7, DEBA
addi r7, r7, 32
b r7
nop
nop
nop
nop
nop
instruction_bus_error_handler:
rcsr r7, DEBA
addi r7, r7, 64
b r7
nop
nop
nop
nop
nop
watchpoint_handler:
rcsr r7, DEBA
addi r7, r7, 96
b r7
nop
nop
nop
nop
nop
data_bus_error_handler:
rcsr r7, DEBA
addi r7, r7, 128
b r7
nop
nop
nop
nop
nop
divide_by_zero_handler:
rcsr r7, DEBA
addi r7, r7, 160
b r7
nop
nop
nop
nop
nop
interrupt_handler:
.extern _ISR_Handler
mvhi r0, hi(_ISR_Handler)
ori r0, r0, lo(_ISR_Handler)
b r0
nop
nop
nop
nop
nop
system_call_handler:
rcsr r7, DEBA
addi r7, r7, 224
b r7
nop
nop
nop
nop
nop
crt0:
/* Flush data cache */
addi r1, r0, 1
wcsr DCC, r1
nop
nop
nop
nop
/* Flush Instruction Cache */
wcsr ICC, r1
nop
nop
nop
nop
/* Initialize stack pointer */
mvhi sp, hi(_fstack-4)
ori sp, sp, lo(_fstack-4)
/* Initialize global pointer */
mvhi gp, hi(_edata)
ori gp, gp, lo(_edata)
/* Clear bss */
mvhi r1, hi(_clear_start)
ori r1, r1, lo(_clear_start)
mvhi r3, hi(_clear_end)
ori r3, r3, lo(_clear_end)
.clear_bss:
be r1, r3, .end_clear_bss
sw (r1+0), r0
addi r1, r1, 4
bi .clear_bss
.end_clear_bss:
mvi r1, 0
be r4, r0, .no_rescue
mvhi r1, hi(.rescue_str)
ori r1, r1, lo(.rescue_str)
.no_rescue:
mvhi r7, hi(boot_card)
ori r7, r7, lo(boot_card)
call r7
# boot_card returns when RTEMS is shutdown
.dead_end:
bi .dead_end
.section .rodata
.rescue_str:
.ascii "rescue"

2
c/src/lib/libbsp/m32c/m32cbsp/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m32c/m32cbsp/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

183
c/src/lib/libbsp/m32c/m32cbsp/start/start.S
View File

@@ -1,183 +0,0 @@
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
#define A16
#define A(n,w) n
#define W w
#define ALIGN 1
#else
#define A24
#define A(n,w) w
#define W l
#define ALIGN 2
#endif
.text
.global _start
_start:
.LFB2:
fset U /* User stack */
ldc #__stack,sp
#ifdef A16
mov.b #%hi8(__romdatastart),r1h
mov.w #%lo16(__romdatastart),a0
mov.w #__datastart,a1
#else
mov.l #__romdatastart,a0
mov.l #__datastart,a1
#endif
mov.w #__romdatacopysize,r3
shl.w #-1,r3
smovf.w
#ifdef A16
mov.w #__bssstart,a1
#else
mov.l #__bssstart,a1
#endif
mov.w #__bsssize,r3
shl.w #-1,r3
mov.w #0,r0
sstr.w
/* jsr.a __m32c_init */
jsr.a _boot_card
.LFE2:
#ifdef A24
/* rv in r0, ok for arg0 */
#else
mov.w r0,r1
#endif
.global _bsp_reset
_bsp_reset:
jsr.a _sys_exit
.text
.global _m32c_run_preinit_array
.type _m32c_run_preinit_array,@function
_m32c_run_preinit_array:
mov.W #__preinit_array_start,a0
mov.W #__preinit_array_end,a1
jmp.w _m32c_run_inilist
.global _m32c_run_init_array
.type _m32c_run_init_array,@function
_m32c_run_init_array:
mov.W #__init_array_start,a0
mov.W #__init_array_end,a1
jmp.w _m32c_run_inilist
.global _m32c_run_fini_array
.type _m32c_run_fini_array,@function
_m32c_run_fini_array:
mov.W #__fini_array_start,a0
mov.W #__fini_array_end,a1
/* fall through */
_m32c_run_inilist:
next_inilist:
cmp.W a0,a1
jeq done_inilist
pushm a0,a1
mov.W [a0],a0
#ifdef A16
mov.b:s #0,a1 /* zero extends */
jsri.a a1a0
#else
jsri.a a0
#endif
popm a0,a1
add.W A(#2,#4),a0
jmp.b next_inilist
done_inilist:
rts
.section .init,"ax",@progbits
.global __init
.global __m32c_init
__init:
__m32c_init:
enter #0
exitd
.section .fini,"ax",@progbits
.global __fini
.global __m32c_fini
__fini:
__m32c_fini:
enter #0
jsr.a _m32c_run_fini_array
exitd
;;; Provide Dwarf unwinding information that will help GDB stop
;;; backtraces at the right place. This is stolen from assembly
;;; code generated by GCC with -dA.
.section .debug_frame,"",@progbits
.Lframe0:
.4byte .LECIE0-.LSCIE0 ; Length of Common Information Entry
.LSCIE0:
.4byte 0xffffffff ; CIE Identifier Tag
.byte 0x1 ; CIE Version
.ascii "\0" ; CIE Augmentation
.uleb128 0x1 ; CIE Code Alignment Factor
.sleb128 -1 ; CIE Data Alignment Factor
.byte 0xd ; CIE RA Column
.byte 0xc ; DW_CFA_def_cfa
.uleb128 0xc
.uleb128 0x3
.byte 0x8d ; DW_CFA_offset, column 0xd
.uleb128 0x3
.p2align ALIGN
.LECIE0:
.LSFDE0:
.4byte .LEFDE0-.LASFDE0 ; FDE Length
.LASFDE0:
.4byte .Lframe0 ; FDE CIE offset
.4byte .LFB2 ; FDE initial location
.4byte .LFE2-.LFB2 ; FDE address range
.byte 0xf ; DW_CFA_def_cfa_expression
.uleb128 1 ; length of expression
.byte 0x30 ; DW_OP_lit0
.p2align ALIGN
.LEFDE0:
.text

2
c/src/lib/libbsp/m68k/av5282/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/av5282/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

393
c/src/lib/libbsp/m68k/av5282/start/start.S
View File

@@ -1,393 +0,0 @@
/*
* uC5282 startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <rtems/asm.h>
#define SRAM_SIZE (64*1024)
#define DEFAULT_IPSBAR 0x40000000
BEGIN_CODE
#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4
PUBLIC (INTERRUPT_VECTOR)
SYM(INTERRUPT_VECTOR):
.long INITIAL_STACK | 0: Initial 'SSP'
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_spuriousInterrupt) | 64: User spurious handler
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
.long SYM(_uhoh) | 162:
.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
.long SYM(_uhoh) | 189:
.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
.long SYM(_uhoh) | 192:
.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
.long SYM(_uhoh) | 198:
.long SYM(_uhoh) | 199:
.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
.long SYM(_uhoh) | 203:
.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
.align 4
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/***************************************************************************
Function : start
Description : setup the internal SRAM for use and setup the INITIAL STACK ptr.
Also enable the internal peripherals
***************************************************************************/
.align 4
PUBLIC (start)
SYM(start):
move.w #0x0000,d0 | Turn off watchdog timer
move.w d0, (0x40140000)
move.w #0x2000,d0 | Set system frequency to 58960000
move.w d0, (0x40120000)
move.w #0x2700,sr | Disable interrupts
move.l #__SRAMBASE+1,d0 | Enable the MCF5282 internal SRAM
movec d0,%rambar | ...so we have a stack
move.l #(INITIAL_STACK),sp | Overwrite the fake stack pointer
/*
* If we're being started by the debugger, and the debugger has
* moved the IPSBAR, we're doomed........
*/
move.l #__IPSBAR+1,d0 | Enable the MCF5282 internal peripherals
move.l d0,DEFAULT_IPSBAR
/*
* Remainder of the startup code is handled by C code
*/
jmp SYM(Init5282) | Start C code (which never returns)
/***************************************************************************
Function : CopyDataClearBSSAndStart
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
start C program. Assume that DATA and BSS sizes are multiples of 4.
***************************************************************************/
.align 4
PUBLIC (CopyDataClearBSSAndStart)
SYM(CopyDataClearBSSAndStart):
lea SYM(_data_dest_start),a0 | Get start of DATA in RAM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NODATACOPY | Yes, no copy necessary
lea SYM(_data_dest_end),a1 | Get end of DATA in RAM
bra.s DATACOPYLOOPTEST | Branch into copy loop
DATACOPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
DATACOPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s DATACOPYLOOP | No, skip
NODATACOPY:
/* Now, clear BSS */
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
/*
* Right : Now we're ready to boot RTEMS
*/
clrl d0 | Pass in null to all boot_card() params
movel d0,a7@- | command line
jsr SYM(boot_card) | Call C boot_card function to startup RTEMS
movel a7@+,d0
MULTI_TASK_EXIT:
nop
nop
trap #14
bra MULTI_TASK_EXIT
END_CODE
.align 2
BEGIN_DATA_DCL
.align 2
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END

2
c/src/lib/libbsp/m68k/csb360/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/csb360/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

413
c/src/lib/libbsp/m68k/csb360/start/start.S
View File

@@ -1,413 +0,0 @@
/*
* CSB360 startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*/
/*
* Copyright (C) 2004 Cogent Computer Systems
* Author: Jay Monkman <jtm@lopingdog.com>
*
* Based on start.S from mcf520elite BSP:
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* Based on work:
* David Fiddes, D.J@fiddes.surfaid.org
* http://www.calm.hw.ac.uk/davidf/coldfire/
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
#include <bsp.h>
BEGIN_CODE
/* Initial stack situated in on-chip static memory */
#define INITIAL_STACK BSP_MEM_ADDR_SRAM+BSP_MEM_SIZE_SRAM-4
PUBLIC (INTERRUPT_VECTOR)
SYM(INTERRUPT_VECTOR):
.long INITIAL_STACK | 00: initial SSP
.long start | 01: Initial PC
.long _unexp_exception | 02: Access Error
.long _unexp_exception | 03: Address Error
.long _unexp_exception | 04: Illegal Instruction
.long _reserved_int | 05: Reserved
.long _reserved_int | 06: Reserved
.long _reserved_int | 07: Reserved
.long _unexp_exception | 08: Priveledge Violation
.long _unexp_exception | 09: Trace
.long _unexp_exception | 0A: Unimplemented A-Line
.long _unexp_exception | 0B: Unimplemented F-Line
.long _unexp_exception | 0C: Debug interrupt
.long _reserved_int | 0D: Reserved
.long _unexp_exception | 0E: Format error
.long _unexp_exception | 0F: Uninitialized interrupt
.long _reserved_int | 10: Reserved
.long _reserved_int | 11: Reserved
.long _reserved_int | 12: Reserved
.long _reserved_int | 13: Reserved
.long _reserved_int | 14: Reserved
.long _reserved_int | 15: Reserved
.long _reserved_int | 16: Reserved
.long _reserved_int | 17: Reserved
.long _spurious_int | 18: Spurious interrupt
.long _avec1_int | 19: Autovector Level 1
.long _avec2_int | 1A: Autovector Level 2
.long _avec3_int | 1B: Autovector Level 3
.long _avec4_int | 1C: Autovector Level 4
.long _avec5_int | 1D: Autovector Level 5
.long _avec6_int | 1E: Autovector Level 6
.long _avec7_int | 1F: Autovector Level 7
.long _unexp_exception | 20: TRAP #0
.long _unexp_exception | 21: TRAP #1
.long _unexp_exception | 22: TRAP #2
.long _unexp_exception | 23: TRAP #3
.long _unexp_exception | 24: TRAP #4
.long _unexp_exception | 25: TRAP #5
.long _unexp_exception | 26: TRAP #6
.long _unexp_exception | 27: TRAP #7
.long _unexp_exception | 28: TRAP #8
.long _unexp_exception | 29: TRAP #9
.long _unexp_exception | 2A: TRAP #10
.long _unexp_exception | 2B: TRAP #11
.long _unexp_exception | 2C: TRAP #12
.long _unexp_exception | 2D: TRAP #13
.long _unexp_exception | 2E: TRAP #14
.long _unexp_exception | 2F: TRAP #15
.long _reserved_int | 30: Reserved
.long _reserved_int | 31: Reserved
.long _reserved_int | 32: Reserved
.long _reserved_int | 33: Reserved
.long _reserved_int | 34: Reserved
.long _reserved_int | 35: Reserved
.long _reserved_int | 36: Reserved
.long _reserved_int | 37: Reserved
.long _reserved_int | 38: Reserved
.long _reserved_int | 39: Reserved
.long _reserved_int | 3A: Reserved
.long _reserved_int | 3B: Reserved
.long _reserved_int | 3C: Reserved
.long _reserved_int | 3D: Reserved
.long _reserved_int | 3E: Reserved
.long _reserved_int | 3F: Reserved
.long _unexp_int | 40-FF: User defined interrupts
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 50:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 60:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 70:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 80:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 90:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | A0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | B0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | C0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | D0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | E0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | F0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
PUBLIC(start)
SYM(start):
move.w #0x2700,sr | First turn off all interrupts!
move.l #(BSP_RAMBAR + MCF5272_RAMBAR_V), d0
movec d0,rambar0 | ...so we have a stack
move.l #(INITIAL_STACK),sp | Set up stack again (may be we are
| going here from monitor or with
| BDM interface assistance)
/*
* Remainder of the startup code is handled by C code
*/
jmp SYM(init5272) | Start C code (which never returns)
/***************************************************************************
Function : clear_bss
Description : clear BSS segment
***************************************************************************/
PUBLIC (clear_bss)
SYM(clear_bss):
lea clear_start,a0 | Get start of BSS
lea clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
rts
PUBLIC (start_csb360)
SYM(start_csb360):
/*
* Right : Now we're ready to boot RTEMS
*/
clrl d0 | Pass in null to all boot_card() params
movel d0,a7@- | command line
jsr SYM(boot_card) | Call C boot_card function to startup RTEMS
# Wait forever
_stop:
nop
stop #0x2700
jmp _stop
# The following labelled nops is a placeholders for breakpoints
_unexp_exception:
nop
jmp _stop
_unexp_int:
nop
jmp _stop
_reserved_int:
nop
jmp _stop
_spurious_int:
nop
jmp _stop
_avec1_int:
nop
jmp _unexp_int
_avec2_int:
nop
jmp _unexp_int
_avec3_int:
nop
jmp _unexp_int
_avec4_int:
nop
jmp _unexp_int
_avec5_int:
nop
jmp _unexp_int
_avec6_int:
nop
jmp _unexp_int
_avec7_int:
nop
jmp _unexp_int
END_CODE
END

2
c/src/lib/libbsp/m68k/gen68340/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/gen68340/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

877
c/src/lib/libbsp/m68k/gen68340/start/start.S
View File

@@ -1,877 +0,0 @@
/*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*/
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Based on the `gen68360' board support package, and covered by the
* original distribution terms.
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*/
#include <rtems/asm.h>
#include <m68349.inc>
#include <bsp.h> /* to indicate dependencies */
/* old addresses for AST68340 only, undefine for AST68349 */
#define _OLD_ASTECC 1
BEGIN_CODE
/*
* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
*/
Entry:
.long SYM(m340)+1024 | 0: Initial SSP
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_uhoh) | 64: User defined vectors (192)
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
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.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
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.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
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.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
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.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
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.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
PUBLIC (_uhoh)
SYM(_uhoh): nop | Leave spot for breakpoint
/* stop #0x2700 | Stop with interrupts disabled */
move.w #0x2700,sr
move.w (a7),_boot_panic_registers+4 | SR
move.l 2(a7),_boot_panic_registers | PC
move.w 6(a7),_boot_panic_registers+6 | format & vector
movem.l d0-d7/a0-a7, _boot_panic_registers+8
movec sfc, d0
movem.l d0, _boot_panic_registers+72
movec dfc, d0
movem.l d0, _boot_panic_registers+76
movec vbr, d0
movem.l d0, _boot_panic_registers+80
jmp SYM(_dbug_dumpanic)
bra.s _crt0_cold_start
/*
* Log, but otherwise ignore, spurious interrupts
*/
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/*
* Place the low-order 3 octets of the board's ethernet address at
* a `well-known' fixed location relative to the startup location.
*/
.align 2
.word 0 | Padding
ethernet_address_buffer:
.word 0x08F3 | Default address
.word 0xDEAD
.word 0xCAFE
BEGIN_DATA
/* equates */
.equ _CPU340, 0x0
.equ _CPU349, 0x31
#ifdef _OLD_ASTECC /* old addresses for AST68340 only */
.equ _EPLD_CS_BASE, 0x1
.equ _PROM_Start, 0x01000000 /* CS0 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x0c000000 /* CS3 */
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
.equ _ExtRam_Start, 0x10000000 /* SRAM */
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
#else /* new addresses for AST68349 and 68340 */
.equ _EPLD_CS_BASE, 0x5
.equ _PROM_Start, 0x50000000 /* CS0 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x0c000000 /* CS3 */
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
.equ _ExtRam_Start, 0x80000000 /* DRAM */
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
#endif
.equ _SPEED349, 0xD680 /* 24 Mhz */
.equ _SPEED340, 0xD700 /* 25 Mhz */
/* .equ _SPEED340, 0xCE00 16 Mhz */
#define crt0_boot_type d0 /* cold/warm start (must be D0) */
#define crt0_temp d1
#define crt0_cpu_type d2
#define crt0_csswitch d3
#define crt0_buswidth d4
#define crt0_pdcs d5
#define crt0_spare6 d6
#define crt0_spare7 d7
#define crt0_sim_base a0
#define crt0_glue a1
#define crt0_dram a2
#define crt0_ptr3 a3
#define crt0_ptr4 a4
#define crt0_ptr5 a5
#define crt0_ptr6 a6
/* -- PDCS buffer equates -- */
.equ pdcs_mask, 0x1F /* DRAM configuration */
.equ pdcs_sw12, 7 /* switch 12 */
.equ pdcs_sw11, 6 /* switch 11 */
.equ pdcs_sw14, 5 /* switch 14 */
.equ bit_cache, pdcs_sw12 /* enable cache if on */
.equ bit_meminit, pdcs_sw11 /* init memory if on */
/* -- Initialization stack and vars -- */
/* When using DWARF, everything must be a multiple of 16-bits. */
#if 1
_AsteccBusWidth: ds.w 0x0101
_AsteccCsSwitch: ds.w 0x0101
#else
_AsteccBusWidth: ds.b 1
_AsteccCsSwitch: ds.b 1
#endif
_AsteccCpuName: ds.l 1
.align 4
_crt0_init_stack:
ds.l 500
_crt0_init_stktop:
/* -- Initialization code -- */
BEGIN_CODE
.align 4
dc.l _crt0_init_stktop /* reset SP */
dc.l _crt0_cold_start /* reset PC */
dc.l _crt0_warm_start
/* When using DWARF, everything must be a multiple of 16-bits. */
.ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards "
.text
dc.w 0
.align 4
.globl start
start:
_crt0_cold_start:
moveq.l #0,crt0_boot_type | signal cold reset
bra.s _crt0_common_start
_crt0_warm_start:
moveq.l #1,crt0_boot_type | signal warm reset
_crt0_common_start:
move.w #0x2700,sr | disable interrupts and switch to interrupt mode
movea.l #_crt0_init_stktop,sp | set up initialization stack
move.l #Entry,crt0_temp | VBR initialization
movec.l crt0_temp,vbr |
moveq.l #0x07,crt0_temp
movec.l crt0_temp,dfc | prepare access in CPU space
move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES
moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795)
movea.l #BASE_SIM,crt0_sim_base
/* -- disable Bus Monitor -- */
move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register
/* -- enable A31-A24 -- */
clr.b SIM_PPRA1(crt0_sim_base)
/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
move.w #0x427F,SIM_MCR(crt0_sim_base)
/* -- enable /IRQ3, 5, 6, 7 -- */
move.b #0xE8,SIM_PPRB(crt0_sim_base)
/* -- enable autovector on /IRQ7 -- */
move.b #0x80,SIM_AVR(crt0_sim_base)
/* -- test CPU type -- */
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne cpu_is_68340
/*-------------------------------------------------------------------------------------------*/
cpu_is_68349:
/* -- set cpu clock -- */
move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock
sync_wait349:
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
beq sync_wait349
/* to allow access to the EPLD internal registers, it is necessary
to disable the global chip-select /CS0 (which decodes every external
cycles). To do that, we initialize the 68349 internal RAM,
copy a part of the initialization code in it, and jump there.
from that moment, /CS0 is not used, therefore it can be initialized
with its default value. Its width may be incorrect, but it will be
adjusted later. The goal is to avoid any conflict with
the accesses to the EPLD registers.
When this is done, we read the RESET parameters (boot prom width
and chip-select switch) and proceed with the initialization
when all is done, we jump back to the boot prom now
decoded with a properly configured /CS0 */
/*-------------------------------------*/
/* -- configure internal SRAM banks -- */
move.l #0x00000000,QDMM_MCR(crt0_sim_base)
move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)
/*--------------------------------------------------------*/
/* -- copy to address of the 68349 initialization code -- */
lea.l _copy_start_code(%pc),crt0_ptr3
lea.l _copy_end_code(%pc),crt0_ptr4
move.l crt0_ptr4,crt0_temp
sub.l crt0_ptr3,crt0_temp
add.l #3,crt0_temp | adjust to next long word
lsr.l #2,crt0_temp
move.l #_FastRam_Start,crt0_ptr4
_copy_loop:
move.l (crt0_ptr3)+,(crt0_ptr4)+
subq.l #1,crt0_temp
bne.s _copy_loop
bra.l _FastRam_Start | jump to code in internal RAM
/*------------------------------------*/
/* -- start of initialization code -- */
_copy_start_code:
bra.l _begin_68349_init
/*----------------------------------------------------------*/
/* Astecc 68349 board : chip-select initialization values */
_table_csepld:
/* When using DWARF, everything must be a multiple of 16-bits. */
#if 1
dc.w (((_EPLD_CS_BASE&0x0F)+0x80) << 8) | 0x80 | 16 bits, 0ws
dc.w 0x9090 | 16 bits, ext /dsack
#else
dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws
dc.b 0x80 | 16 bits, 0 ws
dc.b 0x90 | 16 bits, ext /dsack
dc.b 0x90 | 16 bits, ext /dsack
#endif
_table_cs349:
dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS)
dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0
dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS)
dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1
dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes)
dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2
dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes)
dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3
/*-------------------------------------------------*/
_begin_68349_init:
/*-------------------------------------------------*/
/* 68349 chip select initialization
at this stage, the width of /CS0 may be incorrect
it will be corrected later
*/
_cs68349_init:
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
moveq.l #0x07,crt0_temp
_cs349_init2:
move.l (crt0_ptr3)+,(crt0_ptr4)+
dbra crt0_temp,_cs349_init2
/*-----------------------------------------------*/
/* -- prepare access to the internal registers --*/
moveq.l #EPLD_SPACE,crt0_temp
movec.l crt0_temp,dfc
movec.l crt0_temp,sfc
move.l #GLUE_EPLD,crt0_glue
move.l #DRAM_EPLD,crt0_dram
/*-------------------------------------------*/
/* EPLD generated /CS[3..0] must be disabled */
_csepld_clear:
move.l crt0_glue,crt0_ptr4
move.w #3,crt0_spare6
clr.b crt0_temp
_csepld_clear1:
moves.b crt0_temp,(crt0_ptr4)+
dbra crt0_spare6,_csepld_clear1
/*---------------------------------------------------------*/
/* -- get width of boot PROM, and active chip-select set --*/
moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch
move.b crt0_csswitch,crt0_buswidth
/* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
: sel == 1 => EPLD chip_selects (/CS[3..0]) */
and.b #1,crt0_csswitch
/* bus width of /CS0 during reset bw[1..0] : 0 1 2 3
bus width : 32 16 8 ext./dsackx */
rol.b #2,crt0_buswidth
and.b #3,crt0_buswidth
/*----------------------------------------------------*/
/* -- configure chip select 0 with boot prom width -- */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
move.l (crt0_ptr3)+,crt0_temp
and.b #0xFC,crt0_temp | clear PS0 & PS1
or.b crt0_buswidth,crt0_temp | set boot PROM bus width
move.l crt0_temp,(crt0_ptr4)+
/*------------------------*/
/* -- read PDCS buffer -- */
moves.b REG_PDCS(crt0_glue),crt0_pdcs
/* move.b #0x3F,crt0_pdcs pour test */
/*---------------------------------------*/
/* -- EPLD chip-select initialization -- */
/*---------------------------------------*/
btst.b #0,crt0_csswitch
beq _cs_init_end
/*--------------------------------------------*/
/* 68349 generated /CS[3..0] must be disabled */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
moveq.l #0x03,crt0_temp
_cs349_clear:
move.l (crt0_ptr3)+,(crt0_ptr4)+
move.l (crt0_ptr3)+,crt0_spare6
and.b #0xFE,crt0_spare6 | disable chip-select
move.l crt0_spare6,(crt0_ptr4)+
dbra crt0_temp,_cs349_clear
/*---------------------------------------------*/
/* EPLD generated /CS[3..0] must be configured */
_csepld_init:
move.l crt0_glue,crt0_ptr4
lea.l _table_csepld(%pc),crt0_ptr3
move.b (crt0_ptr3)+,crt0_temp
or.b #0x20,crt0_temp | default width is 32 bits
tst.b crt0_buswidth | is boot PROM bus width 32 bits ?
beq _csepld1 | if not
and.b #0xDF,crt0_temp | set width to 16 bits
_csepld1:
moves.b crt0_temp,(crt0_ptr4)+
moveq.l #0x02,crt0_spare6
_csepld2:
move.b (crt0_ptr3)+,crt0_temp
moves.b crt0_temp,(crt0_ptr4)+
dbra crt0_spare6,_csepld2
_cs_init_end:
/*--------------------------------------*/
/* -- DRAM controller initialization -- */
_dram_init:
move.w #15,crt0_temp
move.l #_ExtRam_Start,crt0_ptr3
_dram_init1:
clr.l (crt0_ptr3)+ | must access DRAM
dbra crt0_temp,_dram_init1 | prior to init refresh
_dram_init2:
move.b #3,crt0_temp
moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states
move.b #0x81,crt0_temp
moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs
move.b #0,crt0_temp
moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes
/*-----------------------*/
/* -- configure cache -- */
_init_cache:
move.l #0x000001E0,CACHE_MCR(crt0_sim_base)
btst.b #bit_cache,crt0_pdcs
bne _init_cache_end
or.l #0x00000001,CACHE_MCR(crt0_sim_base)
_init_cache_end:
/*-----------------------------*/
/* -- timers initialization -- */
clr.b crt0_temp
moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1
moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2
/*--------------------------*/
/* -- I2C initialization -- */
move.b #3,crt0_temp
moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports
/*-----------------------------------------*/
/* -- baudrate generator initialization -- */
move.b #2,crt0_temp
moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400
/*-------------------------------*/
/* -- IO port initialization -- */
clr.b crt0_temp
moves.b crt0_temp,REG_IO(crt0_glue) | set port as input
/* -- */
move.l #68349,crt0_cpu_type
/* -- jump back to PROM -- */
jmp.l (_fill_test) | must be absolute long
_copy_end_code:
/*-------------------------------------------------
initialization code for the 68340 board
-------------------------------------------------*/
/* Astecc 68340 board : chip-select initialization values */
_table_cs340:
dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */
dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */
dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */
dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */
cpu_is_68340:
/* -- set cpu clock -- */
move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock
sync_wait340:
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
beq sync_wait340
/* -- chip select initialization -- */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs340(%pc),crt0_ptr3
moveq.l #0x07,crt0_temp
_b_cs340:
move.l (crt0_ptr3)+,crt0_ptr5
move.l crt0_ptr5,(crt0_ptr4)+ | pour test
dbra crt0_temp,_b_cs340
move.l #68340,crt0_cpu_type
move.b #0,crt0_csswitch | CPU
move.b #1,crt0_buswidth | 16 bits
/*-------------------------------------------------
fill RAM if COLDSTART
-------------------------------------------------*/
_fill_test:
tst.l crt0_boot_type
bne _dont_fill
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne _fill
btst.b #bit_meminit,crt0_pdcs
bne _dont_fill
/* fill main memory */
_fill:
move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars
move.l #_ExtRam_Start,crt0_temp
sub.l #_crt0_init_stack,crt0_temp
add.l #_ExtRam_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_fill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _fill_loop
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne _fill_bccram
/* fill QDMM memory */
movea.l #_FastRam_Start,crt0_ptr3 | get start
move.l #_FastRam_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_QDMMfill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _QDMMfill_loop
bra _dont_fill
/* fill BCC memory */
_fill_bccram:
movea.l #_BCCram_Start,crt0_ptr3 | get start
move.l #_BCCram_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_BCCfill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _BCCfill_loop
/*-------------------------------------------------*/
_dont_fill:
move.b crt0_csswitch,_AsteccCsSwitch
move.b crt0_buswidth,_AsteccBusWidth
move.l crt0_cpu_type,_AsteccCpuName
jmp SYM(_Init68340) | Start C code (which never returns)
/*
* Copy DATA segment, clear BSS segment, set up real stack,
* initialize heap, start C program.
* Assume that DATA and BSS sizes are multiples of 4.
*/
PUBLIC (_CopyDataClearBSSAndStart)
SYM(_CopyDataClearBSSAndStart):
lea SYM(_copy_start),a0 | Get start of DATA in RAM
lea SYM(_etext),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea SYM(_copy_end),a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
movel #_stack_init,a7 | set master stack pointer
movel d0,a7@- | command line
jsr SYM(boot_card) | Call C main
PUBLIC (_mainDone)
SYM(_mainDone):
nop | Leave spot for breakpoint
movew #1,a7 | Force a double bus error
movel d0,a7@- | This should cause a RESET
/* stop #0x2700 | Stop with interrupts disabled */
move.w #0x2700,sr
bra.l SYM(_mainDone) | Stuck forever
.align 2
BEGIN_DATA_DCL
.align 2
PUBLIC (environ)
SYM (environ):
.long 0
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END

2
c/src/lib/libbsp/m68k/gen68360/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/gen68360/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

418
c/src/lib/libbsp/m68k/gen68360/start/start.S
View File

@@ -1,418 +0,0 @@
/*
*
* This file contains the entry point for the application.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Based on the `gen68302' board support package, and covered by the
* original distribution terms.
*
* W. Eric Norum
* Saskatchewan Accelerator Laboratory
* University of Saskatchewan
* Saskatoon, Saskatchewan, CANADA
* eric@skatter.usask.ca
*/
#include <rtems/asm.h>
BEGIN_CODE
/*
* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
*/
Entry:
.long m360+1024 | 0: Initial SSP
.long start | 1: Initial PC
.long _uhoh | 2: Bus error
.long _uhoh | 3: Address error
.long _uhoh | 4: Illegal instruction
.long _uhoh | 5: Zero division
.long _uhoh | 6: CHK, CHK2 instruction
.long _uhoh | 7: TRAPcc, TRAPV instructions
.long _uhoh | 8: Privilege violation
.long _uhoh | 9: Trace
.long _uhoh | 10: Line 1010 emulator
.long _uhoh | 11: Line 1111 emulator
.long _uhoh | 12: Hardware breakpoint
.long _uhoh | 13: Reserved for coprocessor violation
.long _uhoh | 14: Format error
.long _uhoh | 15: Uninitialized interrupt
.long _uhoh | 16: Unassigned, reserved
.long _uhoh | 17:
.long _uhoh | 18:
.long _uhoh | 19:
.long _uhoh | 20:
.long _uhoh | 21:
.long _uhoh | 22:
.long _uhoh | 23:
.long _spuriousInterrupt | 24: Spurious interrupt
.long _uhoh | 25: Level 1 interrupt autovector
.long _uhoh | 26: Level 2 interrupt autovector
.long _uhoh | 27: Level 3 interrupt autovector
.long _uhoh | 28: Level 4 interrupt autovector
.long _uhoh | 29: Level 5 interrupt autovector
.long _uhoh | 30: Level 6 interrupt autovector
.long _uhoh | 31: Level 7 interrupt autovector
.long _uhoh | 32: Trap instruction (0-15)
.long _uhoh | 33:
.long _uhoh | 34:
.long _uhoh | 35:
.long _uhoh | 36:
.long _uhoh | 37:
.long _uhoh | 38:
.long _uhoh | 39:
.long _uhoh | 40:
.long _uhoh | 41:
.long _uhoh | 42:
.long _uhoh | 43:
.long _uhoh | 44:
.long _uhoh | 45:
.long _uhoh | 46:
.long _uhoh | 47:
.long _uhoh | 48: Reserved for coprocessor
.long _uhoh | 49:
.long _uhoh | 50:
.long _uhoh | 51:
.long _uhoh | 52:
.long _uhoh | 53:
.long _uhoh | 54:
.long _uhoh | 55:
.long _uhoh | 56:
.long _uhoh | 57:
.long _uhoh | 58:
.long _uhoh | 59: Unassigned, reserved
.long _uhoh | 60:
.long _uhoh | 61:
.long _uhoh | 62:
.long _uhoh | 63:
.long _uhoh | 64: User defined vectors (192)
.long _uhoh | 65:
.long _uhoh | 66:
.long _uhoh | 67:
.long _uhoh | 68:
.long _uhoh | 69:
.long _uhoh | 70:
.long _uhoh | 71:
.long _uhoh | 72:
.long _uhoh | 73:
.long _uhoh | 74:
.long _uhoh | 75:
.long _uhoh | 76:
.long _uhoh | 77:
.long _uhoh | 78:
.long _uhoh | 79:
.long _uhoh | 80:
.long _uhoh | 81:
.long _uhoh | 82:
.long _uhoh | 83:
.long _uhoh | 84:
.long _uhoh | 85:
.long _uhoh | 86:
.long _uhoh | 87:
.long _uhoh | 88:
.long _uhoh | 89:
.long _uhoh | 90:
.long _uhoh | 91:
.long _uhoh | 92:
.long _uhoh | 93:
.long _uhoh | 94:
.long _uhoh | 95:
.long _uhoh | 96:
.long _uhoh | 97:
.long _uhoh | 98:
.long _uhoh | 99:
.long _uhoh | 100:
.long _uhoh | 101:
.long _uhoh | 102:
.long _uhoh | 103:
.long _uhoh | 104:
.long _uhoh | 105:
.long _uhoh | 106:
.long _uhoh | 107:
.long _uhoh | 108:
.long _uhoh | 109:
.long _uhoh | 110:
.long _uhoh | 111:
.long _uhoh | 112:
.long _uhoh | 113:
.long _uhoh | 114:
.long _uhoh | 115:
.long _uhoh | 116:
.long _uhoh | 117:
.long _uhoh | 118:
.long _uhoh | 119:
.long _uhoh | 120:
.long _uhoh | 121:
.long _uhoh | 122:
.long _uhoh | 123:
.long _uhoh | 124:
.long _uhoh | 125:
.long _uhoh | 126:
.long _uhoh | 127:
.long _uhoh | 128:
.long _uhoh | 129:
.long _uhoh | 130:
.long _uhoh | 131:
.long _uhoh | 132:
.long _uhoh | 133:
.long _uhoh | 134:
.long _uhoh | 135:
.long _uhoh | 136:
.long _uhoh | 137:
.long _uhoh | 138:
.long _uhoh | 139:
.long _uhoh | 140:
.long _uhoh | 141:
.long _uhoh | 142:
.long _uhoh | 143:
.long _uhoh | 144:
.long _uhoh | 145:
.long _uhoh | 146:
.long _uhoh | 147:
.long _uhoh | 148:
.long _uhoh | 149:
.long _uhoh | 150:
.long _uhoh | 151:
.long _uhoh | 152:
.long _uhoh | 153:
.long _uhoh | 154:
.long _uhoh | 155:
.long _uhoh | 156:
.long _uhoh | 157:
.long _uhoh | 158:
.long _uhoh | 159:
.long _uhoh | 160:
.long _uhoh | 161:
.long _uhoh | 162:
.long _uhoh | 163:
.long _uhoh | 164:
.long _uhoh | 165:
.long _uhoh | 166:
.long _uhoh | 167:
.long _uhoh | 168:
.long _uhoh | 169:
.long _uhoh | 170:
.long _uhoh | 171:
.long _uhoh | 172:
.long _uhoh | 173:
.long _uhoh | 174:
.long _uhoh | 175:
.long _uhoh | 176:
.long _uhoh | 177:
.long _uhoh | 178:
.long _uhoh | 179:
.long _uhoh | 180:
.long _uhoh | 181:
.long _uhoh | 182:
.long _uhoh | 183:
.long _uhoh | 184:
.long _uhoh | 185:
.long _uhoh | 186:
.long _uhoh | 187:
.long _uhoh | 188:
.long _uhoh | 189:
.long _uhoh | 190:
.long _uhoh | 191:
.long _uhoh | 192:
.long _uhoh | 193:
.long _uhoh | 194:
.long _uhoh | 195:
.long _uhoh | 196:
.long _uhoh | 197:
.long _uhoh | 198:
.long _uhoh | 199:
.long _uhoh | 200:
.long _uhoh | 201:
.long _uhoh | 202:
.long _uhoh | 203:
.long _uhoh | 204:
.long _uhoh | 205:
.long _uhoh | 206:
.long _uhoh | 207:
.long _uhoh | 208:
.long _uhoh | 209:
.long _uhoh | 210:
.long _uhoh | 211:
.long _uhoh | 212:
.long _uhoh | 213:
.long _uhoh | 214:
.long _uhoh | 215:
.long _uhoh | 216:
.long _uhoh | 217:
.long _uhoh | 218:
.long _uhoh | 219:
.long _uhoh | 220:
.long _uhoh | 221:
.long _uhoh | 222:
.long _uhoh | 223:
.long _uhoh | 224:
.long _uhoh | 225:
.long _uhoh | 226:
.long _uhoh | 227:
.long _uhoh | 228:
.long _uhoh | 229:
.long _uhoh | 230:
.long _uhoh | 231:
.long _uhoh | 232:
.long _uhoh | 233:
.long _uhoh | 234:
.long _uhoh | 235:
.long _uhoh | 236:
.long _uhoh | 237:
.long _uhoh | 238:
.long _uhoh | 239:
.long _uhoh | 240:
.long _uhoh | 241:
.long _uhoh | 242:
.long _uhoh | 243:
.long _uhoh | 244:
.long _uhoh | 245:
.long _uhoh | 246:
.long _uhoh | 247:
.long _uhoh | 248:
.long _uhoh | 249:
.long _uhoh | 250:
.long _uhoh | 251:
.long _uhoh | 252:
.long _uhoh | 253:
.long _uhoh | 254:
.long _uhoh | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
PUBLIC (_uhoh)
_uhoh: nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.l _uhoh | Stuck forever
/*
* Log, but otherwise ignore, spurious interrupts
*/
PUBLIC (_spuriousInterrupt)
_spuriousInterrupt:
addql #1,_M68kSpuriousInterruptCount
rte
/*
* Place the low-order 3 octets of the board's ethernet address at
* a `well-known' fixed location relative to the startup location.
*/
.align 2
.word 0 | Padding
ethernet_address_buffer:
.word 0x08F3 | Default address
.word 0xDEAD
.word 0xCAFE
/*
* Initial PC
*/
.globl start
start:
/*
* Step 2: Stay in Supervisor Mode
*/
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
oriw #0x3000,sr | Switch to Master Stack Pointer
lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram
| a little below the interrupt stack
#endif
/*
* Step 3: Write the VBR
*/
lea Entry,a0 | Get base of vector table
movec a0,vbr | Set up the VBR
/*
* Step 4: Write the MBAR
*/
movec dfc,d1 | Save destination register
moveq #7,d0 | CPU-space funcction code
movec d0,dfc | Set destination function code register
movel #m360+0x101,d0 | MBAR value (mask CPU space accesses)
movesl d0,0x3FF00 | Set MBAR
movec d1,dfc | Restore destination register
/*
* Step 5: Verify a dual-port RAM location
*/
lea m360,a0 | Point a0 to first DPRAM location
moveb #0x33,d0 | Set the test value
moveb d0,a0@ | Set the memory location
cmpb a0@,d0 | Does it read back?
bne _uhoh | If not, bad news!
notb d0 | Flip bits
moveb d0,a0@ | Set the memory location
cmpb a0@,d0 | Does it read back?
bne _uhoh | If not, bad news!
/*
* Remaining steps are handled by C code
*/
jmp _Init68360 | Start C code (which never returns)
/*
* Copy DATA segment, clear BSS segment, set up real stack, start C program.
* Assume that DATA and BSS sizes are multiples of 4.
*/
PUBLIC (_CopyDataClearBSSAndStart)
_CopyDataClearBSSAndStart:
lea _copy_start,a0 | Get start of DATA in RAM
lea etext,a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea _copy_end,a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
movel #_stack_init,a7 | set master stack pointer
movel d0,a7@- | command line
jsr boot_card | Call C main
PUBLIC (_mainDone)
_mainDone:
nop | Leave spot for breakpoint
movew #1,a7 | Force a double bus error
movel d0,a7@- | This should cause a RESET
stop #0x2700 | Stop with interrupts disabled
bra.l _mainDone | Stuck forever
.align 2
END_CODE
BEGIN_DATA_DCL
.align 2
PUBLIC (environ)
environ:
.long 0
PUBLIC (_M68kSpuriousInterruptCount)
_M68kSpuriousInterruptCount:
.long 0
END_DATA_DCL
END

2
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/genmcf548x/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

432
c/src/lib/libbsp/m68k/genmcf548x/start/start.S
View File

@@ -1,432 +0,0 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: start.S |
+-----------------------------------------------------------------+
| The file contains the assembly part of MCF548x init code |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.org/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| |
\*===============================================================*/
/*===============================================================*\
| Includes |
\*===============================================================*/
#include <rtems/asm.h>
#include <bsp/linker-symbols.h>
/*===============================================================*\
| External references |
\*===============================================================*/
.extern __MBAR
.extern _CoreSramBase0
.extern _CoreSramBase1
.extern _CoreSramSize1
.extern mcf548x_init
.extern boot_card
/*===============================================================*\
| Global symbols |
\*===============================================================*/
.global interrupt_vector_table
.global spurious_int_count
.global start
/*===============================================================*\
| Exception Table |
\*===============================================================*/
.section ".vectors","ax" /* begin of vectors section */
PUBLIC (InterruptVectorTable)
SYM(InterruptVectorTable):
INITSP: .long bsp_initstack_end /* Initial SP */
INITPC: .long start /* Initial PC */
vector002: .long asm_default_interrupt /* Access Error */
vector003: .long asm_default_interrupt /* Address Error */
vector004: .long asm_default_interrupt /* Illegal Instruction */
vector005: .long asm_default_interrupt /* Reserved */
vector006: .long asm_default_interrupt /* Reserved */
vector007: .long asm_default_interrupt /* Reserved */
vector008: .long asm_default_interrupt /* Privilege Violation */
vector009: .long asm_default_interrupt /* Trace */
vector010: .long asm_default_interrupt /* Unimplemented A-Line */
vector011: .long asm_default_interrupt /* Unimplemented F-Line */
vector012: .long asm_default_interrupt /* Debug Interrupt */
vector013: .long asm_default_interrupt /* Reserved */
vector014: .long asm_default_interrupt /* Format Error */
vector015: .long asm_default_interrupt /* Unitialized Int. */
vector016: .long asm_default_interrupt /* Reserved */
vector017: .long asm_default_interrupt /* Reserved */
vector018: .long asm_default_interrupt /* Reserved */
vector019: .long asm_default_interrupt /* Reserved */
vector020: .long asm_default_interrupt /* Reserved */
vector021: .long asm_default_interrupt /* Reserved */
vector022: .long asm_default_interrupt /* Reserved */
vector023: .long asm_default_interrupt /* Reserved */
vector024: .long asm_spurious_interrupt /* Spurious Interrupt */
vector025: .long asm_default_interrupt /* Autovector Level 1 */
vector026: .long asm_default_interrupt /* Autovector Level 2 */
vector027: .long asm_default_interrupt /* Autovector Level 3 */
vector028: .long asm_default_interrupt /* Autovector Level 4 */
vector029: .long asm_default_interrupt /* Autovector Level 5 */
vector030: .long asm_default_interrupt /* Autovector Level 6 */
vector031: .long asm_default_interrupt /* Autovector Level 7 */
vector032: .long asm_default_interrupt /* TRAP #0 */
vector033: .long asm_default_interrupt /* TRAP #1 */
vector034: .long asm_default_interrupt /* TRAP #2 */
vector035: .long asm_default_interrupt /* TRAP #3 */
vector036: .long asm_default_interrupt /* TRAP #4 */
vector037: .long asm_default_interrupt /* TRAP #5 */
vector038: .long asm_default_interrupt /* TRAP #6 */
vector039: .long asm_default_interrupt /* TRAP #7 */
vector040: .long asm_default_interrupt /* TRAP #8 */
vector041: .long asm_default_interrupt /* TRAP #9 */
vector042: .long asm_default_interrupt /* TRAP #10 */
vector043: .long asm_default_interrupt /* TRAP #11 */
vector044: .long asm_default_interrupt /* TRAP #12 */
vector045: .long asm_default_interrupt /* TRAP #13 */
vector046: .long asm_default_interrupt /* TRAP #14 */
vector047: .long asm_default_interrupt /* TRAP #15 */
vector048: .long asm_default_interrupt /* Reserved */
vector049: .long asm_default_interrupt /* Reserved */
vector050: .long asm_default_interrupt /* Reserved */
vector051: .long asm_default_interrupt /* Reserved */
vector052: .long asm_default_interrupt /* Reserved */
vector053: .long asm_default_interrupt /* Reserved */
vector054: .long asm_default_interrupt /* Reserved */
vector055: .long asm_default_interrupt /* Reserved */
vector056: .long asm_default_interrupt /* Reserved */
vector057: .long asm_default_interrupt /* Reserved */
vector058: .long asm_default_interrupt /* Reserved */
vector059: .long asm_default_interrupt /* Reserved */
vector060: .long asm_default_interrupt /* Reserved */
vector061: .long asm_default_interrupt /* Reserved */
vector062: .long asm_default_interrupt /* Reserved */
vector063: .long asm_default_interrupt /* Reserved */
vector064: .long asm_default_interrupt
vector065: .long asm_default_interrupt
vector066: .long asm_default_interrupt
vector067: .long asm_default_interrupt
vector068: .long asm_default_interrupt
vector069: .long asm_default_interrupt
vector070: .long asm_default_interrupt
vector071: .long asm_default_interrupt
vector072: .long asm_default_interrupt
vector073: .long asm_default_interrupt
vector074: .long asm_default_interrupt
vector075: .long asm_default_interrupt
vector076: .long asm_default_interrupt
vector077: .long asm_default_interrupt
vector078: .long asm_default_interrupt
vector079: .long asm_default_interrupt
vector080: .long asm_default_interrupt
vector081: .long asm_default_interrupt
vector082: .long asm_default_interrupt
vector083: .long asm_default_interrupt
vector084: .long asm_default_interrupt
vector085: .long asm_default_interrupt
vector086: .long asm_default_interrupt
vector087: .long asm_default_interrupt
vector088: .long asm_default_interrupt
vector089: .long asm_default_interrupt
vector090: .long asm_default_interrupt
vector091: .long asm_default_interrupt
vector092: .long asm_default_interrupt
vector093: .long asm_default_interrupt
vector094: .long asm_default_interrupt
vector095: .long asm_default_interrupt
vector096: .long asm_default_interrupt
vector097: .long asm_default_interrupt
vector098: .long asm_default_interrupt
vector099: .long asm_default_interrupt
vector100: .long asm_default_interrupt
vector101: .long asm_default_interrupt
vector102: .long asm_default_interrupt
vector103: .long asm_default_interrupt
vector104: .long asm_default_interrupt
vector105: .long asm_default_interrupt
vector106: .long asm_default_interrupt
vector107: .long asm_default_interrupt
vector108: .long asm_default_interrupt
vector109: .long asm_default_interrupt
vector110: .long asm_default_interrupt
vector111: .long asm_default_interrupt
vector112: .long asm_default_interrupt
vector113: .long asm_default_interrupt
vector114: .long asm_default_interrupt
vector115: .long asm_default_interrupt
vector116: .long asm_default_interrupt
vector117: .long asm_default_interrupt
vector118: .long asm_default_interrupt
vector119: .long asm_default_interrupt
vector120: .long asm_default_interrupt
vector121: .long asm_default_interrupt
vector122: .long asm_default_interrupt
vector123: .long asm_default_interrupt
vector124: .long asm_default_interrupt
vector125: .long asm_default_interrupt
vector126: .long asm_default_interrupt
vector127: .long asm_default_interrupt
vector128: .long asm_default_interrupt
vector129: .long asm_default_interrupt
vector130: .long asm_default_interrupt
vector131: .long asm_default_interrupt
vector132: .long asm_default_interrupt
vector133: .long asm_default_interrupt
vector134: .long asm_default_interrupt
vector135: .long asm_default_interrupt
vector136: .long asm_default_interrupt
vector137: .long asm_default_interrupt
vector138: .long asm_default_interrupt
vector139: .long asm_default_interrupt
vector140: .long asm_default_interrupt
vector141: .long asm_default_interrupt
vector142: .long asm_default_interrupt
vector143: .long asm_default_interrupt
vector144: .long asm_default_interrupt
vector145: .long asm_default_interrupt
vector146: .long asm_default_interrupt
vector147: .long asm_default_interrupt
vector148: .long asm_default_interrupt
vector149: .long asm_default_interrupt
vector150: .long asm_default_interrupt
vector151: .long asm_default_interrupt
vector152: .long asm_default_interrupt
vector153: .long asm_default_interrupt
vector154: .long asm_default_interrupt
vector155: .long asm_default_interrupt
vector156: .long asm_default_interrupt
vector157: .long asm_default_interrupt
vector158: .long asm_default_interrupt
vector159: .long asm_default_interrupt
vector160: .long asm_default_interrupt
vector161: .long asm_default_interrupt
vector162: .long asm_default_interrupt
vector163: .long asm_default_interrupt
vector164: .long asm_default_interrupt
vector165: .long asm_default_interrupt
vector166: .long asm_default_interrupt
vector167: .long asm_default_interrupt
vector168: .long asm_default_interrupt
vector169: .long asm_default_interrupt
vector170: .long asm_default_interrupt
vector171: .long asm_default_interrupt
vector172: .long asm_default_interrupt
vector173: .long asm_default_interrupt
vector174: .long asm_default_interrupt
vector175: .long asm_default_interrupt
vector176: .long asm_default_interrupt
vector177: .long asm_default_interrupt
vector178: .long asm_default_interrupt
vector179: .long asm_default_interrupt
vector180: .long asm_default_interrupt
vector181: .long asm_default_interrupt
vector182: .long asm_default_interrupt
vector183: .long asm_default_interrupt
vector184: .long asm_default_interrupt
vector185: .long asm_default_interrupt
vector186: .long asm_default_interrupt
vector187: .long asm_default_interrupt
vector188: .long asm_default_interrupt
vector189: .long asm_default_interrupt
vector190: .long asm_default_interrupt
vector191: .long asm_default_interrupt
vector192: .long asm_default_interrupt
vector193: .long asm_default_interrupt
vector194: .long asm_default_interrupt
vector195: .long asm_default_interrupt
vector196: .long asm_default_interrupt
vector197: .long asm_default_interrupt
vector198: .long asm_default_interrupt
vector199: .long asm_default_interrupt
vector200: .long asm_default_interrupt
vector201: .long asm_default_interrupt
vector202: .long asm_default_interrupt
vector203: .long asm_default_interrupt
vector204: .long asm_default_interrupt
vector205: .long asm_default_interrupt
vector206: .long asm_default_interrupt
vector207: .long asm_default_interrupt
vector208: .long asm_default_interrupt
vector209: .long asm_default_interrupt
vector210: .long asm_default_interrupt
vector211: .long asm_default_interrupt
vector212: .long asm_default_interrupt
vector213: .long asm_default_interrupt
vector214: .long asm_default_interrupt
vector215: .long asm_default_interrupt
vector216: .long asm_default_interrupt
vector217: .long asm_default_interrupt
vector218: .long asm_default_interrupt
vector219: .long asm_default_interrupt
vector220: .long asm_default_interrupt
vector221: .long asm_default_interrupt
vector222: .long asm_default_interrupt
vector223: .long asm_default_interrupt
vector224: .long asm_default_interrupt
vector225: .long asm_default_interrupt
vector226: .long asm_default_interrupt
vector227: .long asm_default_interrupt
vector228: .long asm_default_interrupt
vector229: .long asm_default_interrupt
vector230: .long asm_default_interrupt
vector231: .long asm_default_interrupt
vector232: .long asm_default_interrupt
vector233: .long asm_default_interrupt
vector234: .long asm_default_interrupt
vector235: .long asm_default_interrupt
vector236: .long asm_default_interrupt
vector237: .long asm_default_interrupt
vector238: .long asm_default_interrupt
vector239: .long asm_default_interrupt
vector240: .long asm_default_interrupt
vector241: .long asm_default_interrupt
vector242: .long asm_default_interrupt
vector243: .long asm_default_interrupt
vector244: .long asm_default_interrupt
vector245: .long asm_default_interrupt
vector246: .long asm_default_interrupt
vector247: .long asm_default_interrupt
vector248: .long asm_default_interrupt
vector249: .long asm_default_interrupt
vector250: .long asm_default_interrupt
vector251: .long asm_default_interrupt
vector252: .long asm_default_interrupt
vector253: .long asm_default_interrupt
vector254: .long asm_default_interrupt
vector255: .long asm_default_interrupt
/*===============================================================*\
| Start of code |
\*===============================================================*/
.text
PUBLIC (start)
SYM(start):
move.w #0x3700,sr /* disable interrupts */
jmp start_init
/*===============================================================*\
| Sspurious interrupt counter |
\*===============================================================*/
.align 4
.data /* begin of data section */
PUBLIC (spurious_int_count)
SYM(spurious_int_count):
.long 0 /* spurious interrupt counter */
/*===============================================================*\
| Function: Default exception handler |
+-----------------------------------------------------------------+
| - stop and disable all interrupts |
| - loop forever |
\*===============================================================*/
.text /* start of text section */
.align 4
PUBLIC (asm_default_interrupt)
SYM(asm_default_interrupt):
nop
stop #0x3700 /* stop */
bra.w asm_default_interrupt /* loop forever */
/*===============================================================*\
| Function: Exception handler for spurious interrupts |
+-----------------------------------------------------------------+
| - count spurious interrupts |
\*===============================================================*/
.align 4
PUBLIC (asm_spurious_interrupt)
SYM(asm_spurious_interrupt):
add.l #1,spurious_int_count
rte
/*===============================================================*\
| Function: start_init |
+-----------------------------------------------------------------+
| - Disable all intterupts |
| - Setup the internal SRAM |
| - Initialize mcf548x peripherals |
| - Set initial stack pointer |
| - Boot RTEMS
\*===============================================================*/
.align 4
PUBLIC (start_init)
SYM(start_init):
move.l #0x01040100,d0 /* invalidate instruction/data/branch cache, disable all caches */
movec d0,cacr
move.l #_CoreSramBase0,d0 /* initialize RAMBAR0 */
add.l #0x21,d0 /* for code & data */
movec d0,rambar0
move.l #_CoreSramBase1,d0 /* initialize RAMBAR1 */
add.l #0x21,d0 /* for code & data */
movec d0,rambar1 /* movec d0,RAMBAR1 */
move.l #__MBAR,d0 /* initialize MBAR */
movec d0,mbar
move.l #_CoreSramBase1,d0 /* set sp to end of Core SRAM temporarily */
add.l #_CoreSramSize1,d0
move.l d0,sp
move.l #0,d0 /* initialize frame pointer */
movea.l d0,a6
jsr mcf548x_init /* Initialize mcf548x peripherals */
move.l #bsp_initstack_end,sp /* relocate sp */
clrl d0 /* clear d0 */
movel d0,a7@- /* command line == 0 */
jsr boot_card /* boot rtems */
movel a7@+,d0
exit_multitasking:
nop
nop
halt
bra exit_multitasking
.end /* end of start.S module */

2
c/src/lib/libbsp/m68k/mcf5206elite/Makefile.am
View File

@@ -10,7 +10,7 @@ _SUBDIRS = . tools
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/mcf5206elite/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

415
c/src/lib/libbsp/m68k/mcf5206elite/start/start.S
View File

@@ -1,415 +0,0 @@
/*
* MCF5206eLITE startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*/
/*
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* Based on work:
* Author:
* David Fiddes, D.J@fiddes.surfaid.org
* http://www.calm.hw.ac.uk/davidf/coldfire/
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
#include "bsp.h"
BEGIN_CODE
/* Initial stack situated in on-chip static memory */
#define INITIAL_STACK BSP_MEM_ADDR_SRAM+BSP_MEM_SIZE_SRAM-4
PUBLIC (INTERRUPT_VECTOR)
SYM(INTERRUPT_VECTOR):
.long INITIAL_STACK | 00: initial SSP
.long start | 01: Initial PC
.long _unexp_exception | 02: Access Error
.long _unexp_exception | 03: Address Error
.long _unexp_exception | 04: Illegal Instruction
.long _reserved_int | 05: Reserved
.long _reserved_int | 06: Reserved
.long _reserved_int | 07: Reserved
.long _unexp_exception | 08: Priveledge Violation
.long _unexp_exception | 09: Trace
.long _unexp_exception | 0A: Unimplemented A-Line
.long _unexp_exception | 0B: Unimplemented F-Line
.long _unexp_exception | 0C: Debug interrupt
.long _reserved_int | 0D: Reserved
.long _unexp_exception | 0E: Format error
.long _unexp_exception | 0F: Uninitialized interrupt
.long _reserved_int | 10: Reserved
.long _reserved_int | 11: Reserved
.long _reserved_int | 12: Reserved
.long _reserved_int | 13: Reserved
.long _reserved_int | 14: Reserved
.long _reserved_int | 15: Reserved
.long _reserved_int | 16: Reserved
.long _reserved_int | 17: Reserved
.long _spurious_int | 18: Spurious interrupt
.long _avec1_int | 19: Autovector Level 1
.long _avec2_int | 1A: Autovector Level 2
.long _avec3_int | 1B: Autovector Level 3
.long _avec4_int | 1C: Autovector Level 4
.long _avec5_int | 1D: Autovector Level 5
.long _avec6_int | 1E: Autovector Level 6
.long _avec7_int | 1F: Autovector Level 7
.long _unexp_exception | 20: TRAP #0
.long _unexp_exception | 21: TRAP #1
.long _unexp_exception | 22: TRAP #2
.long _unexp_exception | 23: TRAP #3
.long _unexp_exception | 24: TRAP #4
.long _unexp_exception | 25: TRAP #5
.long _unexp_exception | 26: TRAP #6
.long _unexp_exception | 27: TRAP #7
.long _unexp_exception | 28: TRAP #8
.long _unexp_exception | 29: TRAP #9
.long _unexp_exception | 2A: TRAP #10
.long _unexp_exception | 2B: TRAP #11
.long _unexp_exception | 2C: TRAP #12
.long _unexp_exception | 2D: TRAP #13
.long _unexp_exception | 2E: TRAP #14
.long _unexp_exception | 2F: TRAP #15
.long _reserved_int | 30: Reserved
.long _reserved_int | 31: Reserved
.long _reserved_int | 32: Reserved
.long _reserved_int | 33: Reserved
.long _reserved_int | 34: Reserved
.long _reserved_int | 35: Reserved
.long _reserved_int | 36: Reserved
.long _reserved_int | 37: Reserved
.long _reserved_int | 38: Reserved
.long _reserved_int | 39: Reserved
.long _reserved_int | 3A: Reserved
.long _reserved_int | 3B: Reserved
.long _reserved_int | 3C: Reserved
.long _reserved_int | 3D: Reserved
.long _reserved_int | 3E: Reserved
.long _reserved_int | 3F: Reserved
.long _unexp_int | 40-FF: User defined interrupts
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 50:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 60:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 70:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 80:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | 90:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | A0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | B0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | C0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | D0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | E0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int | F0:
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
.long _unexp_int
PUBLIC(start)
SYM(start):
move.w #0x2700,sr | First turn off all interrupts!
move.l #(BSP_MEM_ADDR_SRAM + MCF5206E_RAMBAR_V),d0
movec d0,rambar0 | ...so we have a stack
move.l #(INITIAL_STACK),sp | Set up stack again (may be we are
| going here from monitor or with
| BDM interface assistance)
/*
* Remainder of the startup code is handled by C code
*/
jmp SYM(Init5206e) | Start C code (which never returns)
/***************************************************************************
Function : CopyDataClearBSSAndStart
Description : Copy DATA segment, clear BSS segment, initialize heap,
initialise real stack, start C program. Assume that DATA and BSS sizes
are multiples of 4.
***************************************************************************/
PUBLIC (CopyDataClearBSSAndStart)
SYM(CopyDataClearBSSAndStart):
lea copy_start,a0 | Get start of DATA in RAM
lea SYM(etext),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea copy_end,a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea clear_start,a0 | Get start of BSS
lea clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
move 4(a7),d0
/*
* Right : Now we're ready to boot RTEMS
*/
clrl d0 | Pass in null to all boot_card() params
movel d0,a7@- | command line
jsr SYM(boot_card) | Call C boot_card function to startup RTEMS
# Wait forever
_stop:
nop
stop #0x2700
jmp _stop
# The following labelled nops is a placeholders for breakpoints
_unexp_exception:
nop
jmp _stop
_unexp_int:
nop
jmp _stop
_reserved_int:
nop
jmp _stop
_spurious_int:
nop
jmp _stop
_avec1_int:
nop
jmp _unexp_int
_avec2_int:
nop
jmp _unexp_int
_avec3_int:
nop
jmp _unexp_int
_avec4_int:
nop
jmp _unexp_int
_avec5_int:
nop
jmp _unexp_int
_avec6_int:
nop
jmp _unexp_int
_avec7_int:
nop
jmp _unexp_int
END_CODE
END

2
c/src/lib/libbsp/m68k/mcf52235/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/mcf52235/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

449
c/src/lib/libbsp/m68k/mcf52235/start/start.S
View File

@@ -1,449 +0,0 @@
/*
* mcf52235 startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
.extern _StackInit
BEGIN_CODE
PUBLIC (_INTERRUPT_VECTOR)
SYM(_INTERRUPT_VECTOR):
.long _StackInit /* 00 Initial 'SSP' */
.long SYM(start) /* 01 Initial PC */
.long SYM(_uhoh) /* 02 Access Error */
.long SYM(_uhoh) /* 03 Address Error */
.long SYM(_uhoh) /* 04 Illegal Instruction */
.long SYM(_uhoh) /* 05 Divide by Zero */
.long SYM(_uhoh) /* 06 Reserved */
.long SYM(_uhoh) /* 07 Reserved */
.long SYM(_uhoh) /* 08 Privilege Violation */
.long SYM(_uhoh) /* 09 Trace */
.long SYM(_uhoh) /* 10 Unimplemented A-Line */
.long SYM(_uhoh) /* 11 Unimplemented F-Line */
.long SYM(_uhoh) /* 12 Debug Interrupt */
.long SYM(_uhoh) /* 13 Reserved */
.long SYM(_uhoh) /* 14 Format Error */
.long SYM(_uhoh) /* 15 Reserved */
.long SYM(_uhoh) /* 16 Reserved */
.long SYM(_uhoh) /* 17 Reserved */
.long SYM(_uhoh) /* 18 Reserved */
.long SYM(_uhoh) /* 19 Reserved */
.long SYM(_uhoh) /* 20 Reserved */
.long SYM(_uhoh) /* 21 Reserved */
.long SYM(_uhoh) /* 22 Reserved */
.long SYM(_uhoh) /* 23 Reserved */
.long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */
.long SYM(_uhoh) /* 25 Reserved */
.long SYM(_uhoh) /* 26 Reserved */
.long SYM(_uhoh) /* 27 Reserved */
.long SYM(_uhoh) /* 28 Reserved */
.long SYM(_uhoh) /* 29 Reserved */
.long SYM(_uhoh) /* 30 Reserved */
.long SYM(_uhoh) /* 31 Reserved */
.long SYM(_uhoh) /* 32 TRAP #0 */
.long SYM(_uhoh) /* 33 TRAP #1 */
.long SYM(_uhoh) /* 34 TRAP #2 */
.long SYM(_uhoh) /* 35 TRAP #3 */
.long SYM(_uhoh) /* 36 TRAP #4 */
.long SYM(_uhoh) /* 37 TRAP #5 */
.long SYM(_uhoh) /* 38 TRAP #6 */
.long SYM(_uhoh) /* 39 TRAP #7 */
.long SYM(_uhoh) /* 40 TRAP #8 */
.long SYM(_uhoh) /* 41 TRAP #9 */
.long SYM(_uhoh) /* 42 TRAP #10 */
.long SYM(_uhoh) /* 43 TRAP #11 */
.long SYM(_uhoh) /* 44 TRAP #12 */
.long SYM(_uhoh) /* 45 TRAP #13 */
.long SYM(_uhoh) /* 46 TRAP #14 */
.long SYM(_uhoh) /* 47 TRAP #15 */
.long SYM(_uhoh) /* 48 Reserved */
.long SYM(_uhoh) /* 49 Reserved */
.long SYM(_uhoh) /* 50 Reserved */
.long SYM(_uhoh) /* 51 Reserved */
.long SYM(_uhoh) /* 52 Reserved */
.long SYM(_uhoh) /* 53 Reserved */
.long SYM(_uhoh) /* 54 Reserved */
.long SYM(_uhoh) /* 55 Reserved */
.long SYM(_uhoh) /* 56 Reserved */
.long SYM(_uhoh) /* 57 Reserved */
.long SYM(_uhoh) /* 58 Reserved */
.long SYM(_uhoh) /* 59 Reserved */
.long SYM(_uhoh) /* 60 Reserved */
.long SYM(_uhoh) /* 61 Reserved */
.long SYM(_uhoh) /* 62 Reserved */
.long SYM(_uhoh) /* 63 Reserved */
/* INTC0 */
.long SYM(_uhoh) /* 64*/
.long SYM(_uhoh) /* 65*/
.long SYM(_uhoh) /* 66*/
.long SYM(_uhoh) /* 67*/
.long SYM(_uhoh) /* 68*/
.long SYM(_uhoh) /* 69*/
.long SYM(_uhoh) /* 70*/
.long SYM(_uhoh) /* 71*/
.long SYM(_uhoh) /* 72*/
.long SYM(_uhoh) /* 73*/
.long SYM(_uhoh) /* 74*/
.long SYM(_uhoh) /* 75*/
.long SYM(_uhoh) /* 76*/
.long SYM(_uhoh) /* 77*/
.long SYM(_uhoh) /* 78*/
.long SYM(_uhoh) /* 79*/
.long SYM(_uhoh) /* 80*/
.long SYM(_uhoh) /* 81*/
.long SYM(_uhoh) /* 82*/
.long SYM(_uhoh) /* 83*/
.long SYM(_uhoh) /* 84*/
.long SYM(_uhoh) /* 85*/
.long SYM(_uhoh) /* 86*/
.long SYM(_uhoh) /* 87*/
.long SYM(_uhoh) /* 88*/
.long SYM(_uhoh) /* 89*/
.long SYM(_uhoh) /* 90*/
.long SYM(_uhoh) /* 91*/
.long SYM(_uhoh) /* 92*/
.long SYM(_uhoh) /* 93*/
.long SYM(_uhoh) /* 94*/
.long SYM(_uhoh) /* 95*/
.long SYM(_uhoh) /* 96*/
.long SYM(_uhoh) /* 97*/
.long SYM(_uhoh) /* 98*/
.long SYM(_uhoh) /* 99*/
.long SYM(_uhoh) /* 100*/
.long SYM(_uhoh) /* 101*/
.long SYM(_uhoh) /* 102*/
.long SYM(_uhoh) /* 103*/
.long SYM(_uhoh) /* 104*/
.long SYM(_uhoh) /* 105*/
.long SYM(_uhoh) /* 106*/
.long SYM(_uhoh) /* 107*/
.long SYM(_uhoh) /* 108*/
.long SYM(_uhoh) /* 109*/
.long SYM(_uhoh) /* 110*/
.long SYM(_uhoh) /* 111*/
.long SYM(_uhoh) /* 112*/
.long SYM(_uhoh) /* 113*/
.long SYM(_uhoh) /* 114*/
.long SYM(_uhoh) /* 115*/
.long SYM(_uhoh) /* 116*/
.long SYM(_uhoh) /* 117*/
.long SYM(_uhoh) /* 118*/
.long SYM(_uhoh) /* 119*/
.long SYM(_uhoh) /* 120*/
.long SYM(_uhoh) /* 121*/
.long SYM(_uhoh) /* 122*/
.long SYM(_uhoh) /* 123*/
.long SYM(_uhoh) /* 124*/
.long SYM(_uhoh) /* 125*/
.long SYM(_uhoh) /* 126*/
.long SYM(_uhoh) /* 127*/
/* INTC1 */
.long SYM(_uhoh) /* 128*/
.long SYM(_uhoh) /* 129*/
.long SYM(_uhoh) /* 130*/
.long SYM(_uhoh) /* 131*/
.long SYM(_uhoh) /* 132*/
.long SYM(_uhoh) /* 133*/
.long SYM(_uhoh) /* 134*/
.long SYM(_uhoh) /* 135*/
.long SYM(_uhoh) /* 136*/
.long SYM(_uhoh) /* 137*/
.long SYM(_uhoh) /* 138*/
.long SYM(_uhoh) /* 139*/
.long SYM(_uhoh) /* 140*/
.long SYM(_uhoh) /* 141*/
.long SYM(_uhoh) /* 142*/
.long SYM(_uhoh) /* 143*/
.long SYM(_uhoh) /* 144*/
.long SYM(_uhoh) /* 145*/
.long SYM(_uhoh) /* 146*/
.long SYM(_uhoh) /* 147*/
.long SYM(_uhoh) /* 148*/
.long SYM(_uhoh) /* 149*/
.long SYM(_uhoh) /* 150*/
.long SYM(_uhoh) /* 151*/
.long SYM(_uhoh) /* 152*/
.long SYM(_uhoh) /* 153*/
.long SYM(_uhoh) /* 154*/
.long SYM(_uhoh) /* 155*/
.long SYM(_uhoh) /* 156*/
.long SYM(_uhoh) /* 157*/
.long SYM(_uhoh) /* 158*/
.long SYM(_uhoh) /* 159*/
.long SYM(_uhoh) /* 160*/
.long SYM(_uhoh) /* 161*/
.long SYM(_uhoh) /* 162*/
.long SYM(_uhoh) /* 163*/
.long SYM(_uhoh) /* 164*/
.long SYM(_uhoh) /* 165*/
.long SYM(_uhoh) /* 166*/
.long SYM(_uhoh) /* 167*/
.long SYM(_uhoh) /* 168*/
.long SYM(_uhoh) /* 169*/
.long SYM(_uhoh) /* 170*/
.long SYM(_uhoh) /* 171*/
.long SYM(_uhoh) /* 172*/
.long SYM(_uhoh) /* 173*/
.long SYM(_uhoh) /* 174*/
.long SYM(_uhoh) /* 175*/
.long SYM(_uhoh) /* 176*/
.long SYM(_uhoh) /* 177*/
.long SYM(_uhoh) /* 178*/
.long SYM(_uhoh) /* 179*/
.long SYM(_uhoh) /* 180*/
.long SYM(_uhoh) /* 181*/
.long SYM(_uhoh) /* 182*/
.long SYM(_uhoh) /* 183*/
.long SYM(_uhoh) /* 184*/
.long SYM(_uhoh) /* 185*/
.long SYM(_uhoh) /* 186*/
.long SYM(_uhoh) /* 187*/
.long SYM(_uhoh) /* 188*/
.long SYM(_uhoh) /* 189*/
.long SYM(_uhoh) /* 190*/
.long SYM(_uhoh) /* 191*/
.long SYM(_uhoh) /* 192*/
/* */
.long SYM(_uhoh) /* 193*/
.long SYM(_uhoh) /* 194*/
.long SYM(_uhoh) /* 195*/
.long SYM(_uhoh) /* 196*/
.long SYM(_uhoh) /* 197*/
.long SYM(_uhoh) /* 198*/
.long SYM(_uhoh) /* 199*/
.long SYM(_uhoh) /* 200*/
.long SYM(_uhoh) /* 201*/
.long SYM(_uhoh) /* 202*/
.long SYM(_uhoh) /* 203*/
.long SYM(_uhoh) /* 204*/
.long SYM(_uhoh) /* 205*/
.long SYM(_uhoh) /* 206*/
.long SYM(_uhoh) /* 207*/
.long SYM(_uhoh) /* 208*/
.long SYM(_uhoh) /* 209*/
.long SYM(_uhoh) /* 210*/
.long SYM(_uhoh) /* 211*/
.long SYM(_uhoh) /* 212*/
.long SYM(_uhoh) /* 213*/
.long SYM(_uhoh) /* 214*/
.long SYM(_uhoh) /* 215*/
.long SYM(_uhoh) /* 216*/
.long SYM(_uhoh) /* 217*/
.long SYM(_uhoh) /* 218*/
.long SYM(_uhoh) /* 219*/
.long SYM(_uhoh) /* 220*/
.long SYM(_uhoh) /* 221*/
.long SYM(_uhoh) /* 222*/
.long SYM(_uhoh) /* 223*/
.long SYM(_uhoh) /* 224*/
.long SYM(_uhoh) /* 225*/
.long SYM(_uhoh) /* 226*/
.long SYM(_uhoh) /* 227*/
.long SYM(_uhoh) /* 228*/
.long SYM(_uhoh) /* 229*/
.long SYM(_uhoh) /* 230*/
.long SYM(_uhoh) /* 231*/
.long SYM(_uhoh) /* 232*/
.long SYM(_uhoh) /* 233*/
.long SYM(_uhoh) /* 234*/
.long SYM(_uhoh) /* 235*/
.long SYM(_uhoh) /* 236*/
.long SYM(_uhoh) /* 237*/
.long SYM(_uhoh) /* 238*/
.long SYM(_uhoh) /* 239*/
.long SYM(_uhoh) /* 240*/
.long SYM(_uhoh) /* 241*/
.long SYM(_uhoh) /* 242*/
.long SYM(_uhoh) /* 243*/
.long SYM(_uhoh) /* 244*/
.long SYM(_uhoh) /* 245*/
.long SYM(_uhoh) /* 246*/
.long SYM(_uhoh) /* 247*/
.long SYM(_uhoh) /* 248*/
.long SYM(_uhoh) /* 249*/
.long SYM(_uhoh) /* 250*/
.long SYM(_uhoh) /* 251*/
.long SYM(_uhoh) /* 252*/
.long SYM(_uhoh) /* 253*/
.long SYM(_uhoh) /* 254*/
.long SYM(_uhoh) /* 255*/
/*
* We must write the flash configuration here. This portion of flash is shadowed
* by some flash registers, so we can't put code here!
*/
PUBLIC (_FLASH_CONFIGURATION_FIELD)
SYM(_FLASH_CONFIGURATION_FIELD):
_key_upper: .long 0x00000000
_key_lower: .long 0x00000000
_cfm_prot: .long 0x00000000
_cfm_sacc: .long 0x00000000
_cfm_dacc: .long 0x00000000
_cfm_msec: .long 0x00000000
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
/*
* Spurious Interrupt Handler
*/
.align 4
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1, SYM(_M68kSpuriousInterruptCount)
rte
/*
* Write VBR Register
*/
.align 4
PUBLIC (_wr_vbr)
SYM(_wr_vbr):
move.l 4(sp), d0
movec d0, vbr
nop
rts
/*
* Board startup
* Disable watchdog, interrupts
* Enable sram
*/
.align 4
PUBLIC (start)
SYM(start):
/* Mask off interupts */
move.w #0x2700, sr
/* Save off reset values of D0 and D1 */
move.l d0, d6
move.l d1, d7
/* Initialize RAMBAR: locate SRAM and validate it */
move.l #RamBase, d0
add.l #0x21, d0
movec d0, %rambar
/* Locate Stack Pointer */
move.l #_StackInit, sp
/* Initialize FLASHBAR */
move.l #_FlashBase, d0
cmp.l #0x00000000, d0
bne _change_flashbar
add.l #0x61, d0
movec d0, %flashbar
_continue_startup:
/* Locate Stack Pointer */
move.l #_StackInit, sp
/* Save off intial D0 and D1 to RAM */
move.l d6, SYM(_d0_reset)
move.l d7, SYM(_d1_reset)
/*
* Remainder of the startup code is handled by C code
* This never returns
*/
jmp SYM(Init52235)
_change_flashbar:
/*
* The following sequence is used to set FLASHBAR. Since we may
* be executing from Flash, we must put the routine into SRAM for
* execution and then jump back to Flash using the new address.
*
* The following instructions are coded into the SRAM:
*
* move.l #(__FLASH + 0x61),d0
* movec d0, FLASHBAR
* jmp _continue_startup
*
* An arbitrary SRAM address is chosen until the real address
* can be loaded.
*
* This routine is not necessary if the default Flash address
* (0x00000000) is used.
*
* If running in SRAM, change_flashbar should not be executed
*/
move.l #RamBase, a0
/* Code "move.l #(__FLASH + 0x61),d0" into SRAM */
move.w #0x203C, d0
move.w d0, (a0)+
move.l #_FlashBase, d0
add.l #0x61, d0
move.l d0, (a0)+
/* Code "movec d0,FLASHBAR" into SRAM */
move.l #0x4e7b0C04, d0
move.l d0, (a0)+
/* Code "jmp _continue_startup" into SRAM */
move.w #0x4EF9, d0
move.w d0, (a0)+
move.l #_continue_startup, d0
move.l d0, (a0)+
/* Jump to code segment in internal SRAM */
jmp RamBase
END_CODE
BEGIN_DATA_DCL
.align 4
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
PUBLIC (_d0_reset)
SYM (_d0_reset):
.long 0
PUBLIC (_d1_reset)
SYM (_d1_reset):
.long 0
END_DATA_DCL
END

2
c/src/lib/libbsp/m68k/mcf5225x/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/mcf5225x/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

450
c/src/lib/libbsp/m68k/mcf5225x/start/start.S
View File

@@ -1,450 +0,0 @@
/*
* dpu-mcf52258 startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
.extern _StackInit
BEGIN_CODE
PUBLIC (_INTERRUPT_VECTOR)
SYM(_INTERRUPT_VECTOR):
.long _StackInit /* 00 Initial 'SSP' */
.long SYM(start) /* 01 Initial PC */
.long SYM(_uhoh) /* 02 Access Error */
.long SYM(_uhoh) /* 03 Address Error */
.long SYM(_uhoh) /* 04 Illegal Instruction */
.long SYM(_uhoh) /* 05 Divide by Zero */
.long SYM(_uhoh) /* 06 Reserved */
.long SYM(_uhoh) /* 07 Reserved */
.long SYM(_uhoh) /* 08 Privilege Violation */
.long SYM(_uhoh) /* 09 Trace */
.long SYM(_uhoh) /* 10 Unimplemented A-Line */
.long SYM(_uhoh) /* 11 Unimplemented F-Line */
.long SYM(_uhoh) /* 12 Debug Interrupt */
.long SYM(_uhoh) /* 13 Reserved */
.long SYM(_uhoh) /* 14 Format Error */
.long SYM(_uhoh) /* 15 Reserved */
.long SYM(_uhoh) /* 16 Reserved */
.long SYM(_uhoh) /* 17 Reserved */
.long SYM(_uhoh) /* 18 Reserved */
.long SYM(_uhoh) /* 19 Reserved */
.long SYM(_uhoh) /* 20 Reserved */
.long SYM(_uhoh) /* 21 Reserved */
.long SYM(_uhoh) /* 22 Reserved */
.long SYM(_uhoh) /* 23 Reserved */
.long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */
.long SYM(_uhoh) /* 25 Reserved */
.long SYM(_uhoh) /* 26 Reserved */
.long SYM(_uhoh) /* 27 Reserved */
.long SYM(_uhoh) /* 28 Reserved */
.long SYM(_uhoh) /* 29 Reserved */
.long SYM(_uhoh) /* 30 Reserved */
.long SYM(_uhoh) /* 31 Reserved */
.long SYM(_uhoh) /* 32 TRAP #0 */
.long SYM(_uhoh) /* 33 TRAP #1 */
.long SYM(_uhoh) /* 34 TRAP #2 */
.long SYM(_uhoh) /* 35 TRAP #3 */
.long SYM(_uhoh) /* 36 TRAP #4 */
.long SYM(_uhoh) /* 37 TRAP #5 */
.long SYM(_uhoh) /* 38 TRAP #6 */
.long SYM(_uhoh) /* 39 TRAP #7 */
.long SYM(_uhoh) /* 40 TRAP #8 */
.long SYM(_uhoh) /* 41 TRAP #9 */
.long SYM(_uhoh) /* 42 TRAP #10 */
.long SYM(_uhoh) /* 43 TRAP #11 */
.long SYM(_uhoh) /* 44 TRAP #12 */
.long SYM(_uhoh) /* 45 TRAP #13 */
.long SYM(_uhoh) /* 46 TRAP #14 */
.long SYM(_uhoh) /* 47 TRAP #15 */
.long SYM(_uhoh) /* 48 Reserved */
.long SYM(_uhoh) /* 49 Reserved */
.long SYM(_uhoh) /* 50 Reserved */
.long SYM(_uhoh) /* 51 Reserved */
.long SYM(_uhoh) /* 52 Reserved */
.long SYM(_uhoh) /* 53 Reserved */
.long SYM(_uhoh) /* 54 Reserved */
.long SYM(_uhoh) /* 55 Reserved */
.long SYM(_uhoh) /* 56 Reserved */
.long SYM(_uhoh) /* 57 Reserved */
.long SYM(_uhoh) /* 58 Reserved */
.long SYM(_uhoh) /* 59 Reserved */
.long SYM(_uhoh) /* 60 Reserved */
.long SYM(_uhoh) /* 61 Reserved */
.long SYM(_uhoh) /* 62 Reserved */
.long SYM(_uhoh) /* 63 Reserved */
/* INTC0 */
.long SYM(_uhoh) /* 64*/
.long SYM(_uhoh) /* 65*/
.long SYM(_uhoh) /* 66*/
.long SYM(_uhoh) /* 67*/
.long SYM(_uhoh) /* 68*/
.long SYM(_uhoh) /* 69*/
.long SYM(_uhoh) /* 70*/
.long SYM(_uhoh) /* 71*/
.long SYM(_uhoh) /* 72*/
.long SYM(_uhoh) /* 73*/
.long SYM(_uhoh) /* 74*/
.long SYM(_uhoh) /* 75*/
.long SYM(_uhoh) /* 76*/
.long SYM(_uhoh) /* 77*/
.long SYM(_uhoh) /* 78*/
.long SYM(_uhoh) /* 79*/
.long SYM(_uhoh) /* 80*/
.long SYM(_uhoh) /* 81*/
.long SYM(_uhoh) /* 82*/
.long SYM(_uhoh) /* 83*/
.long SYM(_uhoh) /* 84*/
.long SYM(_uhoh) /* 85*/
.long SYM(_uhoh) /* 86*/
.long SYM(_uhoh) /* 87*/
.long SYM(_uhoh) /* 88*/
.long SYM(_uhoh) /* 89*/
.long SYM(_uhoh) /* 90*/
.long SYM(_uhoh) /* 91*/
.long SYM(_uhoh) /* 92*/
.long SYM(_uhoh) /* 93*/
.long SYM(_uhoh) /* 94*/
.long SYM(_uhoh) /* 95*/
.long SYM(_uhoh) /* 96*/
.long SYM(_uhoh) /* 97*/
.long SYM(_uhoh) /* 98*/
.long SYM(_uhoh) /* 99*/
.long SYM(_uhoh) /* 100*/
.long SYM(_uhoh) /* 101*/
.long SYM(_uhoh) /* 102*/
.long SYM(_uhoh) /* 103*/
.long SYM(_uhoh) /* 104*/
.long SYM(_uhoh) /* 105*/
.long SYM(_uhoh) /* 106*/
.long SYM(_uhoh) /* 107*/
.long SYM(_uhoh) /* 108*/
.long SYM(_uhoh) /* 109*/
.long SYM(_uhoh) /* 110*/
.long SYM(_uhoh) /* 111*/
.long SYM(_uhoh) /* 112*/
.long SYM(_uhoh) /* 113*/
.long SYM(_uhoh) /* 114*/
.long SYM(_uhoh) /* 115*/
.long SYM(_uhoh) /* 116*/
.long SYM(_uhoh) /* 117*/
.long SYM(_uhoh) /* 118*/
.long SYM(_uhoh) /* 119*/
.long SYM(_uhoh) /* 120*/
.long SYM(_uhoh) /* 121*/
.long SYM(_uhoh) /* 122*/
.long SYM(_uhoh) /* 123*/
.long SYM(_uhoh) /* 124*/
.long SYM(_uhoh) /* 125*/
.long SYM(_uhoh) /* 126*/
.long SYM(_uhoh) /* 127*/
/* INTC1 */
.long SYM(_uhoh) /* 128*/
.long SYM(_uhoh) /* 129*/
.long SYM(_uhoh) /* 130*/
.long SYM(_uhoh) /* 131*/
.long SYM(_uhoh) /* 132*/
.long SYM(_uhoh) /* 133*/
.long SYM(_uhoh) /* 134*/
.long SYM(_uhoh) /* 135*/
.long SYM(_uhoh) /* 136*/
.long SYM(_uhoh) /* 137*/
.long SYM(_uhoh) /* 138*/
.long SYM(_uhoh) /* 139*/
.long SYM(_uhoh) /* 140*/
.long SYM(_uhoh) /* 141*/
.long SYM(_uhoh) /* 142*/
.long SYM(_uhoh) /* 143*/
.long SYM(_uhoh) /* 144*/
.long SYM(_uhoh) /* 145*/
.long SYM(_uhoh) /* 146*/
.long SYM(_uhoh) /* 147*/
.long SYM(_uhoh) /* 148*/
.long SYM(_uhoh) /* 149*/
.long SYM(_uhoh) /* 150*/
.long SYM(_uhoh) /* 151*/
.long SYM(_uhoh) /* 152*/
.long SYM(_uhoh) /* 153*/
.long SYM(_uhoh) /* 154*/
.long SYM(_uhoh) /* 155*/
.long SYM(_uhoh) /* 156*/
.long SYM(_uhoh) /* 157*/
.long SYM(_uhoh) /* 158*/
.long SYM(_uhoh) /* 159*/
.long SYM(_uhoh) /* 160*/
.long SYM(_uhoh) /* 161*/
.long SYM(_uhoh) /* 162*/
.long SYM(_uhoh) /* 163*/
.long SYM(_uhoh) /* 164*/
.long SYM(_uhoh) /* 165*/
.long SYM(_uhoh) /* 166*/
.long SYM(_uhoh) /* 167*/
.long SYM(_uhoh) /* 168*/
.long SYM(_uhoh) /* 169*/
.long SYM(_uhoh) /* 170*/
.long SYM(_uhoh) /* 171*/
.long SYM(_uhoh) /* 172*/
.long SYM(_uhoh) /* 173*/
.long SYM(_uhoh) /* 174*/
.long SYM(_uhoh) /* 175*/
.long SYM(_uhoh) /* 176*/
.long SYM(_uhoh) /* 177*/
.long SYM(_uhoh) /* 178*/
.long SYM(_uhoh) /* 179*/
.long SYM(_uhoh) /* 180*/
.long SYM(_uhoh) /* 181*/
.long SYM(_uhoh) /* 182*/
.long SYM(_uhoh) /* 183*/
.long SYM(_uhoh) /* 184*/
.long SYM(_uhoh) /* 185*/
.long SYM(_uhoh) /* 186*/
.long SYM(_uhoh) /* 187*/
.long SYM(_uhoh) /* 188*/
.long SYM(_uhoh) /* 189*/
.long SYM(_uhoh) /* 190*/
.long SYM(_uhoh) /* 191*/
.long SYM(_uhoh) /* 192*/
/* */
.long SYM(_uhoh) /* 193*/
.long SYM(_uhoh) /* 194*/
.long SYM(_uhoh) /* 195*/
.long SYM(_uhoh) /* 196*/
.long SYM(_uhoh) /* 197*/
.long SYM(_uhoh) /* 198*/
.long SYM(_uhoh) /* 199*/
.long SYM(_uhoh) /* 200*/
.long SYM(_uhoh) /* 201*/
.long SYM(_uhoh) /* 202*/
.long SYM(_uhoh) /* 203*/
.long SYM(_uhoh) /* 204*/
.long SYM(_uhoh) /* 205*/
.long SYM(_uhoh) /* 206*/
.long SYM(_uhoh) /* 207*/
.long SYM(_uhoh) /* 208*/
.long SYM(_uhoh) /* 209*/
.long SYM(_uhoh) /* 210*/
.long SYM(_uhoh) /* 211*/
.long SYM(_uhoh) /* 212*/
.long SYM(_uhoh) /* 213*/
.long SYM(_uhoh) /* 214*/
.long SYM(_uhoh) /* 215*/
.long SYM(_uhoh) /* 216*/
.long SYM(_uhoh) /* 217*/
.long SYM(_uhoh) /* 218*/
.long SYM(_uhoh) /* 219*/
.long SYM(_uhoh) /* 220*/
.long SYM(_uhoh) /* 221*/
.long SYM(_uhoh) /* 222*/
.long SYM(_uhoh) /* 223*/
.long SYM(_uhoh) /* 224*/
.long SYM(_uhoh) /* 225*/
.long SYM(_uhoh) /* 226*/
.long SYM(_uhoh) /* 227*/
.long SYM(_uhoh) /* 228*/
.long SYM(_uhoh) /* 229*/
.long SYM(_uhoh) /* 230*/
.long SYM(_uhoh) /* 231*/
.long SYM(_uhoh) /* 232*/
.long SYM(_uhoh) /* 233*/
.long SYM(_uhoh) /* 234*/
.long SYM(_uhoh) /* 235*/
.long SYM(_uhoh) /* 236*/
.long SYM(_uhoh) /* 237*/
.long SYM(_uhoh) /* 238*/
.long SYM(_uhoh) /* 239*/
.long SYM(_uhoh) /* 240*/
.long SYM(_uhoh) /* 241*/
.long SYM(_uhoh) /* 242*/
.long SYM(_uhoh) /* 243*/
.long SYM(_uhoh) /* 244*/
.long SYM(_uhoh) /* 245*/
.long SYM(_uhoh) /* 246*/
.long SYM(_uhoh) /* 247*/
.long SYM(_uhoh) /* 248*/
.long SYM(_uhoh) /* 249*/
.long SYM(_uhoh) /* 250*/
.long SYM(_uhoh) /* 251*/
.long SYM(_uhoh) /* 252*/
.long SYM(_uhoh) /* 253*/
.long SYM(_uhoh) /* 254*/
.long SYM(_uhoh) /* 255*/
/*
* We must write the flash configuration here.
This portion of RAM is shadowed
* by some flash registers, so we can't put code here!
*/
PUBLIC (_FLASH_CONFIGURATION_FIELD)
SYM(_FLASH_CONFIGURATION_FIELD):
_key_upper: .long 0x5a5a5a5a
_key_lower: .long 0x5a5a5a5a
_cfm_prot: .long 0x00000000
_cfm_sacc: .long 0x00000000
_cfm_dacc: .long 0x00000000
_cfm_msec: .long 0x80000000 //enable the KEYEN bit to bypass security in backdoor mode
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
/*
* Spurious Interrupt Handler
*/
.align 4
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1, SYM(_M68kSpuriousInterruptCount)
rte
/*
* Write VBR Register
*/
/*
.align 4
PUBLIC (_wr_vbr)
SYM(_wr_vbr):
move.l 4(sp), d0
movec d0, vbr
nop
rts
*/
/*
* Board startup
* Disable watchdog, interrupts
* Enable sram
*/
.align 4
PUBLIC (start)
SYM(start):
/* Mask off interupts */
move.w #0x2700, sr
/* Save off intial D0 and D1 to NOT scratched registers conforming to ABI C calling convention */
move.l d0,d5;
move.l d1,d6;
/* Initialize RAMBAR: locate SRAM and validate it */
move.l #RamBase, d7
add.l #0x21, d7
movec d7, %rambar
/* Locate Stack Pointer */
move.l #_StackInit, sp
/* Initialize FLASHBAR */
move.l #_FlashBase, d7
cmp.l #0x00000000, d7
bne _change_flashbar
add.l #0x61, d7
movec d7, %flashbar
_continue_startup:
/* Locate Stack Pointer */
// move.l #_StackInit, sp //is done automatically by the CPU
/*
* Remainder of the startup code is handled by C code
* This never returns
*/
jmp SYM(Init5225x)
_change_flashbar:
/*
* The following sequence is used to set FLASHBAR. Since we may
* be executing from Flash, we must put the routine into SRAM for
* execution and then jump back to Flash using the new address.
*
* The following instructions are coded into the SRAM:
*
* move.l #(__FLASH + 0x61),d0
* movec d0, FLASHBAR
* jmp _continue_startup
*
* An arbitrary SRAM address is chosen until the real address
* can be loaded.
*
* This routine is not necessary if the default Flash address
* (0x00000000) is used.
*
* If running in SRAM, change_flashbar should not be executed
*/
move.l #RamBase, a0
/* Code "move.l #(__FLASH + 0x61),d0" into SRAM */
move.w #0x203C, d0
move.w d0, (a0)+
move.l #_FlashBase, d0
add.l #0x61, d0
move.l d0, (a0)+
/* Code "movec d0,FLASHBAR" into SRAM */
move.l #0x4e7b0C04, d0
move.l d0, (a0)+
/* Code "jmp _continue_startup" into SRAM */
move.w #0x4EF9, d0
move.w d0, (a0)+
move.l #_continue_startup, d0
move.l d0, (a0)+
/* Jump to code segment in internal SRAM */
jmp RamBase
END_CODE
BEGIN_DATA_DCL
.align 4
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
PUBLIC (_d0_reset)
SYM (_d0_reset):
.long 0
PUBLIC (_d1_reset)
SYM (_d1_reset):
.long 0
END_DATA_DCL
END

2
c/src/lib/libbsp/m68k/mcf5235/Makefile.am
View File

@@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/mcf5235/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

387
c/src/lib/libbsp/m68k/mcf5235/start/start.S
View File

@@ -1,387 +0,0 @@
/*
* mcf5235 startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
#define SRAM_SIZE (64*1024)
#define DEFAULT_IPSBAR 0x40000000
BEGIN_CODE
#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4
PUBLIC (INTERRUPT_VECTOR)
SYM(INTERRUPT_VECTOR):
.long INITIAL_STACK | 0: Initial 'SSP'
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_spuriousInterrupt) | 64: User spurious handler
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
.long SYM(_uhoh) | 162:
.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
.long SYM(_uhoh) | 189:
.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
.long SYM(_uhoh) | 192:
.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
.long SYM(_uhoh) | 198:
.long SYM(_uhoh) | 199:
.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
.long SYM(_uhoh) | 203:
.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
.align 4
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/***************************************************************************
Function : start
Description : setup the internal SRAM for use and setup the INITIAL STACK ptr.
Also enable the internal peripherals
***************************************************************************/
.align 4
PUBLIC (start)
SYM(start):
move.w #0x0000,d0 | Turn off watchdog timer
move.w d0, (0x40140000)
move.l #0x01000000,d0 | Set system frequency to 150 MHz
move.l d0, (0x40120000)
move.w #0x2700,sr | Disable interrupts
move.l #__SRAMBASE+1,d0 | Enable the MCF5235 internal SRAM
movec d0,%rambar | ...so we have a stack
move.l #0x20000201, d0
move.l d0,(0x40000008) | set up 2nd RAMBAR to make 2nd port avail to FEC
move.l #__IPSBAR+1,d0 | Enable the MCF5235 internal peripherals
move.l d0,DEFAULT_IPSBAR
/*
* Remainder of the startup code is handled by C code
*/
jmp SYM(Init5235) | Start C code (which never returns)
/***************************************************************************
Function : CopyDataClearBSSAndStart
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
start C program. Assume that DATA and BSS sizes are multiples of 4.
***************************************************************************/
.align 4
PUBLIC (CopyDataClearBSSAndStart)
SYM(CopyDataClearBSSAndStart):
lea SYM(_data_dest_start),a0 | Get start of DATA in RAM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NODATACOPY | Yes, no copy necessary
lea SYM(_data_dest_end),a1 | Get end of DATA in RAM
bra.s DATACOPYLOOPTEST | Branch into copy loop
DATACOPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
DATACOPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s DATACOPYLOOP | No, skip
NODATACOPY:
/* Now, clear BSS */
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
/*
* Right : Now we're ready to boot RTEMS
*/
clrl d0 | Pass in null to all boot_card() params
movel d0,a7@- | command line
jsr SYM(boot_card) | Call C boot_card function to startup RTEMS
movel a7@+,d0
MULTI_TASK_EXIT:
nop
nop
trap #14
bra MULTI_TASK_EXIT
.align 2
END_CODE
BEGIN_DATA_DCL
.align 2
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END

2
c/src/lib/libbsp/m68k/mcf5329/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/mcf5329/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

379
c/src/lib/libbsp/m68k/mcf5329/start/start.S
View File

@@ -1,379 +0,0 @@
/*
* mcf52235 startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
.extern _StackInit
BEGIN_CODE
PUBLIC (_INTERRUPT_VECTOR)
SYM(_INTERRUPT_VECTOR):
.long _StackInit /* 00 Initial 'SSP' */
.long SYM(start) /* 01 Initial PC */
.long SYM(_uhoh) /* 02 Access Error */
.long SYM(_uhoh) /* 03 Address Error */
.long SYM(_uhoh) /* 04 Illegal Instruction */
.long SYM(_uhoh) /* 05 Divide by Zero */
.long SYM(_uhoh) /* 06 Reserved */
.long SYM(_uhoh) /* 07 Reserved */
.long SYM(_uhoh) /* 08 Privilege Violation */
.long SYM(_uhoh) /* 09 Trace */
.long SYM(_uhoh) /* 10 Unimplemented A-Line */
.long SYM(_uhoh) /* 11 Unimplemented F-Line */
.long SYM(_uhoh) /* 12 Debug Interrupt */
.long SYM(_uhoh) /* 13 Reserved */
.long SYM(_uhoh) /* 14 Format Error */
.long SYM(_uhoh) /* 15 Reserved */
.long SYM(_uhoh) /* 16 Reserved */
.long SYM(_uhoh) /* 17 Reserved */
.long SYM(_uhoh) /* 18 Reserved */
.long SYM(_uhoh) /* 19 Reserved */
.long SYM(_uhoh) /* 20 Reserved */
.long SYM(_uhoh) /* 21 Reserved */
.long SYM(_uhoh) /* 22 Reserved */
.long SYM(_uhoh) /* 23 Reserved */
.long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */
.long SYM(_uhoh) /* Reserved */
.long SYM(_uhoh) /* Reserved */
.long SYM(_uhoh) /* Reserved */
.long SYM(_uhoh) /* Reserved */
.long SYM(_uhoh) /* Reserved */
.long SYM(_uhoh) /* Reserved */
.long SYM(_uhoh) /* Reserved */
.long SYM(_uhoh) /* 32 TRAP #0 */
.long SYM(_uhoh) /* 33 TRAP #1 */
.long SYM(_uhoh) /* 34 TRAP #2 */
.long SYM(_uhoh) /* 35 TRAP #3 */
.long SYM(_uhoh) /* 36 TRAP #4 */
.long SYM(_uhoh) /* 37 TRAP #5 */
.long SYM(_uhoh) /* 38 TRAP #6 */
.long SYM(_uhoh) /* 39 TRAP #7 */
.long SYM(_uhoh) /* 40 TRAP #8 */
.long SYM(_uhoh) /* 41 TRAP #9 */
.long SYM(_uhoh) /* 42 TRAP #10 */
.long SYM(_uhoh) /* 43 TRAP #11 */
.long SYM(_uhoh) /* 44 TRAP #12 */
.long SYM(_uhoh) /* 45 TRAP #13 */
.long SYM(_uhoh) /* 46 TRAP #14 */
.long SYM(_uhoh) /* 47 TRAP #15 */
.long SYM(_uhoh) /* 48 Reserved */
.long SYM(_uhoh) /* 49 Reserved */
.long SYM(_uhoh) /* 50 Reserved */
.long SYM(_uhoh) /* 51 Reserved */
.long SYM(_uhoh) /* 52 Reserved */
.long SYM(_uhoh) /* 53 Reserved */
.long SYM(_uhoh) /* 54 Reserved */
.long SYM(_uhoh) /* 55 Reserved */
.long SYM(_uhoh) /* 56 Reserved */
.long SYM(_uhoh) /* 57 Reserved */
.long SYM(_uhoh) /* 58 Reserved */
.long SYM(_uhoh) /* 59 Reserved */
.long SYM(_uhoh) /* 60 Reserved */
.long SYM(_uhoh) /* 61 Reserved */
.long SYM(_uhoh) /* 62 Reserved */
.long SYM(_uhoh) /* 63 Reserved */
/* INTC0 */
.long SYM(_uhoh) /* 64*/
.long SYM(_uhoh) /* 65*/
.long SYM(_uhoh) /* 66*/
.long SYM(_uhoh) /* 67*/
.long SYM(_uhoh) /* 68*/
.long SYM(_uhoh) /* 69*/
.long SYM(_uhoh) /* 70*/
.long SYM(_uhoh) /* 71*/
.long SYM(_uhoh) /* 72*/
.long SYM(_uhoh) /* 73*/
.long SYM(_uhoh) /* 74*/
.long SYM(_uhoh) /* 75*/
.long SYM(_uhoh) /* 76*/
.long SYM(_uhoh) /* 77*/
.long SYM(_uhoh) /* 78*/
.long SYM(_uhoh) /* 79*/
.long SYM(_uhoh) /* 80*/
.long SYM(_uhoh) /* 81*/
.long SYM(_uhoh) /* 82*/
.long SYM(_uhoh) /* 83*/
.long SYM(_uhoh) /* 84*/
.long SYM(_uhoh) /* 85*/
.long SYM(_uhoh) /* 86*/
.long SYM(_uhoh) /* 87*/
.long SYM(_uhoh) /* 88*/
.long SYM(_uhoh) /* 89*/
.long SYM(_uhoh) /* 90*/
.long SYM(_uhoh) /* 91*/
.long SYM(_uhoh) /* 92*/
.long SYM(_uhoh) /* 93*/
.long SYM(_uhoh) /* 94*/
.long SYM(_uhoh) /* 95*/
.long SYM(_uhoh) /* 96*/
.long SYM(_uhoh) /* 97*/
.long SYM(_uhoh) /* 98*/
.long SYM(_uhoh) /* 99*/
.long SYM(_uhoh) /* 100*/
.long SYM(_uhoh) /* 101*/
.long SYM(_uhoh) /* 102*/
.long SYM(_uhoh) /* 103*/
.long SYM(_uhoh) /* 104*/
.long SYM(_uhoh) /* 105*/
.long SYM(_uhoh) /* 106*/
.long SYM(_uhoh) /* 107*/
.long SYM(_uhoh) /* 108*/
.long SYM(_uhoh) /* 109*/
.long SYM(_uhoh) /* 110*/
.long SYM(_uhoh) /* 111*/
.long SYM(_uhoh) /* 112*/
.long SYM(_uhoh) /* 113*/
.long SYM(_uhoh) /* 114*/
.long SYM(_uhoh) /* 115*/
.long SYM(_uhoh) /* 116*/
.long SYM(_uhoh) /* 117*/
.long SYM(_uhoh) /* 118*/
.long SYM(_uhoh) /* 119*/
.long SYM(_uhoh) /* 120*/
.long SYM(_uhoh) /* 121*/
.long SYM(_uhoh) /* 122*/
.long SYM(_uhoh) /* 123*/
.long SYM(_uhoh) /* 124*/
.long SYM(_uhoh) /* 125*/
.long SYM(_uhoh) /* 126*/
.long SYM(_uhoh) /* 127*/
/* INTC1 */
.long SYM(_uhoh) /* 128*/
.long SYM(_uhoh) /* 129*/
.long SYM(_uhoh) /* 130*/
.long SYM(_uhoh) /* 131*/
.long SYM(_uhoh) /* 132*/
.long SYM(_uhoh) /* 133*/
.long SYM(_uhoh) /* 134*/
.long SYM(_uhoh) /* 135*/
.long SYM(_uhoh) /* 136*/
.long SYM(_uhoh) /* 137*/
.long SYM(_uhoh) /* 138*/
.long SYM(_uhoh) /* 139*/
.long SYM(_uhoh) /* 140*/
.long SYM(_uhoh) /* 141*/
.long SYM(_uhoh) /* 142*/
.long SYM(_uhoh) /* 143*/
.long SYM(_uhoh) /* 144*/
.long SYM(_uhoh) /* 145*/
.long SYM(_uhoh) /* 146*/
.long SYM(_uhoh) /* 147*/
.long SYM(_uhoh) /* 148*/
.long SYM(_uhoh) /* 149*/
.long SYM(_uhoh) /* 150*/
.long SYM(_uhoh) /* 151*/
.long SYM(_uhoh) /* 152*/
.long SYM(_uhoh) /* 153*/
.long SYM(_uhoh) /* 154*/
.long SYM(_uhoh) /* 155*/
.long SYM(_uhoh) /* 156*/
.long SYM(_uhoh) /* 157*/
.long SYM(_uhoh) /* 158*/
.long SYM(_uhoh) /* 159*/
.long SYM(_uhoh) /* 160*/
.long SYM(_uhoh) /* 161*/
.long SYM(_uhoh) /* 162*/
.long SYM(_uhoh) /* 163*/
.long SYM(_uhoh) /* 164*/
.long SYM(_uhoh) /* 165*/
.long SYM(_uhoh) /* 166*/
.long SYM(_uhoh) /* 167*/
.long SYM(_uhoh) /* 168*/
.long SYM(_uhoh) /* 169*/
.long SYM(_uhoh) /* 170*/
.long SYM(_uhoh) /* 171*/
.long SYM(_uhoh) /* 172*/
.long SYM(_uhoh) /* 173*/
.long SYM(_uhoh) /* 174*/
.long SYM(_uhoh) /* 175*/
.long SYM(_uhoh) /* 176*/
.long SYM(_uhoh) /* 177*/
.long SYM(_uhoh) /* 178*/
.long SYM(_uhoh) /* 179*/
.long SYM(_uhoh) /* 180*/
.long SYM(_uhoh) /* 181*/
.long SYM(_uhoh) /* 182*/
.long SYM(_uhoh) /* 183*/
.long SYM(_uhoh) /* 184*/
.long SYM(_uhoh) /* 185*/
.long SYM(_uhoh) /* 186*/
.long SYM(_uhoh) /* 187*/
.long SYM(_uhoh) /* 188*/
.long SYM(_uhoh) /* 189*/
.long SYM(_uhoh) /* 190*/
.long SYM(_uhoh) /* 191*/
.long SYM(_uhoh) /* 192*/
/* */
.long SYM(_uhoh) /* 193*/
.long SYM(_uhoh) /* 194*/
.long SYM(_uhoh) /* 195*/
.long SYM(_uhoh) /* 196*/
.long SYM(_uhoh) /* 197*/
.long SYM(_uhoh) /* 198*/
.long SYM(_uhoh) /* 199*/
.long SYM(_uhoh) /* 200*/
.long SYM(_uhoh) /* 201*/
.long SYM(_uhoh) /* 202*/
.long SYM(_uhoh) /* 203*/
.long SYM(_uhoh) /* 204*/
.long SYM(_uhoh) /* 205*/
.long SYM(_uhoh) /* 206*/
.long SYM(_uhoh) /* 207*/
.long SYM(_uhoh) /* 208*/
.long SYM(_uhoh) /* 209*/
.long SYM(_uhoh) /* 210*/
.long SYM(_uhoh) /* 211*/
.long SYM(_uhoh) /* 212*/
.long SYM(_uhoh) /* 213*/
.long SYM(_uhoh) /* 214*/
.long SYM(_uhoh) /* 215*/
.long SYM(_uhoh) /* 216*/
.long SYM(_uhoh) /* 217*/
.long SYM(_uhoh) /* 218*/
.long SYM(_uhoh) /* 219*/
.long SYM(_uhoh) /* 220*/
.long SYM(_uhoh) /* 221*/
.long SYM(_uhoh) /* 222*/
.long SYM(_uhoh) /* 223*/
.long SYM(_uhoh) /* 224*/
.long SYM(_uhoh) /* 225*/
.long SYM(_uhoh) /* 226*/
.long SYM(_uhoh) /* 227*/
.long SYM(_uhoh) /* 228*/
.long SYM(_uhoh) /* 229*/
.long SYM(_uhoh) /* 230*/
.long SYM(_uhoh) /* 231*/
.long SYM(_uhoh) /* 232*/
.long SYM(_uhoh) /* 233*/
.long SYM(_uhoh) /* 234*/
.long SYM(_uhoh) /* 235*/
.long SYM(_uhoh) /* 236*/
.long SYM(_uhoh) /* 237*/
.long SYM(_uhoh) /* 238*/
.long SYM(_uhoh) /* 239*/
.long SYM(_uhoh) /* 240*/
.long SYM(_uhoh) /* 241*/
.long SYM(_uhoh) /* 242*/
.long SYM(_uhoh) /* 243*/
.long SYM(_uhoh) /* 244*/
.long SYM(_uhoh) /* 245*/
.long SYM(_uhoh) /* 246*/
.long SYM(_uhoh) /* 247*/
.long SYM(_uhoh) /* 248*/
.long SYM(_uhoh) /* 249*/
.long SYM(_uhoh) /* 250*/
.long SYM(_uhoh) /* 251*/
.long SYM(_uhoh) /* 252*/
.long SYM(_uhoh) /* 253*/
.long SYM(_uhoh) /* 254*/
.long SYM(_uhoh) /* 255*/
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
/*
* Spurious Interrupt Handler
*/
.align 4
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1, SYM(_M68kSpuriousInterruptCount)
rte
/*
* Write VBR Register
*/
.align 4
PUBLIC (_wr_vbr)
SYM(_wr_vbr):
move.l 4(sp), d0
movec d0, vbr
nop
rts
/*
* Board startup
* Disable watchdog, interrupts
* Enable sram
*/
.align 4
PUBLIC (start)
SYM(start):
/* Mask off interupts */
move.w #0x2700,sr
/* Save off reset values of D0 and D1 */
move.l d0,d6
move.l d1,d7
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #_CoreSRamBase,d0
add.l #0x221,d0
movec d0,%rambar
/* Save off intial D0 and D1 to RAM */
move.l d6, SYM(_d0_reset)
move.l d7, SYM(_d1_reset)
/* Locate Stack Pointer */
move.l #_StackInit,sp
/*
* Remainder of the startup code is handled by C code
* This never returns
*/
jmp SYM(Init5329)
END_CODE
BEGIN_DATA_DCL
.align 4
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
PUBLIC (_d0_reset)
SYM (_d0_reset):
.long 0
PUBLIC (_d1_reset)
SYM (_d1_reset):
.long 0
END_DATA_DCL
END

2
c/src/lib/libbsp/m68k/mrm332/Makefile.am
View File

@@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/mrm332/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

71
c/src/lib/libbsp/m68k/mrm332/start/start.S
View File

@@ -1,71 +0,0 @@
/**
* @file
*
* MRM332 Assembly Start Up Code
*/
/*
* COPYRIGHT (c) 2000.
* Matt Cross <profesor@gweep.net>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#include "mrm332.h"
#include <rtems/asm.h>
#include <rtems/m68k/sim.h>
BEGIN_CODE
/* Put the header necessary for the modified CPU32bug to automatically
start up rtems: */
#if 1
.long 0xbeefbeef ;
#endif
.long 0 ;
.long start ;
.global start
start:
oriw #0x0700,sr /* Mask off interupts */
// Set VBR to CPU32Bug vector table address
movel #0x0,d0 /* Use the initial vectors until we get going */
movecl d0,vbr
movel #end, d0 /* Next 3 instructions set stack pointer */
addl #_StackSize,d0 /* sp = end + _StackSize from linker script */
movel d0,sp
movel d0,a6
/* include in ram_init.S */
/*
* Initalize the SIM module.
* The stack pointer is not usable until the RAM chip select lines
* are configured. The following code must remain inline.
*/
/* Module Configuration Register */
/* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
/* SIMCR etc and SAM macro all defined in sim.h found at */
/* /cpukit/score/cpu/m68k/rtems/m68k/sim.h */
/* The code below does the following: */
/* - Sets Freeze Software Enable */
/* - Turns off Show Cycle Enable */
/* - Sets the location of SIM module mapping */
/* - Sets the SIM Interrupt Arbitration Field */
lea SIMCR, a0
movew #FRZSW,d0
oriw #SAM(0,8,SHEN),d0
oriw #(MM*SIM_MM),d0
oriw #SAM(SIM_IARB,0,IARB),d0
movew d0, a0@
jsr start_c /* Jump to the C startup code */
END_CODE

2
c/src/lib/libbsp/m68k/mvme147/Makefile.am
View File

@@ -10,7 +10,7 @@ noinst_PROGRAMS =
## Zilog component header files
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/m68k/mvme147s/Makefile.am
View File

@@ -10,7 +10,7 @@ noinst_PROGRAMS =
## Zilog component header files
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/m68k/mvme162/Makefile.am
View File

@@ -9,7 +9,7 @@ noinst_PROGRAMS =
## Zilog component header files
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

2
c/src/lib/libbsp/m68k/mvme167/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

147
c/src/lib/libbsp/m68k/shared/start/start.S
View File

@@ -1,147 +0,0 @@
/* entry.s
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
#if (M68K_COLDFIRE_ARCH == 0) /* All ColdFire BSPs must provide their own start vector */
BEGIN_CODE
| Default entry points for:
PUBLIC (start) | GNU
PUBLIC (M68Kvec) | Vector Table
SYM (start):
SYM (M68Kvec): | standard location for vectors
nop | for linkers with problem
| location zero
jmp SYM (start_around)
/*
* We can use the following space as our vector table
* if the CPU has a VBR or we can save vector table in it
* if the CPU does not.
*/
.space 4088 | to avoid initial intr stack
| from 135BUG on MVME13?
| and start code at 0x4000
SYM (vectors):
.space 1016 | reserve space for rest of vectors
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
SYM (lowintstack):
.space 4092 | reserve for interrupt stack
SYM (hiintstack):
.space 4 | end of interrupt stack
#endif
PUBLIC (start_around)
SYM (start_around):
move.w sr, SYM (initial_sr)
oriw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!!
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
movec isp,a0
move.l a0, SYM (initial_isp)
movec usp,a0
move.l a0, SYM (initial_usp)
movec msp,a0
move.l a0, SYM (initial_msp)
#else
move.l a7, SYM (initial_msp)
#endif
|
| zero out uninitialized data area
|
zerobss:
moveal # SYM (bsp_section_bss_end),a0 | find end of .bss
moveal # SYM (bsp_section_bss_begin),a1 | find beginning of .bss
movel #0,d0
loop: movel #0,a1@+ | to zero out uninitialized
cmpal a0,a1
jlt loop | loop until _end reached
movel # SYM (_stack_init),d0 | d0 = stop of stack
movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!!
movel d0,a7 | set master stack pointer
movel d0,a6 | set base pointer
/*
* RTEMS should maintain a separate interrupt stack on CPUs
* without one in hardware. This is currently not supported
* on versions of the m68k without a HW intr stack.
*/
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
lea SYM (hiintstack),a0 | a0 = high end of intr stack
movec a0,isp | set interrupt stack
#endif
movel #0,a7@- | push command line
jsr SYM (boot_card)
addl #12,a7
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
move.l SYM (initial_isp),a0
movec a0,isp
move.l SYM (initial_usp),a0
movec a0,usp
move.l SYM (initial_msp),a0
movec a0,msp
#else
movea.l SYM (initial_msp),a7
#endif
move.w SYM (initial_sr),sr
rts
END_CODE
BEGIN_DATA
PUBLIC (start_frame)
SYM (start_frame):
.space 4,0
END_DATA
BEGIN_BSS
PUBLIC (initial_isp)
SYM (initial_isp):
.space 4
PUBLIC (initial_msp)
SYM (initial_msp):
.space 4
PUBLIC (initial_usp)
SYM (initial_usp):
.space 4
PUBLIC (initial_sr)
SYM (initial_sr):
.space 2
.align 16
PUBLIC (starting_stack)
SYM (starting_stack):
.space 0x1000
PUBLIC (_stack_init)
SYM (_stack_init):
END_DATA
#endif
END

2
c/src/lib/libbsp/m68k/uC5282/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/m68k/uC5282/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

403
c/src/lib/libbsp/m68k/uC5282/start/start.S
View File

@@ -1,403 +0,0 @@
/*
* uC5282 startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
#define SRAM_SIZE (64*1024)
#define DEFAULT_IPSBAR 0x40000000
BEGIN_CODE
/***************************************************************************
Function : Entry
Description : Entry point to the system. In a raw system we would have
put the initial stack pointer as the first 4 bytes. Instead we have to
provide a real instruction at the first location since we might be getting
started by dBUG after downloading from TFTP or FLASH. Hack in an
'initial stack pointer' that actually is a jump to the start address!
***************************************************************************/
Entry:
nop ; jmp SYM(start) | 0: Initial 'SSP' 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_spuriousInterrupt) | 64: User spurious handler
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
.long SYM(_uhoh) | 162:
.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
.long SYM(_uhoh) | 189:
.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
.long SYM(_uhoh) | 192:
.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
.long SYM(_uhoh) | 198:
.long SYM(_uhoh) | 199:
.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
.long SYM(_uhoh) | 203:
.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
.align 4
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
.align 4
PUBLIC (start)
SYM(start):
move.w #0x2700,sr | Disable interrupts
/*
* If we're being started by the debugger, and the debugger has
* moved the IPSBAR, we're doomed........
*/
move.l #__IPSBAR+1,d0 | Enable the MCF5282 internal peripherals
move.l d0,DEFAULT_IPSBAR
move.l #__SRAMBASE+0x201,d0 | Enable the MCF5282 internal SRAM
movec d0,%rambar | CPU-space copy of RAMBAR
move.l d0,DEFAULT_IPSBAR+8 | Memory-space copy of RAMBAR
move.l #__SRAMBASE+SRAM_SIZE-4,sp | Overwrite the fake stack pointer
/*
* Copy the vector table to address 0 (VBR must be 0 mod 2^20)
* Leave the dBUG vectors (0-63) alone
*/
lea.l (64*4)+Entry,a0
lea.l (64*4),a1
move.l #(256-64)-1,d0
vectcpy:
move.l a0@+,a1@+ | Copy the vector table
sub.l #1,d0
bne.s vectcpy
/*
* Remainder of the startup code is handled by C code
*/
jmp SYM(Init5282) | Start C code (which never returns)
/***************************************************************************
Function : CopyDataClearBSSAndStart
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
start C program. Assume that DATA and BSS sizes are multiples of 4.
***************************************************************************/
.align 4
PUBLIC (CopyDataClearBSSAndStart)
SYM(CopyDataClearBSSAndStart):
lea SYM(_data_dest_start),a0 | Get start of DATA in RAM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
sub.l #SYM(_header_offset),a2 | Change source by the amount of the header offset
cmpl a0,a2 | Are they the same?
beq.s NODATACOPY | Yes, no copy necessary
lea SYM(_data_dest_end),a1 | Get end of DATA in RAM
bra.s DATACOPYLOOPTEST | Branch into copy loop
DATACOPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
DATACOPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s DATACOPYLOOP | No, skip
NODATACOPY:
/* Now, clear BSS */
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
/*
* Right : Now we're ready to boot RTEMS
*/
clrl d0 | Pass in null to all boot_card() params
movel d0,a7@- | command line
jsr SYM(boot_card) | Call C boot_card function to startup RTEMS
movel a7@+,d0
MULTI_TASK_EXIT:
nop
nop
trap #14
bra MULTI_TASK_EXIT
END_CODE
.align 2
BEGIN_DATA_DCL
.align 2
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END

2
c/src/lib/libbsp/mips/csb350/Makefile.am
View File

@@ -9,7 +9,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/mips/csb350/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

122
c/src/lib/libbsp/mips/csb350/start/start.S
View File

@@ -1,122 +0,0 @@
/*
* start.S -- startup file for Cogent CSB350 Au1100 based board
*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#include <rtems/asm.h>
#include <bsp/regs.h>
.text
.align 2
/* Without the following nop, GDB thinks _start is a data variable.
* This is probably a bug in GDB in handling a symbol that is at the
* start of the .text section.
*/
nop
.globl _start
.ent _start
_start:
.set noreorder
/* Get the address of start into $5 in a position independent
* fashion. This lets us know whether we have been relocated or not.
*/
$LF1 = . + 8
bal $LF1
nop
_branch:
move $5, $31 /* $5 == where are we */
li $6, 0x8800000c /* $6 == where we want to be */
li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
mtc0 zero, C0_CAUSE
1:
li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
2:
/* Fix high bits, if any, of the PC so that exception handling
doesn't get confused. */
la v0, 3f
jr v0
nop
3:
la gp, _gp /* set the global data pointer */
.end _start
/*
* zero out the bss section.
*/
.globl zerobss
.ent zerobss
zerobss:
la v0, _fbss
la v1, _end
3:
sw zero,0(v0)
bltu v0,v1,3b
addiu v0,v0,4 /* executed in delay slot */
la t0, _stack_init /* initialize stack so we */
/* We must subtract 24 bytes for the 3 8 byte arguments to main, in
case main wants to write them back to the stack. The caller is
supposed to allocate stack space for parameters in registers in
the old MIPS ABIs. We must do this even though we aren't passing
arguments, because main might be declared to have them.
Some ports need a larger alignment for the stack, so we subtract
32, which satisifes the stack for the arguments and keeps the
stack pointer better aligned. */
subu t0,t0,32
move sp,t0 /* set stack pointer */
.end zerobss
.globl exit .text
.globl init
.ent init
init:
move a0,zero /* set command line to 0 */
jal boot_card /* call the program start function */
nop
/* fall through to the "exit" routine */
jal _sys_exit /* call libc exit to run the G++ */
/* destructors */
move a0,v0 /* pass through the exit code */
.end init
/*
* _sys_exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run. NOTE: This is
* the only other routine we provide in the crt0.o object, since
* it may be tied to the "_start" routine. It also allows
* executables that contain a complete world to be linked with
* just the crt0.o object.
*/
.globl _sys_exit
.ent _sys_exit
_sys_exit:
7:
#ifdef GCRT0
jal _mcleanup
nop
#endif
/* break inst. can cope with 0xfffff, but GAS limits the range: */
break 1023
nop
b 7b /* but loop back just in-case */
nop
.end _sys_exit
/* EOF crt0.S */

2
c/src/lib/libbsp/mips/hurricane/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
#isr
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/mips/hurricane/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

339
c/src/lib/libbsp/mips/hurricane/start/start.S
View File

@@ -1,339 +0,0 @@
/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
*/
/*************************************************************************
**
** Copyright 1991-95 Integrated Device Technology, Inc.
** All Rights Reserved
**
**************************************************************************/
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#include <rtems/asm.h>
#include <bsp.h>
#if 0
.extern _fdata,4 /* this is defined by the linker */
.extern _edata,4 /* this is defined by the linker */
.extern _idata,4 /* this is defined by the linker */
#endif
.extern _fbss,4 /* this is defined by the linker */
.extern end,4 /* this is defined by the linker */
.lcomm sim_mem_cfg_struct,12
.text
/* For the V3 Eval board, we can safely assume that we have
at least 16 megabytes of RAM */
#define HARD_CODED_MEM_SIZE 0x1000000
#define TMP_STKSIZE 1024
/*
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
*/
#define P_STACKSIZE 0x2000 /* sets stack size to 8k */
/**************************************************************************
**
** start - Typical standalone start up code required for R3000/R4000
**
**
** 1) Initialize the STATUS Register
** a) Clear parity error bit
** b) Set co_processor 1 usable bit ON
** c) Clear all IntMask Enables
** d) Set kernel/disabled mode
** 2) Initialize Cause Register
** a) clear software interrupt bits
** 3) Determine FPU installed or not
** if not, clear CoProcessor 1 usable bit
** 4) Clear bss area
** 5) MUST allocate temporary stack until memory size determined
** It MUST be uncached to prevent overwriting when caches are cleared
** 6) Install exception handlers
** 7) Determine memory and cache sizes
** 8) Establish permanent stack (cached or uncached as defined by bss)
** 9) Flush Instruction and Data caches
** 10) If there is a Translation Lookaside Buffer, Clear the TLB
** 11) Execute initialization code if the IDT/c library is to be used
**
** 12) Jump to user's "main()" (boot_card() for RTEMS)
** 13) Jump to promexit
**
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** This is used to mark code specific to R3xxx or R4xxx processors.
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** when compiling with IDT/C6.x
**
***************************************************************************/
FRAME(start,sp,0,ra)
.set noreorder
#if __mips_fpr == 64
li v0,SR_CU1|SR_FR|SR_DE /* initally clear ERL, enable FPU with 64 bit regs, disable cache errors */
#else
li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPU with 32 bit regs, disable cache errors */
#endif
mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */
nop
mtc0 zero,C0_CAUSE /* clear software interrupts */
nop
la t0,0xBE200000 /* on Hurricane board, enable interrupt output signal from UART ch. B */
li t1,0x8 /* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */
sw t1,0x10(t0)
li v0,CFG_C_NONCOHERENT # initialise default cache mode
mtc0 v0,C0_CONFIG
/*
** check to see if an fpu is really plugged in
*/
li t3,0xaaaa5555 /* put a's and 5's in t3 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 zero,fp1 /* try to write zero in fp */
mfc1 t0,fp0
mfc1 t1,fp1
nop
bne t0,t3,1f /* branch if no match */
nop
bne t1,zero,1f /* double check for positive id */
nop
/* We have a FPU. clear fcsr */
ctc1 zero, fcr31
j 2f /* status register already correct */
nop
1:
li v0,SR_DE /* clear ERL and disable FPA */
mtc0 v0, C0_SR /* reset status register */
2:
la gp, _gp
#if 0
/* Initialize data sections from "rom" copy */
la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */
la t1,_fdata /* start of initialized data section */
la t2,_edata /* end of initialized data section */
3:
lw t3,0(t0)
sw t3,0(t1)
addiu t1,t1,4
bne t1,t2,3b
addiu t0,t0,4
#endif
/* clear bss before using it */
la v0,_fbss /* start of bss */
la v1,end /* end of bss */
4: sw zero,0(v0)
bltu v0,v1,4b
add v0,4
/************************************************************************
**
** Temporary Stack - needed to handle stack saves until
** memory size is determined and permanent stack set
**
** MUST be uncached to avoid confusion at cache
** switching during memory sizing
**
*************************************************************************/
/* For MIPS 3, we need to be sure that the stack is aligned on a
* double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 11f /* Last three bits Zero, already aligned */
nop
add v0, 4
11:
or v0, K1BASE /* switch to uncached */
add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
sub v1, v1, (4*4) /* overhead */
move sp, v1 /* set sp to top of stack */
4: sw zero, 0(v0)
bltu v0, v1, 4b /* clear out temp stack */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
/* nop */ /* MUST do before memory probes */
/* Force processor into uncached space during memory/cache probes */
la v0, 5f
li v1, K1BASE
or v0, v1
j v0
nop
5:
li a0, HARD_CODED_MEM_SIZE /* Set memory size global */
jal set_memory_size
nop
la a0, sim_mem_cfg_struct
jal get_mem_conf /* Make call to get mem size */
nop
la a0, sim_mem_cfg_struct
lw a0, 0(a0) /* Get memory size from struct */
jal config_cache /* determine size of D & I caches */
nop
move v0, a0 /* mem_size */
/* For MIPS 3, we need to be sure that the stack (and hence v0
* here) is aligned on a double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 12f /* Last three bits Zero, already aligned */
nop
subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/
12:
/**************************************************************************
**
** Permanent Stack - now know top of memory, put permanent stack there
**
***************************************************************************/
la t2, _fbss /* cache mode as linked */
and t2, 0xF0000000 /* isolate segment */
la t1, 6f
j t1 /* back to original cache mode */
nop
6:
or v0, t2 /* stack back to original cache mode */
addiu v0,v0,-16 /* overhead */
move sp, v0 /* now replace count w top of memory */
move v1, v0
subu v1, P_STACKSIZE /* clear requested stack size */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
bltu v1,v0,7b
add v1, 4
.set reorder
/* FIX THIS - This corrupts memory spaces */
/* jal flush_cache_nowrite */ /* flush Data & Instruction caches */
/* jal mon_flush_cache */
/**************************************************************************
**
** If this chip supports a Translation Lookaside Buffer, clear it
**
***************************************************************************/
.set noreorder
mfc0 t1, C0_SR /* look at Status Register */
nop
.set reorder
jal init_tlb /* clear the tlb */
/* Force processor into cached instruction space for rest of initialization */
#if 0
la t0, 1f
li t1, K0BASE /* force into cached space */
or t0, t1
j t0
nop
1:
#endif
/************************************************************************
**
** Initialization required if using IDT/c or libc.a, standard C Lib
**
** can SKIP if not necessary for application
**
************************************************************************/
8:
/* FIX THIS - Need the pmon equivalent
jal idtsim_init_sbrk
jal idtsim_init_file
*/
/*********************** END I/O initialization **********************/
move a0,zero /* Set command line passed to main */
jal boot_card
nop
# jump to the "exit" routine
jal idtsim__exit
move a0,v0 # pass through the exit code
# FIX THIS - Need the pmon equivalent
# jal idtsim_promexit
1:
beq zero,zero,1b
nop
ENDFRAME(start)
/*
* _sys_exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run. NOTE: This is
* the only other routine we provide in the crt0.o object, since
* it may be tied to the "_start" routine. It also allows
* executables that contain a complete world to be linked with
* just the crt0.o object.
*/
FRAME(_sys_exit,sp,0,ra)
break 1023
nop
13:
b 13b # but loop back just in-case
nop
ENDFRAME(_sys_exit)
.globl __sizemem
.ent __sizemem
__sizemem:
li v0,HARD_CODED_MEM_SIZE
j ra
nop
.end __sizemem

2
c/src/lib/libbsp/mips/jmr3904/Makefile.am
View File

@@ -8,7 +8,7 @@ dist_project_lib_DATA = startup/bsp_specs
#isr
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/mips/jmr3904/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

196
c/src/lib/libbsp/mips/jmr3904/start/start.S
View File

@@ -1,196 +0,0 @@
/*
* start.S -- startup file for JMR3904 BSP based upon crt0.S from
* newlib-1.8.2/libgloss/mips and adapted for RTEMS.
*
* crt0.S -- startup file for MIPS.
*
* Copyright (c) 1995, 1996, 1997 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <rtems/asm.h>
#include <bsp/regs.h>
#ifdef __mips16
/* This file contains 32 bit assembly code. */
.set nomips16
#endif
/* This is for referencing addresses that are not in the .sdata or
.sbss section under embedded-pic, or before we've set up gp. */
#ifdef __mips_embedded_pic
# ifdef __mips64
# define LA(t,x) la t,x-PICBASE ; daddu t,s0,t
# else
# define LA(t,x) la t,x-PICBASE ; addu t,s0,t
# endif
#else /* __mips_embedded_pic */
# define LA(t,x) la t,x
#endif /* __mips_embedded_pic */
.text
.align 2
/* Without the following nop, GDB thinks _start is a data variable.
* This is probably a bug in GDB in handling a symbol that is at the
* start of the .text section.
*/
nop
.globl _start
.ent _start
_start:
.set noreorder
/* Get the address of start into $5 in a position independent fashion.
** This lets us know whether we have been relocated or not.
*/
$LF1 = . + 8
bal $LF1
nop
_branch:
move $5, $31 # $5 == where are we
li $6, 0x8800000c # $6 == where we want to be
/* #la $6,_branch */
beq $5, $6, _start_in_ram
nop
/* relocate the code from EEPROM to RAM */
la $7, _edata
relocate:
lw $8, ($5) # $8 = *EEPROM
addu $5, $5, 4 # EEPROM++
sw $8, ($6) # *RAM = $8
addu $6, $6, 4 # RAM++
bne $6, $7, relocate # copied all the way to edata?
nop
la $6, _start_in_ram
jr $6
nop
.end _start
.globl _start_in_ram
.ent _start_in_ram
_start_in_ram:
nop
#ifdef __mips_embedded_pic
PICBASE = .+8
bal PICBASE
nop
move s0,$31
#endif
li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
mtc0 zero, C0_CAUSE
/* Check for FPU presence */
#ifndef __mips_soft_float
/* This doesn't work if there is no FPU. We get illegal instruction
exceptions. */
li t2,0xAAAA5555
mtc1 t2,fp0 /* write to FPR 0 */
mtc1 zero,fp1 /* write to FPR 1 */
mfc1 t0,fp0
mfc1 t1,fp1
nop
bne t0,t2,1f /* check for match */
nop
bne t1,zero,1f /* double check */
nop
#ifndef __mips64 /* Clear the FR bit */
li v0, SR_CU1|SR_PE|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
#endif
j 2f
nop
#endif
1:
li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
2:
/* Fix high bits, if any, of the PC so that exception handling
doesn't get confused. */
LA (v0, 3f)
jr v0
nop
3:
LA (gp, _gp) # set the global data pointer
.end _start_in_ram
/*
* zero out the bss section.
*/
.globl zerobss
.ent zerobss
zerobss:
LA (v0, _fbss)
LA (v1, _end)
3:
sw zero,0(v0)
bltu v0,v1,3b
addiu v0,v0,4 # executed in delay slot
la t0, _stack_init # initialize stack so we
/* We must subtract 24 bytes for the 3 8 byte arguments to main, in
case main wants to write them back to the stack. The caller is
supposed to allocate stack space for parameters in registers in
the old MIPS ABIs. We must do this even though we aren't passing
arguments, because main might be declared to have them.
Some ports need a larger alignment for the stack, so we subtract
32, which satisifes the stack for the arguments and keeps the
stack pointer better aligned. */
subu t0,t0,32
move sp,t0 # set stack pointer
.end zerobss
.globl exit .text
.globl init
.ent init
init:
move a0,zero # set command line to 0
jal boot_card # call the program start function
nop
/* fall through to the "exit" routine */
jal _sys_exit /* call libc exit to run the G++ */
/* destructors */
move a0,v0 /* pass through the exit code */
.end init
/*
* _sys_exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run. NOTE: This is
* the only other routine we provide in the crt0.o object, since
* it may be tied to the "_start" routine. It also allows
* executables that contain a complete world to be linked with
* just the crt0.o object.
*/
.globl bsp_reset
bsp_reset:
.globl _sys_exit
.ent _sys_exit
_sys_exit:
7:
#ifdef GCRT0
jal _mcleanup
nop
#endif
/* break instruction can cope with 0xfffff, but GAS limits the range: */
break 1023
nop
b 7b # but loop back just in-case
nop
.end _sys_exit
/* EOF crt0.S */

2
c/src/lib/libbsp/mips/malta/Makefile.am
View File

@@ -13,7 +13,7 @@ dist_project_lib_DATA = startup/bsp_specs
#irq
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/mips/malta/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

221
c/src/lib/libbsp/mips/malta/start/start.S
View File

@@ -1,221 +0,0 @@
/*
* start.S -- startup file for JMR3904 BSP based upon crt0.S from
* newlib-1.8.2/libgloss/mips and adapted for RTEMS.
*
* crt0.S -- startup file for MIPS.
*
* Copyright (c) 1995, 1996, 1997 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <rtems/asm.h>
#include <bsp/regs.h>
#include <bsp.h>
#ifdef __mips16
/* This file contains 32 bit assembly code. */
.set nomips16
#endif
/* This is for referencing addresses that are not in the .sdata or
.sbss section under embedded-pic, or before we've set up gp. */
#ifdef __mips_embedded_pic
# ifdef __mips64
# define LA(t,x) la t,x-PICBASE ; daddu t,s0,t
# else
# define LA(t,x) la t,x-PICBASE ; addu t,s0,t
# endif
#else /* __mips_embedded_pic */
# define LA(t,x) la t,x
#endif /* __mips_embedded_pic */
.text
.align 2
/* Without the following nop, GDB thinks _start is a data variable.
* This is probably a bug in GDB in handling a symbol that is at the
* start of the .text section.
*/
nop
nop
nop
nop
nop
nop
nop
nop
nop
.globl _start
.ent _start
_start:
nop
nop
nop
nop
nop
nop
nop
nop
.set noreorder
/* Get the address of start into $5 in a position independent fashion.
** This lets us know whether we have been relocated or not.
*/
$LF1 = . + 8
bal $LF1
nop
_branch:
#if 0
move $5, $31 # $5 == where are we
li $6, 0x8800000c # $6 == where we want to be
/* #la $6,_branch */
beq $5, $6, _start_in_ram
nop
/* relocate the code from EEPROM to RAM */
la $7, _edata
relocate:
nop
lw $8, ($5) # $8 = *EEPROM
addu $5, $5, 4 # EEPROM++
sw $8, ($6) # *RAM = $8
addu $6, $6, 4 # RAM++
bne $6, $7, relocate # copied all the way to edata?
nop
la $6, _start_in_ram
jr $6
nop
.end _start
.globl _start_in_ram
.ent _start_in_ram
#endif
_start_in_ram:
nop
#if 0
#ifdef __mips_embedded_pic
PICBASE = .+8
bal PICBASE
nop
move s0,$31
#endif
#endif
li v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
mtc0 zero, C0_CAUSE
#if 0
/* Check for FPU presence */
#ifndef __mips_soft_float
/* This doesn't work if there is no FPU. We get illegal instruction
exceptions. */
li t2,0xAAAA5555
mtc1 t2,fp0 /* write to FPR 0 */
mtc1 zero,fp1 /* write to FPR 1 */
mfc1 t0,fp0
mfc1 t1,fp1
nop
bne t0,t2,1f /* check for match */
nop
bne t1,zero,1f /* double check */
nop
#ifndef __mips64 /* Clear the FR bit */
li v0, SR_CU1|SR_PE|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
#endif
j 2f
nop
#endif
#endif
1:
li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
2:
/* Fix high bits, if any, of the PC so that exception handling
doesn't get confused. */
LA (v0, 3f)
jr v0
nop
3:
LA (gp, _gp) # set the global data pointer
#if 0
.end _start_in_ram
#else
.end _start
#endif
/*
* zero out the bss section.
*/
.globl zerobss
.ent zerobss
zerobss:
LA (v0, _fbss)
LA (v1, _end)
3:
sw zero,0(v0)
bltu v0,v1,3b
addiu v0,v0,4 # executed in delay slot
la t0, _stack_init # initialize stack so we
/* We must subtract 24 bytes for the 3 8 byte arguments to main, in
case main wants to write them back to the stack. The caller is
supposed to allocate stack space for parameters in registers in
the old MIPS ABIs. We must do this even though we aren't passing
arguments, because main might be declared to have them.
Some ports need a larger alignment for the stack, so we subtract
32, which satisifes the stack for the arguments and keeps the
stack pointer better aligned. */
subu t0,t0,32
move sp,t0 # set stack pointer
.end zerobss
.globl exit .text
.globl init
.ent init
init:
nop
jal init_tlb /* clear the tlb */
move a0,zero # set command line to 0
jal boot_card # call the program start function
nop
dead:
b dead
nop
.end init
/*
* _sys_exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run. NOTE: This is
* the only other routine we provide in the crt0.o object, since
* it may be tied to the "_start" routine. It also allows
* executables that contain a complete world to be linked with
* just the crt0.o object.
*/
.globl _sys_exit
.ent _sys_exit
_sys_exit:
7:
#ifdef GCRT0
jal _mcleanup
nop
#endif
/* break instruction can cope with 0xfffff, but GAS limits the range: */
break 1023
nop
b 7b # but loop back just in-case
nop
.end _sys_exit
/* EOF crt0.S */

2
c/src/lib/libbsp/mips/rbtx4925/Makefile.am
View File

@@ -10,7 +10,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/mips/rbtx4925/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

360
c/src/lib/libbsp/mips/rbtx4925/start/start.S
View File

@@ -1,360 +0,0 @@
/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
*************************************************************************
**
** Copyright 1991-95 Integrated Device Technology, Inc.
** All Rights Reserved
**
** idt_csu.S -- IDT stand alone startup code
**
**************************************************************************/
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#include <rtems/asm.h>
#include <bsp.h>
.extern mon_flush_cache
#if 0
.extern _fdata,4 /* this is defined by the linker */
.extern _edata,4 /* this is defined by the linker */
.extern _idata,4 /* this is defined by the linker */
#endif
.extern _fbss,4 /* this is defined by the linker */
.extern end,4 /* this is defined by the linker */
.lcomm sim_mem_cfg_struct,12
.text
#define HARD_CODED_MEM_SIZE 0x1000000 /* RBTX4925 has 16 megabytes of RAM */
#define PMON_VECTOR 0xbfc00500
#define TMP_STKSIZE 1024
/*
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
*/
#define P_STACKSIZE 0x2000 /* sets stack size to 8k */
/**************************************************************************
**
** start - Typical standalone start up code required for R3000/R4000
**
**
** 1) Initialize the STATUS Register
** a) Clear parity error bit
** b) Set co_processor 1 usable bit ON
** c) Clear all IntMask Enables
** d) Set kernel/disabled mode
** 2) Initialize Cause Register
** a) clear software interrupt bits
** 3) Determine FPU installed or not
** if not, clear CoProcessor 1 usable bit
** 4) Initialize data areas. Clear bss area.
** 5) MUST allocate temporary stack until memory size determined
** It MUST be uncached to prevent overwriting when caches are cleared
** 6) Install exception handlers
** 7) Determine memory and cache sizes
** 8) Establish permanent stack (cached or uncached as defined by bss)
** 9) Flush Instruction and Data caches
** 10) If there is a Translation Lookaside Buffer, Clear the TLB
** 11) Execute initialization code if the IDT/c library is to be used
**
** 12) Jump to user's "main()"
** 13) Jump to promexit
**
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** This is used to mark code specific to R3xxx or R4xxx processors.
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** when compiling with IDT/C6.x
**
***************************************************************************/
FRAME(start,sp,0,ra)
.set noreorder
#if __mips_fpr == 64
li v0,SR_CU1|SR_FR /* initally clear ERL, enable FPU with 64 bit regs */
#else
li v0,SR_CU1 /* initally clear ERL, enable FPU with 32 bit regs */
#endif
mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */
nop
mtc0 zero,C0_CAUSE /* clear software interrupts */
nop
li v0,CFG_C_NONCOHERENT /* initialise default cache mode */
mtc0 v0,C0_CONFIG
/*
** check to see if a fpu is really plugged in
*/
li t3,0xaaaa5555 /* put a's and 5's in t3 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 zero,fp1 /* try to write zero in fp */
mfc1 t0,fp0
mfc1 t1,fp1
nop
bne t0,t3,1f /* branch if no match */
nop
bne t1,zero,1f /* double check for positive id */
nop
/* We have a FPU. clear fcsr */
ctc1 zero, fcr31
j 2f /* status register already correct */
nop
1:
li v0,0x0 /* clear ERL and disable FPA */
mtc0 v0, C0_SR /* reset status register */
2:
la gp, _gp /* Initialize gp register (pointer to "small" data)*/
#if 0
/* Initialize data sections from "rom" copy */
la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */
la t1,_fdata /* start of initialized data section */
la t2,_edata /* end of initialized data section */
3:
lw t3,0(t0)
sw t3,0(t1)
addiu t1,t1,4
bne t1,t2,3b
addiu t0,t0,4
#endif
/* clear bss before using it */
la v0,_fbss /* start of bss */
la v1,end /* end of bss */
4: sw zero,0(v0)
bltu v0,v1,4b
add v0,4
/************************************************************************
**
** Temporary Stack - needed to handle stack saves until
** memory size is determined and permanent stack set
**
** MUST be uncached to avoid confusion at cache
** switching during memory sizing
**
*************************************************************************/
/* For MIPS 3, we need to be sure that the stack is aligned on a
* double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 11f /* Last three bits Zero, already aligned */
nop
add v0, 4
11:
or v0, K1BASE /* switch to uncached */
add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
sub v1, v1, (4*4) /* overhead */
move sp, v1 /* set sp to top of stack */
4: sw zero, 0(v0)
bltu v0, v1, 4b /* clear out temp stack */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
/* nop */ /* MUST do before memory probes */
/* Force processor into uncached space during memory/cache probes */
la v0, 5f
li v1, K1BASE
or v0, v1
j v0
nop
5:
li a0, HARD_CODED_MEM_SIZE /* Set memory size global */
jal set_memory_size
nop
la a0, sim_mem_cfg_struct
jal get_mem_conf /* Make call to get mem size */
nop
la a0, sim_mem_cfg_struct
lw a0, 0(a0) /* Get memory size from struct */
jal config_cache /* determine size of D & I caches */
nop
move v0, a0 /* mem_size */
/* For MIPS 3, we need to be sure that the stack (and hence v0
* here) is aligned on a double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 12f /* Last three bits Zero, already aligned */
nop
subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/
12:
/**************************************************************************
**
** Permanent Stack - now know top of memory, put permanent stack there
**
***************************************************************************/
la t2, _fbss /* cache mode as linked */
and t2, 0xF0000000 /* isolate segment */
la t1, 6f
j t1 /* back to original cache mode */
nop
6:
or v0, t2 /* stack back to original cache mode */
addiu v0,v0,-16 /* overhead */
move sp, v0 /* now replace count w top of memory */
move v1, v0
subu v1, P_STACKSIZE /* clear requested stack size */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
bltu v1,v0,7b
add v1, 4
/* Invalidate data cache*/
lui t0, 0x8000 /* Set starting address */
addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */
/* D-Cache Writeback and Invalidate */
1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */
nop
cache 1, 0(t0) /* Index_Writeback_Inv_D way 0 */
cache 1, 1(t0) /* Index_Writeback_Inv_D way 1 */
cache 1, 2(t0) /* Index_Writeback_Inv_D way 2 */
cache 1, 3(t0) /* Index_Writeback_Inv_D way 3 */
b 1b
addi t0, t0, 32
2:
/* Invalidate instruction cache*/
lui t0, 0x8000 /* Set starting address */
addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */
/* I-Cache Disable */
mfc0 t2, C0_CONFIG /* get C0_Config */
lui t3, 0x2 /* C0_CONFIG#17 ICE# */
or t3, t2, t3 /* set ICE# bit */
mtc0 t3, C0_CONFIG /* set C_Config */
b 1f /* stop streaming */
nop
/* I-Cache Invalidate */
1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */
nop
cache 0, 0(t0) /* Index_Invalidate_I way 0 */
cache 0, 1(t0) /* Index_Invalidate_I way 1 */
cache 0, 2(t0) /* Index_Invalidate_I way 2 */
cache 0, 3(t0) /* Index_Invalidate_I way 3 */
b 1b
addi t0, t0, 32
/* I-Cache Enable */
2: mtc0 t2, C0_CONFIG /* set C0_Config */
nop
/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
we don't want to run out of slow flash device. */
la t0,0x9fc00000
li t1, 0x1000
move t3, t0
addu t1, t0, t1
1: bge t0, t1, 2f
nop
lui t2, 0x1fff /* MASK */
ori t2, t2, 0xf000
and t2, t3, t2 /* virtual->physical */
srl t2, t2, 4 /* [31:12] --> [35:8] */
ori t2, t2, 0x00c4 /* Set Valid & Lock Bits */
mtc0 t2, C0_TAGLO /* Load data to TagLo reg. */
nop
cache 0x08, 3(t0) /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/
nop
cache 0x14, 3(t0) /* 5(I)=0x14: Fill(Memory->Cache) Way3*/
b 1b
addi t0, t0, 32
2: nop
.set reorder
/*
** Clear Translation Lookaside Buffer (TLB)
*/
jal init_tlb /* clear the tlb */
/*
** End of CPU initialization, ready to start kernel
*/
move a0,zero /* Set argc passed to main */
jal boot_card
nop
/* Kernel has been shutdown, jump to the "exit" routine */
jal _sys_exit
move a0,v0 # pass through the exit code
1:
beq zero,zero,1b
nop
ENDFRAME(start)
/*
* _sys_exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run. NOTE: This is
* the only other routine we provide in the crt0.o object, since
* it may be tied to the "_start" routine. It also allows
* executables that contain a complete world to be linked with
* just the crt0.o object.
*/
FRAME(_sys_exit,sp,0,ra)
break 1023
nop
13:
b 13b # but loop back just in-case
nop
ENDFRAME(_sys_exit)
.globl __sizemem
.ent __sizemem
__sizemem:
li v0,HARD_CODED_MEM_SIZE
j ra
nop
.end __sizemem

2
c/src/lib/libbsp/mips/rbtx4938/Makefile.am
View File

@@ -10,7 +10,7 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/mips/rbtx4938/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

359
c/src/lib/libbsp/mips/rbtx4938/start/start.S
View File

@@ -1,359 +0,0 @@
/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
*************************************************************************
**
** Copyright 1991-95 Integrated Device Technology, Inc.
** All Rights Reserved
**
** idt_csu.S -- IDT stand alone startup code
**
**************************************************************************/
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#include <rtems/asm.h>
#include <bsp.h>
.extern mon_flush_cache
#if 0
.extern _fdata,4 /* this is defined by the linker */
.extern _edata,4 /* this is defined by the linker */
.extern _idata,4 /* this is defined by the linker */
#endif
.extern _fbss,4 /* this is defined by the linker */
.extern end,4 /* this is defined by the linker */
.lcomm sim_mem_cfg_struct,12
.text
#define HARD_CODED_MEM_SIZE 0x1000000 /* RBTX4938 has 16 megabytes of RAM */
#define PMON_VECTOR 0xbfc00500
#define TMP_STKSIZE 1024
/*
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
*/
#define P_STACKSIZE 0x2000 /* sets stack size to 8k */
/**************************************************************************
**
** start - Typical standalone start up code required for R3000/R4000
**
**
** 1) Initialize the STATUS Register
** a) Clear parity error bit
** b) Set co_processor 1 usable bit ON
** c) Clear all IntMask Enables
** d) Set kernel/disabled mode
** 2) Initialize Cause Register
** a) clear software interrupt bits
** 3) Determine FPU installed or not
** if not, clear CoProcessor 1 usable bit
** 4) Initialize data areas. Clear bss area.
** 5) MUST allocate temporary stack until memory size determined
** It MUST be uncached to prevent overwriting when caches are cleared
** 6) Install exception handlers
** 7) Determine memory and cache sizes
** 8) Establish permanent stack (cached or uncached as defined by bss)
** 9) Flush Instruction and Data caches
** 10) If there is a Translation Lookaside Buffer, Clear the TLB
** 11) Execute initialization code if the IDT/c library is to be used
**
** 12) Jump to user's "main()"
** 13) Jump to promexit
**
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** This is used to mark code specific to R3xxx or R4xxx processors.
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** when compiling with IDT/C6.x
**
***************************************************************************/
FRAME(start,sp,0,ra)
.set noreorder
#if __mips_fpr == 64
li v0,SR_CU1|SR_FR /* initally clear ERL, enable FPU with 64 bit regs */
#else
li v0,SR_CU1 /* initally clear ERL, enable FPU with 32 bit regs */
#endif
mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */
nop
mtc0 zero,C0_CAUSE /* clear software interrupts */
nop
li v0,CFG_C_NONCOHERENT /* initialise default cache mode */
mtc0 v0,C0_CONFIG
/*
** check to see if a fpu is really plugged in
*/
li t3,0xaaaa5555 /* put a's and 5's in t3 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 zero,fp1 /* try to write zero in fp */
mfc1 t0,fp0
mfc1 t1,fp1
nop
bne t0,t3,1f /* branch if no match */
nop
bne t1,zero,1f /* double check for positive id */
nop
/* We have a FPU. clear fcsr */
ctc1 zero, fcr31
j 2f /* status register already correct */
nop
1:
li v0,0x0 /* clear ERL and disable FPA */
mtc0 v0, C0_SR /* reset status register */
2:
la gp, _gp /* Initialize gp register (pointer to "small" data)*/
#if 0
/* Initialize data sections from "rom" copy */
la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */
la t1,_fdata /* start of initialized data section */
la t2,_edata /* end of initialized data section */
3:
lw t3,0(t0)
sw t3,0(t1)
addiu t1,t1,4
bne t1,t2,3b
addiu t0,t0,4
#endif
/* clear bss before using it */
la v0,_fbss /* start of bss */
la v1,end /* end of bss */
4: sw zero,0(v0)
bltu v0,v1,4b
add v0,4
/************************************************************************
**
** Temporary Stack - needed to handle stack saves until
** memory size is determined and permanent stack set
**
** MUST be uncached to avoid confusion at cache
** switching during memory sizing
**
*************************************************************************/
/* For MIPS 3, we need to be sure that the stack is aligned on a
* double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 11f /* Last three bits Zero, already aligned */
nop
add v0, 4
11:
or v0, K1BASE /* switch to uncached */
add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
sub v1, v1, (4*4) /* overhead */
move sp, v1 /* set sp to top of stack */
4: sw zero, 0(v0)
bltu v0, v1, 4b /* clear out temp stack */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
/* nop */ /* MUST do before memory probes */
/* Force processor into uncached space during memory/cache probes */
la v0, 5f
li v1, K1BASE
or v0, v1
j v0
nop
5:
li a0, HARD_CODED_MEM_SIZE /* Set memory size global */
jal set_memory_size
nop
la a0, sim_mem_cfg_struct
jal get_mem_conf /* Make call to get mem size */
nop
la a0, sim_mem_cfg_struct
lw a0, 0(a0) /* Get memory size from struct */
jal config_cache /* determine size of D & I caches */
nop
move v0, a0 /* mem_size */
/* For MIPS 3, we need to be sure that the stack (and hence v0
* here) is aligned on a double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 12f /* Last three bits Zero, already aligned */
nop
subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/
12:
/**************************************************************************
**
** Permanent Stack - now know top of memory, put permanent stack there
**
***************************************************************************/
la t2, _fbss /* cache mode as linked */
and t2, 0xF0000000 /* isolate segment */
la t1, 6f
j t1 /* back to original cache mode */
nop
6:
or v0, t2 /* stack back to original cache mode */
addiu v0,v0,-16 /* overhead */
move sp, v0 /* now replace count w top of memory */
move v1, v0
subu v1, P_STACKSIZE /* clear requested stack size */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
bltu v1,v0,7b
add v1, 4
/* Invalidate data cache*/
lui t0, 0x8000 /* Set starting address */
addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */
/* D-Cache Writeback and Invalidate */
1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */
nop
cache 1, 0(t0) /* Index_Writeback_Inv_D way 0 */
cache 1, 1(t0) /* Index_Writeback_Inv_D way 1 */
cache 1, 2(t0) /* Index_Writeback_Inv_D way 2 */
cache 1, 3(t0) /* Index_Writeback_Inv_D way 3 */
b 1b
addi t0, t0, 32
2:
/* Invalidate instruction cache*/
lui t0, 0x8000 /* Set starting address */
addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */
/* I-Cache Disable */
mfc0 t2, C0_CONFIG /* get C0_Config */
lui t3, 0x2 /* C0_CONFIG#17 ICE# */
or t3, t2, t3 /* set ICE# bit */
mtc0 t3, C0_CONFIG /* set C_Config */
b 1f /* stop streaming */
nop
/* I-Cache Invalidate */
1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */
nop
cache 0, 0(t0) /* Index_Invalidate_I way 0 */
cache 0, 1(t0) /* Index_Invalidate_I way 1 */
cache 0, 2(t0) /* Index_Invalidate_I way 2 */
cache 0, 3(t0) /* Index_Invalidate_I way 3 */
b 1b
addi t0, t0, 32
/* I-Cache Enable */
2: mtc0 t2, C0_CONFIG /* set C0_Config */
nop
/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
we don't want to run out of slow flash device. */
la t0,0x9fc00000
li t1, 0x1000
move t3, t0
addu t1, t0, t1
1: bge t0, t1, 2f
nop
lui t2, 0x1fff /* MASK */
ori t2, t2, 0xf000
and t2, t3, t2 /* virtual->physical */
srl t2, t2, 4 /* [31:12] --> [35:8] */
ori t2, t2, 0x00c4 /* Set Valid & Lock Bits */
mtc0 t2, C0_TAGLO /* Load data to TagLo reg. */
nop
cache 0x08, 3(t0) /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/
nop
cache 0x14, 3(t0) /* 5(I)=0x14: Fill(Memory->Cache) Way3*/
b 1b
addi t0, t0, 32
2: nop
.set reorder
/*
** Clear Translation Lookaside Buffer (TLB)
*/
jal init_tlb /* clear the tlb */
/*
** End of CPU initialization, ready to start kernel
*/
move a0,zero /* Set command line passed to boot_card */
jal boot_card
nop
/* Kernel has been shutdown, jump to the "exit" routine */
jal _sys_exit
move a0,v0 # pass through the exit code
1:
beq zero,zero,1b
nop
ENDFRAME(start)
/*
* _sys_exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run. NOTE: This is
* the only other routine we provide in the crt0.o object, since
* it may be tied to the "_start" routine. It also allows
* executables that contain a complete world to be linked with
* just the crt0.o object.
*/
FRAME(_sys_exit,sp,0,ra)
break 1023
nop
13:
b 13b # but loop back just in-case
nop
ENDFRAME(_sys_exit)
.globl __sizemem
.ent __sizemem
__sizemem:
li v0,HARD_CODED_MEM_SIZE
j ra
nop
.end __sizemem

2
c/src/lib/libbsp/moxie/moxiesim/Makefile.am
View File

@@ -11,7 +11,7 @@ dist_project_lib_DATA = startup/bsp_specs
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/moxie/moxiesim/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

28
c/src/lib/libbsp/moxie/moxiesim/start/start.S
View File

@@ -1,28 +0,0 @@
/* Copyright (C) 2011, 2013, 2014 Anthony Green */
/* moxie start up file. */
#include "bspopts.h"
#if defined(HAVE_OLD_MOXIE_ASM)
#define sub sub.l
#endif
.text
.global _start
_start:
ldi.l $sp, _stack /* load up stack pointer */
xor $fp, $fp /* zero fp to allow unwinders to stop */
/* zero the bss area */
ldi.l $r0, __bss_start__
xor $r1, $r1
ldi.l $r2, __bss_end__
sub $r2, $r0
jsra memset
ldi.l $r0, 0x0 # pass in NULL
jsra boot_card
jmpa _start # restart
.Lend:
.size _start,(.Lend-_start)

4
c/src/lib/libbsp/nios2/nios2_iss/Makefile.am
View File

@@ -7,9 +7,9 @@ dist_project_lib_DATA = startup/bsp_specs
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/nios2/nios2_iss/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
crtnn.$(OBJEXT): start/crtnn.S
crtnn.$(OBJEXT): ../../../../../../bsps/nios2/nios2_iss/start/crtnn.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT) crtnn.$(OBJEXT)

43
c/src/lib/libbsp/nios2/nios2_iss/start/crtnn.S
View File

@@ -1,43 +0,0 @@
/* NIOS2 crtn.asm fix
*
* COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
/* Can't use the original crtn.asm from Altera because it doesn't
restore the stack pointer correctly (in 5.1b73, the stack pointer
is further decreased by 48 instead of increased). This is named
differently (crtnn instead crtn) to make sure it can be picked up
using custom gcc specs instead of gcc's crtn. - kawk */
.section .init
ldw ra, 44(sp)
ldw r23, 40(sp)
ldw r22, 36(sp)
ldw r21, 32(sp)
ldw r20, 28(sp)
ldw r19, 24(sp)
ldw r18, 20(sp)
ldw r17, 16(sp)
ldw r16, 12(sp)
ldw fp, 8(sp)
addi sp, sp, 48
ret
.section .fini
ldw ra, 44(sp)
ldw r23, 40(sp)
ldw r22, 36(sp)
ldw r21, 32(sp)
ldw r20, 28(sp)
ldw r19, 24(sp)
ldw r18, 20(sp)
ldw r17, 16(sp)
ldw r16, 12(sp)
ldw fp, 8(sp)
addi sp, sp, 48
ret

122
c/src/lib/libbsp/nios2/nios2_iss/start/start.S
View File

@@ -1,122 +0,0 @@
/* NIOS2 startup code
*
* This is the entry point on reset and when loading the
* executive from a bootloader.
*
* COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
.section .entry
.align 3
movhi et, %hiadj(start)
addi et, et, %lo(start)
jmp et
.section .irq
.align 3
movhi et, %hiadj(_exception_vector)
addi et, et, %lo(_exception_vector)
jmp et
.section .text
.align 3
.globl start
.type start,@function
.extern _exception_vector
start:
#------------------------------------------------------
# disable interrupts
wrctl status, zero
wrctl ienable, zero
#------------------------------------------------------
# invalidate instruction cache
mov r2, r0
movhi r3, %hi(__nios2_icache_size)
ori r3, r3, %lo(__nios2_icache_size)
icache_init_loop:
initi r2
addi r2, r2, __nios2_icache_line_size
bltu r2, r3, icache_init_loop
#------------------------------------------------------
# invalidate data cache
mov r2, r0
movhi r3, %hi(__nios2_dcache_size)
ori r3, r3, %lo(__nios2_dcache_size)
dcache_init_loop:
initd 0(r2)
addi r2, r2, __nios2_dcache_line_size
bltu r2, r3, dcache_init_loop
#------------------------------------------------------
# initialize stack pointer
movhi sp, %hiadj(__alt_stack_pointer - 4)
addi sp, sp, %lo(__alt_stack_pointer - 4)
# initialize global pointer
movhi gp, %hiadj(_gp)
addi gp, gp, %lo(_gp)
# initialize exception tmp register
movhi et, %hiadj(_end)
addi et, et, %lo(_end)
#------------------------------------------------------
# TODO: copy data from flash to RAM, if not there already
# For now its save to assume it is there already when we're
# loading code though JTAG into RAM-only system
# at least copy exception code to right place
movhi r2, %hiadj(__ram_exceptions_start)
addi r2, r2, %lo(__ram_exceptions_start)
movhi r3, %hiadj(brto_ev)
addi r3, r3, %lo(brto_ev)
ldw r4, 0(r3)
stw r4, 0(r2)
ldw r4, 4(r3)
stw r4, 4(r2)
ldw r4, 8(r3)
stw r4, 8(r2)
ldw r4, 12(r3)
stw r4, 12(r2)
#------------------------------------------------------
# clear bss
movhi r2, %hiadj(__bss_start)
addi r2, r2, %lo(__bss_start)
movhi r3, %hiadj(__bss_end)
addi r3, r3, %lo(__bss_end)
beq r2, r3, 1f
0:
stw zero, (r2)
addi r2, r2, 4
bltu r2, r3, 0b
1:
#------------------------------------------------------
# jump to (shared) boot_card (never comes back)
mov r4, zero
mov r5, zero
mov r6, zero
call boot_card
# but just in case it does come back, stick here.
_stuck_in_start:
br _stuck_in_start
#------------------------------------------------------
# code to be placed at exception address
brto_ev:
movhi et, %hiadj(_exception_vector)
addi et, et, %lo(_exception_vector)
jmp et

2
c/src/lib/libbsp/or1k/generic_or1k/Makefile.am
View File

@@ -19,7 +19,7 @@ dist_project_lib_DATA = startup/bsp_specs
# Data #
###############################################################################
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/or1k/generic_or1k/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)

181
c/src/lib/libbsp/or1k/generic_or1k/start/start.S
View File

@@ -1,181 +0,0 @@
/*
* Copyright (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE
*/
#include <bsp/linker-symbols.h>
/* The following macro defines the first instructions every exception
* should execute before jumping to its handler function from the
* exception vector table. r3 is saved into the stack and loaded with
* vector number before jumping to _ISR_Handler. r3 value is restored
* back from _ISR_Handler after handling the exception and before
* returning from interrupt.
*/
#define EXCEPTION_SETUP(vector) \
l.nop ;\
l.addi r1, r1, -200 ;\
l.sw 0(r1), r3; \
l.addi r3, r0, vector; \
l.j _ISR_Handler; \
l.nop
.extern boot_card
.extern bsp_section_bss_begin
.extern bsp_section_bss_end
.extern bsp_start_vector_table_end
.extern bsp_start_vector_table_size
.extern bsp_vector_table_size
.extern bsp_section_stack_begin
.extern exception_frame_save
.extern _OR1K_Exception_Process
.extern _OR1K_Exception_default
.extern rtems_clock_tick
.extern _exit
.extern printk
.extern bsp_interrupt_handler_default
/* Global symbols */
.global _start
.global bsp_start_vector_table_begin
/* Popualte HW vector table */
.section .vector, "ax"
.org 0x100
_reset:
l.j _start
l.nop
.org 0x200
_buserr:
EXCEPTION_SETUP(2)
.org 0x300
_dPageFault:
EXCEPTION_SETUP(3)
.org 0x400
_iPageFaule:
EXCEPTION_SETUP(4)
.org 0x500
_timer:
EXCEPTION_SETUP(5)
.org 0x600
_unalign:
EXCEPTION_SETUP(6)
.org 0x700
_undefIns:
EXCEPTION_SETUP(7)
.org 0x800
_exInt:
EXCEPTION_SETUP(8)
.org 0x900
_dTLB:
EXCEPTION_SETUP(9)
.org 0xA00
_iTLB:
EXCEPTION_SETUP(10)
.org 0xB00
_range:
EXCEPTION_SETUP(11)
.org 0xC00
_syscall:
EXCEPTION_SETUP(12)
.org 0xD00
_fp:
EXCEPTION_SETUP(13)
.org 0xE00
_trap:
EXCEPTION_SETUP(14)
.org 0xF00
_undef1:
EXCEPTION_SETUP(15)
.org 0x1500
_undef2:
EXCEPTION_SETUP(16)
.org 0x1900
_undef3:
EXCEPTION_SETUP(17)
.org 0x1F00
bsp_start_vector_table_begin:
.word 0
.word _start /* Reset */
.word _OR1K_Exception_default /* Bus Error */
.word _OR1K_Exception_default /* Data Page Fault */
.word _OR1K_Exception_default /* Instruction Page Fault */
.word _OR1K_Exception_default /* Tick timer */
.word _OR1K_Exception_default /* Alignment */
.word _OR1K_Exception_default /* Undefiend Instruction */
.word _OR1K_Exception_default /* External Interrupt */
.word _OR1K_Exception_default /* Data TLB Miss */
.word _OR1K_Exception_default /* Instruction TLB Miss */
.word _OR1K_Exception_default /* Range Exception */
.word _OR1K_Exception_default /* System Call */
.word _OR1K_Exception_default /* Floating Point Exception */
.word _OR1K_Exception_default /* Trap */
.word _OR1K_Exception_default /* Reserver for future use */
.word _OR1K_Exception_default /* Reserved for implementation-specific */
.word _OR1K_Exception_default /* Reserved for custom exceptions. */
bsp_start_vector_table_end:
.section ".bsp_start_text", "ax"
.type _start,@function
_start:
/* Set SR register to Supervision mode */
l.ori r1, r0, 0x1
l.mtspr r0, r1, 17
/* load stack and frame pointers */
l.movhi r1, hi(bsp_section_stack_begin)
l.ori r1, r1, lo(bsp_section_stack_begin)
l.add r2, r0, r1
/* Clearing .bss */
l.movhi r13, hi(bsp_section_bss_begin)
l.ori r13, r13, lo(bsp_section_bss_begin)
l.movhi r15, hi(bsp_section_bss_end)
l.ori r15, r15, lo(bsp_section_bss_end)
_loop_clear_bss:
l.sfgeu r13, r15
l.bf _end_clear_bss
l.addi r13, r13, 4
l.sw 0(r13), r0
l.j _loop_clear_bss
l.nop
_end_clear_bss:
l.j boot_card
l.nop
/* Temporary code for unhandled exceptions */
.section .text
.align
.global _unhandled_exception
unhandled_exception:
l.nop

8
c/src/lib/libbsp/powerpc/beatnik/Makefile.am
View File

@@ -13,18 +13,18 @@ project_lib_DATA =
#include
#start
rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S
rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -DASM -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT)
preload.$(OBJEXT): ../shared/start/preload.S
preload.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/preload.S
$(CPPASCOMPILE) -DASM -o $@ -c $<
vectors_entry.$(OBJEXT): ../shared/start/vectors_entry.S
vectors_entry.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/vectors_entry.S
$(CPPASCOMPILE) -DASM -o $@ -c $<
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/start.S
$(CPPASCOMPILE) -DASM -o $@ -c $<
motld_start.$(OBJEXT): preload.$(OBJEXT) vectors_entry.$(OBJEXT) start.$(OBJEXT)

4
c/src/lib/libbsp/powerpc/gen5200/Makefile.am
View File

@@ -9,11 +9,11 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/powerpc/gen5200/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S
rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT)

1000
c/src/lib/libbsp/powerpc/gen5200/start/start.S
View File

File diff suppressed because it is too large Load Diff

4
c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
View File

@@ -9,11 +9,11 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/powerpc/gen83xx/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S
rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT)

529
c/src/lib/libbsp/powerpc/gen83xx/start/start.S
View File

@@ -1,529 +0,0 @@
/*===============================================================*\
| Project: RTEMS generic MPC83xx BSP |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.org/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| this file contains the startup assembly code |
\*===============================================================*/
#include <libcpu/powerpc-utility.h>
#include <rtems/powerpc/cache.h>
#include <bsp.h>
#include <mpc83xx/mpc83xx.h>
.macro SET_IMM_REGW base, reg2, offset, value
LA \reg2, \value
stw \reg2,\offset(\base)
.endm
#define REP8(l) l ; l; l; l; l; l; l; l;
.extern boot_card
.extern MBAR
#if defined(RESET_CONF_WRD_L)
.section ".resconf","ax"
PUBLIC_VAR (reset_conf_words)
reset_conf_words:
REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff))
REP8( .byte ((RESET_CONF_WRD_L >> 0) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 24) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff))
#endif
.section ".vectors","ax"
PUBLIC_VAR (reset_vec)
reset_vec:
bl rom_entry
.section ".bsp_start_text", "ax"
PUBLIC_VAR (_start)
_start:
/* Reset time base */
li r0, 0
mtspr TBWU, r0
mtspr TBWL, r0
#ifdef HAS_UBOOT
mr r14, r3
#endif /* HAS_UBOOT */
/*
* basic CPU setup:
* init MSR
*/
mfmsr r30
SETBITS r30, r29, MSR_ME|MSR_RI
CLRBITS r30, r29, MSR_IP|MSR_EE
mtmsr r30 /* Set RI/ME, Clr EE in MSR */
b start_rom_skip
PUBLIC_VAR (rom_entry)
rom_entry:
/*
* basic CPU setup:
* init MSR
*/
mfmsr r30
SETBITS r30, r29, MSR_ME|MSR_RI
CLRBITS r30, r29, MSR_IP|MSR_EE
mtmsr r30 /* Set RI/ME, Clr EE in MSR */
/*
* ROM startup: remap IMMR to 0xE0000000
* use special sequence from MPC8349EA RM Rev 1, 5.2.4.1.1 "Updating IMMRBAR"
*/
LWI r30,IMMRBAR_DEFAULT
LWI r31,IMMRBAR
lwz r29,0(r30)
stw r31,0(r30)
#if 0
lwz r29,0(r28) /* read from ROM... */
#endif
isync
lwz r29,0(r31) /* read from IMMRBAR... */
isync
/*
* NOTE: now r31 points to onchip registers
*/
/*
* we start from 0x100, so ROM is currently mapped to
* 0x00000000..
* in the next step, ROM will be remapped to its final location
* at 0xfe000000... (using LBLAWBAR1 with LBLAWBAR0 value)
* and we jump to that location.
* then we remove the ROM mapping to zero
*/
#ifdef LBLAWBAR0_VAL
SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR0_VAL
#endif
#ifdef LBLAWAR0_VAL
SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR0_VAL
#endif
/*
* ROM startup: jump to code final ROM location
*/
LA r20, bsp_rom_start /* ROM-RAM reloc in r20 */
LA r29, start_code_in_rom /* get compile time addr of label */
add r29,r20,r29 /* compute exec address */
mtlr r29
blr /* now further execution in upper ROM */
start_code_in_rom:
#ifdef LBLAWBAR0_VAL
SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL
#endif
#ifdef LBLAWAR0_VAL
SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL
#endif
/*
* Local access window 1 is a special case since we used it for a temporary
* mapping. If we do not use it then restore the reset value.
*/
#ifdef LBLAWBAR1_VAL
SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL
#else
SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,0
#endif
#ifdef LBLAWAR1_VAL
SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR1_VAL
#else
SET_IMM_REGW r31,r30,LBLAWAR1_OFF,0
#endif
#ifdef LBLAWBAR2_VAL
SET_IMM_REGW r31,r30,LBLAWBAR2_OFF,LBLAWBAR2_VAL
#endif
#ifdef LBLAWAR2_VAL
SET_IMM_REGW r31,r30,LBLAWAR2_OFF,LBLAWAR2_VAL
#endif
#ifdef LBLAWBAR3_VAL
SET_IMM_REGW r31,r30,LBLAWBAR3_OFF,LBLAWBAR3_VAL
#endif
#ifdef LBLAWAR3_VAL
SET_IMM_REGW r31,r30,LBLAWAR3_OFF,LBLAWAR3_VAL
#endif
/*
* ROM startup: init bus system
*/
#ifdef BR0_VAL
SET_IMM_REGW r31,r30,BR0_OFF,BR0_VAL
#endif
#ifdef OR0_VAL
SET_IMM_REGW r31,r30,OR0_OFF,OR0_VAL
#endif
#ifdef BR1_VAL
SET_IMM_REGW r31,r30,BR1_OFF,BR1_VAL
#endif
#ifdef OR1_VAL
SET_IMM_REGW r31,r30,OR1_OFF,OR1_VAL
#endif
#ifdef BR2_VAL
SET_IMM_REGW r31,r30,BR2_OFF,BR2_VAL
#endif
#ifdef OR2_VAL
SET_IMM_REGW r31,r30,OR2_OFF,OR2_VAL
#endif
#ifdef BR3_VAL
SET_IMM_REGW r31,r30,BR3_OFF,BR3_VAL
#endif
#ifdef OR3_VAL
SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
#endif
#ifdef BR4_VAL
SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL
#endif
#ifdef OR4_VAL
SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL
#endif
#ifdef BR5_VAL
SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL
#endif
#ifdef OR5_VAL
SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL
#endif
/*
* ROM startup: init SDRAM access window
*/
#ifdef DDRLAWBAR0_VAL
SET_IMM_REGW r31,r30,DDRLAWBAR0_OFF,DDRLAWBAR0_VAL
#endif
#ifdef DDRLAWAR0_VAL
SET_IMM_REGW r31,r30,DDRLAWAR0_OFF,DDRLAWAR0_VAL
#endif
#ifdef DDRLAWBAR1_VAL
SET_IMM_REGW r31,r30,DDRLAWBAR1_OFF,DDRLAWBAR1_VAL
#endif
#ifdef DDRLAWAR1_VAL
SET_IMM_REGW r31,r30,DDRLAWAR1_OFF,DDRLAWAR1_VAL
#endif
/*
* ROM startup: init refresh interval
*/
#ifdef MRPTR_VAL
SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL
#endif
/*
* ROM startup: init SDRAM
*/
#ifdef LSRT_VAL
SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL
#endif
#ifdef LSDMR_VAL
SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL
#endif
#ifdef CS0_BNDS_VAL
SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL
#endif
#ifdef CS1_BNDS_VAL
SET_IMM_REGW r31,r30,CS1_BNDS_OFF,CS1_BNDS_VAL
#endif
#ifdef CS2_BNDS_VAL
SET_IMM_REGW r31,r30,CS2_BNDS_OFF,CS2_BNDS_VAL
#endif
#ifdef CS3_BNDS_VAL
SET_IMM_REGW r31,r30,CS3_BNDS_OFF,CS3_BNDS_VAL
#endif
#ifdef CS0_CONFIG_VAL
SET_IMM_REGW r31,r30,CS0_CONFIG_OFF,CS0_CONFIG_VAL
#endif
#ifdef CS1_CONFIG_VAL
SET_IMM_REGW r31,r30,CS1_CONFIG_OFF,CS1_CONFIG_VAL
#endif
#ifdef CS2_CONFIG_VAL
SET_IMM_REGW r31,r30,CS2_CONFIG_OFF,CS2_CONFIG_VAL
#endif
#ifdef CS3_CONFIG_VAL
SET_IMM_REGW r31,r30,CS3_CONFIG_OFF,CS3_CONFIG_VAL
#endif
#ifdef TIMING_CFG_3_VAL
SET_IMM_REGW r31,r30,TIMING_CFG_3_OFF,TIMING_CFG_3_VAL
#endif
#ifdef TIMING_CFG_0_VAL
SET_IMM_REGW r31,r30,TIMING_CFG_0_OFF,TIMING_CFG_0_VAL
#endif
#ifdef TIMING_CFG_1_VAL
SET_IMM_REGW r31,r30,TIMING_CFG_1_OFF,TIMING_CFG_1_VAL
#endif
#ifdef TIMING_CFG_2_VAL
SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL
#endif
#ifdef DDRCDR_VAL
SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL
#endif
#ifdef DDR_SDRAM_CFG_2_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL
#endif
#ifdef DDR_SDRAM_MODE_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_OFF,DDR_SDRAM_MODE_VAL
#endif
#ifdef DDR_SDRAM_MODE_2_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_MODE_2_OFF,DDR_SDRAM_MODE_2_VAL
#endif
#ifdef DDR_SDRAM_MD_CNTL_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_MD_CNTL_OFF,DDR_SDRAM_MD_CNTL_VAL
#endif
#ifdef DDR_SDRAM_MD_ITVL_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_MD_ITVL_OFF,DDR_SDRAM_MD_ITVL_VAL
#endif
#ifdef DDR_SDRAM_CLK_CNTL_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL
#endif
#ifdef DDR_SDRAM_CFG_2_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL|DDR_SDRAM_CFG_2_D_INIT
#endif
#ifdef DDR_ERR_DISABLE_VAL
/*
* disable detect of RAM errors
*/
SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL
#endif
#ifdef DDR_SDRAM_DATA_INIT_VAL
/*
* set this value to initialize memory
*/
SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL
#endif
#ifdef DDR_SDRAM_INIT_ADDR_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL
#endif
#ifdef DDR_SDRAM_CFG_VAL
/*
* config DDR SDRAM
*/
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN
/*
* FIXME: wait 200us
*/
/*
* enable DDR SDRAM
*/
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL | DDR_SDRAM_CFG_MEM_EN
/*
* wait, until DDR_SDRAM_CFG_2_D_INIT is cleared
*/
1: lwz r30,DDR_SDRAM_CFG_2_OFF(r31)
andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT
bne 1b
#endif
#ifdef DDR_ERR_DISABLE_VAL2
/*
* enable detect of some RAM errors
*/
SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2
#endif
#ifdef DDR_SDRAM_INTERVAL_VAL
/*
* set the refresh interval
*/
SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL
#endif
start_rom_skip:
/*
* determine current execution address offset
*/
bl start_rom_skip1
start_rom_skip1:
mflr r20
LA r30,start_rom_skip1
sub. r20,r20,r30
/*
* execution address offset == 0?
* then do not relocate code and data
*/
beq start_code_in_ram
/*
* ROM or relocatable startup: copy startup code to SDRAM
*/
/* get start address of start section in RAM */
LA r29, bsp_section_start_begin
/* get start address of start section in ROM (add reloc offset) */
add r30, r20, r29
/* get size of startup code */
LA r28, bsp_section_start_end
sub 28,r28,r29
/* copy startup code from ROM to RAM location */
bl copy_image
/*
* ROM startup: jump to code copy in SDRAM
*/
/* get compile time address of label */
LA r29, copy_rest_of_text
mtlr r29
blr /* now further execution RAM */
copy_rest_of_text:
LWI r31,IMMRBAR
#ifdef LCRR_VAL
SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL
#endif
/*
* ROM or relocatable startup: copy rest of code to SDRAM
*/
/* get start address of rest of loadable sections in RAM */
LA r29, bsp_section_text_begin
/* get start address of loadable sections in ROM (add reloc offset) */
add r30, r20, r29
/* get size of rest of loadable sections */
LA r28, bsp_section_data_end
sub r28,r28,r29
bl copy_image /* copy text section from ROM to RAM location */
start_code_in_ram:
/*
* ROM/RAM startup: clear bss in SDRAM
*/
LA r3, bsp_section_sbss_begin /* get start address of bss section */
LA r4, bsp_section_bss_end /* get end address of bss section */
sub r4, r4, r3 /* get size of bss section */
bl mpc83xx_zero_4 /* Clear the bss section */
#ifdef HAS_UBOOT
mr r3, r14
bl bsp_uboot_copy_board_info
#endif /* HAS_UBOOT */
/* Read-only small data */
LA r2, _SDA2_BASE_
/* Read-write small data */
LA r13, _SDA_BASE_
/* Clear cmdline */
li r3, 0
/* Set start stack pointer */
LA r1, start_stack_end
stwu r3, -4(r1)
stwu r3, -4(r1)
/* Call the first C routine */
bl SYM (boot_card)
twiddle:
/* We don't expect to return from boot_card but if we do */
/* wait here for watchdog to kick us into hard reset */
b twiddle
copy_image:
cmpwi r28, 0
beqlr
mr r27, r28
srwi r28, r28, 2
mtctr r28
slwi r28, r28, 2
sub r27, r27, r28 /* maybe some residual bytes */
copy_image_word:
lswi r28, r30, 0x04
stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
addi r30, r30, 0x04 /* increment source pointer */
addi r29, r29, 0x04 /* increment destination pointer */
bdnz copy_image_word /* decrement ctr and branch if not 0 */
cmpwi r27, 0x00 /* copy image finished ? */
beq copy_image_end;
mtctr r27 /* reload counter for residual bytes */
copy_image_byte:
lswi r28, r30, 0x01
stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
addi r30, r30, 0x01 /* increment source pointer */
addi r29, r29, 0x01 /* increment destination pointer */
bdnz copy_image_byte /* decrement ctr and branch if not 0 */
copy_image_end:
blr
/**
* @fn int mpc83xx_zero_4( void *dest, size_t n)
*
* @brief Zero all @a n bytes starting at @a dest with 4 byte writes.
*
* The address @a dest has to be aligned on 4 byte boundaries. The size @a n
* must be evenly divisible by 4.
*/
GLOBAL_FUNCTION mpc83xx_zero_4
/* Create zero */
xor r0, r0, r0
/* Set offset */
xor r5, r5, r5
/* Loop counter for the first bytes up to 16 bytes */
rlwinm. r9, r4, 30, 30, 31
beq mpc83xx_zero_4_more
mtctr r9
mpc83xx_zero_4_head:
stwx r0, r3, r5
addi r5, r5, 4
bdnz mpc83xx_zero_4_head
mpc83xx_zero_4_more:
/* More than 16 bytes? */
srwi. r9, r4, 4
beqlr
mtctr r9
/* Set offsets */
addi r6, r5, 4
addi r7, r5, 8
addi r8, r5, 12
mpc83xx_zero_4_tail:
stwx r0, r3, r5
addi r5, r5, 16
stwx r0, r3, r6
addi r6, r6, 16
stwx r0, r3, r7
addi r7, r7, 16
stwx r0, r3, r8
addi r8, r8, 16
bdnz mpc83xx_zero_4_tail
/* Return */
blr
.section ".bsp_rwextra", "aw", @nobits
/* Start stack area */
.align 4
.space 4096
start_stack_end:

2
c/src/lib/libbsp/powerpc/haleakala/Makefile.am
View File

@@ -7,7 +7,7 @@ dist_project_lib_DATA = startup/bsp_specs
rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S
rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = rtems_crti.$(OBJEXT)

6
c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am
View File

@@ -15,15 +15,15 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): ../shared/start/start.S
start.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S
rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT)
vectors_entry.$(OBJEXT): ../shared/start/vectors_entry.S
vectors_entry.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/vectors_entry.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += vectors_entry.$(OBJEXT)

4
c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
View File

@@ -9,11 +9,11 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/powerpc/mpc55xxevb/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S
rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT)

299
c/src/lib/libbsp/powerpc/mpc55xxevb/start/start.S
View File

@@ -1,299 +0,0 @@
/**
* @file
*
* @ingroup mpc55xx_asm
*
* @brief Boot and system start code.
*/
/*
* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bspopts.h>
#include <bsp/linker-symbols.h>
#include <libcpu/powerpc-utility.h>
#if MPC55XX_CHIP_FAMILY != 551
#define HAS_SPE
#endif
#if MPC55XX_CHIP_FAMILY == 564
#define INIT_REGISTERS_FOR_LSM
#endif
#ifdef HAS_SPE
#define ZERO_GPR(reg) evxor reg, reg, reg
#else
#define ZERO_GPR(reg) xor reg, reg, reg
#endif
.extern __eabi
.extern boot_card
.extern bsp_ram_start
.extern mpc55xx_start_config_mmu_early
.extern mpc55xx_start_config_mmu_early_count
.extern mpc55xx_start_early
.globl _start
.globl mpc55xx_start_load_section
.globl mpc55xx_start_mmu_apply_config
#ifdef MPC55XX_BOOTFLAGS
.globl mpc55xx_bootflag_0
.globl mpc55xx_bootflag_1
#endif
.section ".bsp_start_text", "ax"
/* BAM: RCHW */
.int 0x005a0000
/* BAM: Address of start instruction */
.int _start
#ifdef MPC55XX_BOOTFLAGS
/*
* We skip over the next two boot flag words to the next 64-bit
* aligned start address. It is 64-bit aligned to play well with
* FLASH programming. These boot flags can be set by debuggers
* and emulators to customize boot. Currently bit0 of
* bootflag_0 means to "skip setting up the MMU", allowing
* external MMU setup in a debugger before branching to 0x10.
* This can be used e.g., to map FLASH into RAM.
*/
mpc55xx_bootflag_0:
.int 0xffffffff
mpc55xx_bootflag_1:
.int 0xffffffff
#endif
_start:
#ifdef MPC55XX_ENABLE_START_PROLOGUE
bl mpc55xx_start_prologue
#endif
#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
/* Enable SPE */
#ifdef HAS_SPE
mfmsr r3
oris r3, r3, MSR_SPE >> 16
mtmsr r3
isync
#endif
/*
* Initialization of core registers according to "e200z4 Power
* Architecture Core Reference Manual" section 2.6 "Reset Settings"
* table 2-16 "Reset Settings of e200 Resources". This is necessary
* for lock step mode (LSM).
*/
ZERO_GPR(r0)
#ifdef INIT_REGISTERS_FOR_LSM
ZERO_GPR(r1)
ZERO_GPR(r2)
ZERO_GPR(r4)
ZERO_GPR(r5)
ZERO_GPR(r6)
ZERO_GPR(r7)
ZERO_GPR(r8)
ZERO_GPR(r9)
ZERO_GPR(r10)
ZERO_GPR(r11)
ZERO_GPR(r12)
ZERO_GPR(r13)
ZERO_GPR(r14)
ZERO_GPR(r15)
ZERO_GPR(r16)
ZERO_GPR(r17)
ZERO_GPR(r18)
ZERO_GPR(r19)
ZERO_GPR(r20)
ZERO_GPR(r21)
ZERO_GPR(r22)
ZERO_GPR(r23)
ZERO_GPR(r24)
ZERO_GPR(r25)
ZERO_GPR(r26)
ZERO_GPR(r27)
ZERO_GPR(r28)
ZERO_GPR(r29)
ZERO_GPR(r30)
ZERO_GPR(r31)
mtcrf 0xff, r0
mtcsrr0 r0
mtcsrr1 r0
mtctr r0
mtspr FSL_EIS_DBCNT, r0
mtspr DEAR_BOOKE, r0
mtdec r0
mtspr BOOKE_DECAR, r0
mtspr FSL_EIS_DSRR0, r0
mtspr FSL_EIS_DSRR1, r0
mtspr BOOKE_DVC1, r0
mtspr BOOKE_DVC2, r0
mtspr BOOKE_IVPR, r0
mtlr r0
mtspr FSL_EIS_MCAR, r0
mtmcsrr0 r0
mtmcsrr1 r0
mtspr SPRG0, r0
mtspr SPRG1, r0
mtspr SPRG2, r0
mtspr SPRG3, r0
mtspr SPRG4, r0
mtspr SPRG5, r0
mtspr SPRG6, r0
mtspr SPRG7, r0
mtspr FSL_EIS_SPRG8, r0
mtspr FSL_EIS_SPRG9, r0
mtsrr0 r0
mtsrr1 r0
mtspr USPRG0, r0
#ifdef HAS_SPE
evmra r0, r0
#endif
#endif /* INIT_REGISTERS_FOR_LSM */
mtspr TBWL, r0
mtspr TBWU, r0
/* Enable time base */
mfspr r3, HID0
ori r3, r3, 0x4000
mtspr HID0, r3
/*
* Enable branch prediction.
*
* Errata e4396: e200z7: Erroneous Address Fetch
*
* The propose workaround does not work.
*/
#if MPC55XX_CHIP_FAMILY != 567
LWI r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BALLOC_ALL | FSL_EIS_BUCSR_BPRED_NOT_TAKEN | FSL_EIS_BUCSR_BPEN
mtspr FSL_EIS_BUCSR, r3
#endif
#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
/* MMU early initialization */
LA r3, mpc55xx_start_config_mmu_early
LW r4, mpc55xx_start_config_mmu_early_count
bl mpc55xx_start_mmu_apply_config
#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
/* Initialize intermediate stack (ECC) */
LA r3, bsp_ram_start
addi r4, r3, MPC55XX_EARLY_STACK_SIZE
zero_intermediate_stack_loop:
#ifdef HAS_SPE
evstdd r0, 0(r3)
evstdd r0, 8(r3)
evstdd r0, 16(r3)
evstdd r0, 24(r3)
#else
stw r0, 0(r3)
stw r0, 4(r3)
stw r0, 8(r3)
stw r0, 12(r3)
stw r0, 16(r3)
stw r0, 20(r3)
stw r0, 24(r3)
stw r0, 28(r3)
#endif
addi r3, r3, 32
cmpw cr7, r3, r4
bne cr7, zero_intermediate_stack_loop
subi r1, r3, 16
#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
/* Next steps in C */
bl mpc55xx_start_early
/* Initialize start stack */
LA r1, start_stack_end
subi r1, r1, 16
li r0, 0
stw r0, 0(r1)
/*
* Load sections. This must be performed after the stack switch
* because it may overwrite the initial stack.
*/
LA r3, bsp_section_fast_text_begin
LA r4, bsp_section_fast_text_load_begin
LA r5, bsp_section_fast_text_size
bl mpc55xx_start_load_section
LA r3, bsp_section_fast_data_begin
LA r4, bsp_section_fast_data_load_begin
LA r5, bsp_section_fast_data_size
bl mpc55xx_start_load_section
LA r3, bsp_section_data_begin
LA r4, bsp_section_data_load_begin
LA r5, bsp_section_data_size
bl mpc55xx_start_load_section
/* Set up EABI and SYSV environment */
bl __eabi
/* Clear command line */
li r3, 0
/* Start RTEMS */
bl boot_card
/* Spin around */
twiddle:
b twiddle
mpc55xx_start_mmu_apply_config:
cmpwi cr7, r4, r0
beqlr cr7
mtctr r4
mmu_init_loop:
lwz r4, 0(r3)
lwz r5, 4(r3)
lwz r6, 8(r3)
lwz r7, 12(r3)
mtspr FSL_EIS_MAS0, r4
mtspr FSL_EIS_MAS1, r5
mtspr FSL_EIS_MAS2, r6
mtspr FSL_EIS_MAS3, r7
tlbwe
addi r3, r3, 16
bdnz mmu_init_loop
blr
mpc55xx_start_load_section:
cmpw cr7, r3, r4
beqlr cr7
b memcpy
/* Start stack area */
.section ".bsp_rwextra", "aw", @nobits
.align 4
.space 4096
start_stack_end:

4
c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am
View File

@@ -8,13 +8,13 @@ dist_project_lib_DATA = startup/bsp_specs
noinst_PROGRAMS =
start.$(OBJEXT): start/start.S
start.$(OBJEXT): ../../../../../../bsps/powerpc/mpc8260ads/start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
project_lib_DATA += linkcmds
rtems_crti.$(OBJEXT): ../shared/start/rtems_crti.S
rtems_crti.$(OBJEXT): ../../../../../../bsps/powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT)

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