forked from Imagelibrary/rtems
bsps: Move start files to bsps
This patch is a part of the BSP source reorganization. Update #3285.
This commit is contained in:
Sebastian Huber
455
bsps/powerpc/virtex5/start/start.S
Normal file
455
bsps/powerpc/virtex5/start/start.S
Normal file
@@ -0,0 +1,455 @@
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/*!@file start.S
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*
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* @brief Initialization code to set up the CPU and call boot_card()
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*
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* This "BSP" targets the Xilinx Virtex XC5VFX70T and related parts. This
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* BSP makes no assumptions on what firmware is loaded into the FPGA.
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*
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* Provides the .entry section code. This is the first code to run in
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* the PPC after download to RAM. Excecution in this case starts at
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* 'download_entry'.
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*
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* The entrypoint 'start' is provided for the case where a bootloader has
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* initialized the CPU, and all that remains to do is to set up a C
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* environment and call boot_card.
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*
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* Derived from virtex dlentry and others.
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*
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* Some portions of this code follow section 3.4 of the PPC440x5 CPU Core User's
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* Manual v7.1 from IBM. Other parts were derived from examples provided
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* by Xilinx in their ML510 Reference Designs, e.g., ml510_bsb1_design_ppc440.
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* See boot.S in standalone/, for example.
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*
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* References:
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* Embedded Processor Block in Virtex-5 FPGAs Reference Guide UG200 (v1.8)
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* http://www.xilinx.com/support/documentation/user_guides/ug200.pdf
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*
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* PowerPC 440x5 Embedded Processor Core User's Manual (Version 7.1)
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* https://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_440_Embedded_Core
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*
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* @author Richard Claus <claus@SLAC.Stanford.edu>
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*
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* @date March 4, 2011 -- Created
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*
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* $Revision: 675 $
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*
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* @verbatim Copyright 2011
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* by
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* The Board of Trustees of the
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* Leland Stanford Junior University.
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* All rights reserved.
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*
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* Work supported by the U.S. Department of Energy under contract
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* DE-AC03-76SF00515.
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*
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* Disclaimer Notice
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*
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* The items furnished herewith were developed under the sponsorship
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* of the U.S. Government. Neither the U.S., nor the U.S. D.O.E., nor the
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* Leland Stanford Junior University, nor their employees, makes any war-
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* ranty, express or implied, or assumes any liability or responsibility
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* for accuracy, completeness or usefulness of any information, apparatus,
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* product or process disclosed, or represents that its use will not in-
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* fringe privately-owned rights. Mention of any product, its manufactur-
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* er, or suppliers shall not, nor is it intended to, imply approval, dis-
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* approval, or fitness for any particular use. The U.S. and the Univer-
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* sity at all times retain the right to use and disseminate the furnished
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* items for any purpose whatsoever. Notice 91 02 01
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*
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* @endverbatim
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*/
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#include <rtems/asm.h>
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#include <rtems/powerpc/powerpc.h>
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#include <rtems/powerpc/registers.h>
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#define V_TS_SZ_I 0x0290 // V,TS=0(Inst),SIZE=9,TID=0
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#define V_TS_SZ_D 0x0390 // V,TS=1(Data),SIZE=9,TID=0
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#define WIMG_U_S_0 0x043F // !(U0-3),!W, I,!M,!G,!E,UX,UW,UR,SX,SW,SR
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#define WIMG_U_S_1 0x003F // !(U0-3),!W,!I,!M,!G,!E,UX,UW,UR,SX,SW,SR
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#define PAGE_SZ 0x10000000 // 256 MB
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/*
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* The virtex ELF link scripts support some special sections:
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* .entry The actual entry point
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* .vectors The section containing the interrupt entry veneers.
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*/
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/*
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* Downloaded code loads the vectors separately to 0x00000100,
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* so .entry can be over 256 bytes.
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*
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* The other sections are linked in the following order:
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* .entry
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* .text
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* .data
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* .bss
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* see linker command file for section placement
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*
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* The initial stack is set to __stack_base
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*
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* All the entry veneer has to do is to clear the BSS.
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*/
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.section .entry
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PUBLIC_VAR(download_entry)
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PUBLIC_VAR(__rtems_entry_point)
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SYM(download_entry):
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SYM(__rtems_entry_point):
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b startupDL /* Entry point used by xmd dow command */
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PUBLIC_VAR (start)
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SYM(start):
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b startupBL /* Entry point used by bootLoader */
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base_addr:
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/*-------------------------------------------------------------------
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* Parameters from linker
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*-----------------------------------------------------------------*/
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toc_pointer:
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.long __got_start
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bss_length:
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.long __bss_size
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bss_addr:
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.long __bss_start
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stack_top:
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.long __stack_base
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.eject
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/*------------------------------------------------------------------
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* This code follows section 3.4 of the PPC440x5 CPU Core User's
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* Manual. The numbers in the comments refer to the step numbers
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* therein. Some of the implementation comes from examples provided
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* by Xilinx in their ML510 Reference Designs, e.g.,
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* ml510_bsb1_design_ppc440. See boot.S in standalone/.
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*------------------------------------------------------------------*/
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/*------------------------------------------------------------------
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* This code is designed to accomodate warm restarts, in which the
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* application software triggers the restart of the system by branching
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* to the following code (either boot or boot1) without causing
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* one of the hardware resets: core, chip, system or JTAG (section
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* 3.2,3 in the Power PC 440-S Embedded Processor Core User's Manual).
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*-----------------------------------------------------------------*/
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/* -----------------------------------------------------------------
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* Setup CPU
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*-----------------------------------------------------------------*/
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first: li r0,0 // Clear r0
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/* -----------------------------------------------------------------
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* Initialize the memory system.
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*------------------------------------------------------------------*/
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iccci r0,r0 // 2. Invalidate instruction cache
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dccci r0,r0 // 3. Invalidate data cache
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msync // 4. Force in-progress data PLB ops to complete
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mfdbcr0 r2 // 5. Disable all debug events
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lis r3,0x8100
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and r2,r2,r3 // Ignore EDM,TRAP to allow XMD use
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mtdbcr0 r2
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li r2,-1
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mtdbsr r2 // 6. Initialize all debug event status
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/*------------------------------------------------------------------
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* Set Core Configuration Register 0 as follows:
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* sum: 0x00206000
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* bit 1 off Parity Recovery Enable
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* bit 4 off Cache Read Parity Enable
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* bit 10 on Disable Store Gathering
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* bit 11 off Disable APU Instruction Broadcast
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* bit 16 off Disable Trace Broadcast
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* bit 17:18 on Specifies behaviour of icbt,dcbt/dcbtst insts
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* bit 23 off Force Load/Store Alignment
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* bit 28:29 off Instruction Cache Speculative Line Count
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* bit 30:31 off Instruction Cache Speculative Line Threshold
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* NB: UG200/pg 21: Spec. prefetching must be disabled
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*------------------------------------------------------------------*/
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lis r2, 0x00206000@h // 7. Set CCR0: DSTG
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ori r2,r2,0x00206000@l // Set CCR0: GDCBT, GICBT
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mtccr0 r2 // Configure CCR0
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mtspr PPC440_CCR1,r0 // 8. Clear CCR1
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/*------------------------------------------------------------------
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* 9. Configure cache regions
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*------------------------------------------------------------------*/
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mtspr PPC440_INV0,r0
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mtspr PPC440_INV1,r0
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mtspr PPC440_INV2,r0
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mtspr PPC440_INV3,r0
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mtspr PPC440_DNV0,r0
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mtspr PPC440_DNV1,r0
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mtspr PPC440_DNV2,r0
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mtspr PPC440_DNV3,r0
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mtspr PPC440_ITV0,r0
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mtspr PPC440_ITV1,r0
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mtspr PPC440_ITV2,r0
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mtspr PPC440_ITV3,r0
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mtspr PPC440_DTV0,r0
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mtspr PPC440_DTV1,r0
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mtspr PPC440_DTV2,r0
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mtspr PPC440_DTV3,r0
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/*------------------------------------------------------------------
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* Cache victim limits
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* floors 0, ceiling max to use the entire cache -- nothing locked
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*------------------------------------------------------------------*/
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lis r2, 0x0001f800@h
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ori r2,r2,0x0001f800@l
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mtspr PPC440_IVLIM,r2
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mtspr PPC440_DVLIM,r2
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/*------------------------------------------------------------------
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* Configure instruction and data cache regions:
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* Set up register constants (r6,r7), page index (r5), address
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* variable (r4), EPN_V_TS bits (r3)
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*
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* Word 0 bits: 0xX0000290, 0xX0000390
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* Bits Field Inst Data Description
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* 0:21 EPN 0-15 0-15 Effective Page Number
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* 22 V 1 1 Valid
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* 23 TS 0 1 Translation Address Space
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* 24:27 SIZE 9 9 Page Size (9 = 256 MB)
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* 38:31 TPAR 0 0 Tag Parity
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* 32:39 TID 0 0 Translation ID (in the MMUCR)
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*
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* Word 1 bits: 0x00000000, 0x00000000
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* Bits Field Inst Data Description
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* 0:21 RPN 0 0 Real Page Number
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* 22:23 PAR1 0 0 Parity for TLB word 1
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* 28:31 ERPN 0 0 Extended Real Page Number
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*
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* Word 2 bits: 0x0000043f, 0x00000c3f
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* Bits Field Inst Data Description
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* 0: 1 PAR2 0 0 Parity for TLB word 2
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* 16 U0 0 0 User-Defineable Storage Attribute 0
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* 17 U1 0 0 User-Defineable Storage Attribute 1
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* 18 U2 0 0 User-Defineable Storage Attribute 2
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* 19 U3 0 0 User-Defineable Storage Attribute 3
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* 20 W 0 0 Write-Through
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* 21 I 1 1 Caching Inhibited
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* 22 M 0 0 Memory Coherence Required
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* 23 G 0 0 Guarded
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* 24 E 0 0 Endian
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* 26 UX 1 1 User State Execute Enable
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* 27 UW 1 1 User State Write Enable
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* 28 UR 1 1 User State Read Enable
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* 29 SX 1 1 Supervisor State Execute Enable
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* 30 SW 1 1 Supervisor State Write Enable
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* 31 SR 1 1 Supervisor State Read Enable
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*------------------------------------------------------------------*/
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mtspr PPC440_MMUCR,r0 // 10a. Clear MMUCR
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li r7,WIMG_U_S_1 // Word 2: Pages are NOT cache inhibited
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lis r6, PAGE_SZ@h // Page size constant
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ori r6,r6,PAGE_SZ@l
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mr r5,r0 // TLB entry index
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mr r4,r0 // Initialize RPN to zero
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mflr r28 // Save return address
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bl tlbSetup // 10b. Set up the TLBs
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mtlr r28 // Restore return address
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/*------------------------------------------------------------------
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* Select whether Wait Enable, interrupts/exceptions and which address
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* spaces should be enabled when application starts
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*------------------------------------------------------------------*/
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lis r3, 0x00000000@h // 10d. MSR[IS]=0 MSR[DS]=0
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ori r3,r3,0x00000000@l
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mtsrr1 r3
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mtsrr0 r28 // Return address
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rfi // Context synchronize to invalidate shadow TLB contents
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/*-------------------------------------------------------------------
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* Entry point used when downloaded, e.g. through XMD
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*------------------------------------------------------------------*/
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startupDL:
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/*-------------------------------------------------------------------
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* Do initialization up to the point where a context sync is required
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*------------------------------------------------------------------*/
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bl first // Do first things first
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/*-------------------------------------------------------------------
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* 11. Tell the processor where the exception vector table will be
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*------------------------------------------------------------------*/
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.extern SYM(__vectors)
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lis r1, __vectors@h /* set EVPR exc. vector prefix */
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mtspr BOOKE_IVPR,r1
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/*------------------------------------------------------------------
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* Set up default exception and interrupt vectors
|
||||
*------------------------------------------------------------------*/
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li r1,0
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mtivor0 r1
|
||||
addi r1,r1,0x10
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||||
mtivor1 r1
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||||
addi r1,r1,0x10
|
||||
mtivor2 r1
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||||
addi r1,r1,0x10
|
||||
mtivor3 r1
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addi r1,r1,0x10
|
||||
mtivor4 r1
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||||
addi r1,r1,0x10
|
||||
mtivor5 r1
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||||
addi r1,r1,0x10
|
||||
mtivor6 r1
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||||
addi r1,r1,0x10
|
||||
mtivor7 r1
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||||
addi r1,r1,0x10
|
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mtivor8 r1
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||||
addi r1,r1,0x10
|
||||
mtivor9 r1
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||||
addi r1,r1,0x10
|
||||
mtivor10 r1
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||||
addi r1,r1,0x10
|
||||
mtivor11 r1
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||||
addi r1,r1,0x10
|
||||
mtivor12 r1
|
||||
addi r1,r1,0x10
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||||
mtivor13 r1
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||||
addi r1,r1,0x10
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||||
mtivor14 r1
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||||
addi r1,r1,0x10
|
||||
mtivor15 r1
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* 12. Configure debug facilities
|
||||
*------------------------------------------------------------------*/
|
||||
mtdbcr1 r0
|
||||
mtdbcr2 r0
|
||||
mtiac1 r0
|
||||
mtiac2 r0
|
||||
mtiac3 r0
|
||||
mtiac4 r0
|
||||
mtdac1 r0
|
||||
mtdac2 r0
|
||||
mtdvc1 r0
|
||||
mtdvc2 r0
|
||||
mfdbcr0 r2 // Freeze timers on debug events
|
||||
ori r2,r2,0x0001
|
||||
mtdbcr0 r2
|
||||
isync
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* 13. Configure timer facilities
|
||||
*------------------------------------------------------------------*/
|
||||
mtdec r0 // Clear Decrementer to prevent exception
|
||||
mttbl r0 // Clear Timebase to prevent Fixed Interval..
|
||||
mttbu r0 // ..timer and Watchdog Timer exceptions
|
||||
mtpit r0 // Programmable interval timer
|
||||
li r2,-1 // -1 to clear TSR
|
||||
mttsr r2 // Timer status register
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* Clear out stale values in certain registers to avoid confusion
|
||||
*------------------------------------------------------------------*/
|
||||
mtcrf 0xff,r0 // Need for simulation
|
||||
mtctr r0 // Counter register
|
||||
mtxer r0 // Fixed-point exception register
|
||||
mtesr r0 // Exception syndrome register
|
||||
mtdear r0 // Data exception address register
|
||||
mtmcsr r0 // Machine check syndrome register
|
||||
|
||||
/* Fall through */
|
||||
|
||||
/* -------------------------------------------------------------------
|
||||
* If a bootloader has run that has already initialized the CPU,
|
||||
* which among other things has loaded this code into memory and
|
||||
* jumped to start above, the initialization above does not need
|
||||
* to be redone. Execution thus resumes here.
|
||||
*------------------------------------------------------------------*/
|
||||
|
||||
startupBL:
|
||||
/*-------------------------------------------------------------------
|
||||
* Load the parameter table base address
|
||||
*------------------------------------------------------------------*/
|
||||
lis r1, base_addr@h
|
||||
ori r1,r1,base_addr@l
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* Setup stack for RTEMS and call boot_card(). From this
|
||||
* point forward registers will be used in accordance with the
|
||||
* PowerPC EABI.
|
||||
*
|
||||
* boot_card() supervises the initialization of RTEMS and the C
|
||||
* library. It calls bsp_start(), bsp_predriver_hook(), etc.
|
||||
*------------------------------------------------------------------*/
|
||||
lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */
|
||||
lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */
|
||||
|
||||
/* Align as required by ABI */
|
||||
li r3,PPC_STACK_ALIGNMENT-1
|
||||
andc r1,r1,r3
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* Set up r2 and r13. Upon entry r1 must have a nonzero value
|
||||
* as it will be stored in an "init done" flag. Stupid but true.
|
||||
* r1 must also be set up as a stack pointer as __eabi() jumps
|
||||
* to __init() which has a standard function prolog.
|
||||
*------------------------------------------------------------------*/
|
||||
bl __eabi /* setup EABI and SYSV environment */
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* Zero the .bss, .sbss and .sbss2 sections.
|
||||
* Must have r2 and r13 properly set.
|
||||
*------------------------------------------------------------------*/
|
||||
bl zero_bss /* Assume Bank regs set up..., cache etc. */
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* Create a minimal stack frame for this code, the caller of boot_card().
|
||||
*------------------------------------------------------------------*/
|
||||
addi r1,r1,-PPC_MINIMUM_STACK_FRAME_SIZE
|
||||
|
||||
xor r3,r3,r3 /* Clear r3 */
|
||||
stw r3,0(r1) /* Clear stack chain */
|
||||
stw r3,4(r1)
|
||||
stw r3,8(r1)
|
||||
stw r3,12(r1)
|
||||
lis r5,environ@ha
|
||||
la r5,environ@l(r5) /* environp */
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* Call boot_card() with its arguments, the command-line pointer and
|
||||
* the argument count, set to NULL.
|
||||
*------------------------------------------------------------------*/
|
||||
li r4,0 /* argv */
|
||||
li r3,0 /* argc */
|
||||
.extern SYM (boot_card)
|
||||
b SYM (boot_card) /* call the first C routine */
|
||||
|
||||
|
||||
.eject
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* Set up TLB entries: 2 entries are needed for the same 256MB page
|
||||
* one for instruction memory and the other for data memory.
|
||||
* (TS bit=0 for instructions)
|
||||
*------------------------------------------------------------------*/
|
||||
tlbSetup:
|
||||
1: ori r3,r4,V_TS_SZ_I // Fold V_TS_SZ in with EPN=RPN
|
||||
tlbwe r3,r5,0 // Word 0: EPN_V_TS_SZ (Instructions)
|
||||
tlbwe r4,r5,1 // Word 1: RPN_ERPN
|
||||
tlbwe r7,r5,2 // Word 2: WIMG_U_S
|
||||
ori r3,r4,V_TS_SZ_D // Fold V_TS_SZ in with EPN=RPN
|
||||
addi r5,r5,1 // Next TLB entry
|
||||
tlbwe r3,r5,0 // Word 0: EPN_V_TS_SZ (Data)
|
||||
tlbwe r4,r5,1 // Word 1: RPN_ERPN
|
||||
tlbwe r7,r5,2 // Word 2: WIMG_U_S
|
||||
add r4,r4,r6 // Increment RPN to next 256MB block
|
||||
addi r5,r5,1 // Next TLB entry
|
||||
cmpwi r5,32 // Done yet?
|
||||
bne 1b
|
||||
li r0,0
|
||||
2: // Zero out index 32-63 TLB entries
|
||||
tlbwe r0,r5,0
|
||||
tlbwe r0,r5,1
|
||||
tlbwe r0,r5,2
|
||||
addi r5,r5,1
|
||||
cmpwi r5,64
|
||||
bne 2b
|
||||
|
||||
blr
|
||||
Reference in New Issue
Block a user