forked from Imagelibrary/rtems
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support. * include/tm27.h: New.
This commit is contained in:
Ralf Corsepius
@@ -1,3 +1,8 @@
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2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
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* include/bsp.h: Split out tmtest27 support.
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* include/tm27.h: New.
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2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
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PR 613/bsps
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@@ -53,68 +53,6 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
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#define RTEMS_BSP_NETWORK_DRIVER_NAME "sonic1"
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#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_erc32_sonic_driver_attach
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/*
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* Define the interrupt mechanism for Time Test 27
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*
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* NOTE: Since the interrupt code for the SPARC supports both synchronous
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* and asynchronous trap handlers, support for testing with both
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* is included.
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*/
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#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0
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/*
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* The synchronous trap is an arbitrarily chosen software trap.
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*/
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#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1)
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#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 );
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#define Cause_tm27_intr() \
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asm volatile( "ta 0x10; nop " );
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#define Clear_tm27_intr()
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#define Lower_tm27_intr()
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/*
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* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
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*/
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#else /* use a regular asynchronous trap */
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#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
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#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
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#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
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#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 ); \
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set_vector( (handler), TEST_VECTOR2, 1 );
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#define Cause_tm27_intr() \
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do { \
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ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
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nop(); \
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nop(); \
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nop(); \
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} while (0)
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#define Clear_tm27_intr() \
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ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
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#define Lower_tm27_intr()
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#endif
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/*
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* Simple spin delay in microsecond units for device drivers.
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* This is very dependent on the clock speed of the target.
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80
c/src/lib/libbsp/sparc/erc32/include/tm27.h
Normal file
80
c/src/lib/libbsp/sparc/erc32/include/tm27.h
Normal file
@@ -0,0 +1,80 @@
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/*
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* tm27.h
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#ifndef _TMTEST27
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#error "This is an RTEMS internal file you must not include directly."
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#endif
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#ifndef __tm27_h
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#define __tm27_h
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/*
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* Define the interrupt mechanism for Time Test 27
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*
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* NOTE: Since the interrupt code for the SPARC supports both synchronous
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* and asynchronous trap handlers, support for testing with both
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* is included.
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*/
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#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0
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/*
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* The synchronous trap is an arbitrarily chosen software trap.
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*/
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#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1)
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#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 );
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#define Cause_tm27_intr() \
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asm volatile( "ta 0x10; nop " );
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#define Clear_tm27_intr()
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#define Lower_tm27_intr()
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/*
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* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
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*/
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#else /* use a regular asynchronous trap */
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#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
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#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
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#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
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#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 ); \
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set_vector( (handler), TEST_VECTOR2, 1 );
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#define Cause_tm27_intr() \
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do { \
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ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
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nop(); \
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nop(); \
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nop(); \
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} while (0)
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#define Clear_tm27_intr() \
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ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
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#define Lower_tm27_intr()
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#endif
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#endif
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@@ -1,3 +1,8 @@
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2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
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* include/bsp.h: Split out tmtest27 support.
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* include/tm27.h: New.
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2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
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PR 613/bsps
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@@ -53,67 +53,6 @@ extern int rtems_leon_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *conf
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#define RTEMS_BSP_NETWORK_DRIVER_NAME "open_eth1"
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#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_leon_open_eth_driver_attach
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/*
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* Define the interrupt mechanism for Time Test 27
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*
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* NOTE: Since the interrupt code for the SPARC supports both synchronous
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* and asynchronous trap handlers, support for testing with both
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* is included.
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*/
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#define SIS_USE_SYNCHRONOUS_TRAP 0
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/*
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* The synchronous trap is an arbitrarily chosen software trap.
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*/
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#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
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#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 );
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#define Cause_tm27_intr() \
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asm volatile( "ta 0x10; nop " );
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#define Clear_tm27_intr()
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#define Lower_tm27_intr()
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/*
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* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
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*/
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#else /* use a regular asynchronous trap */
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#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1
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#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
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#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1
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#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 ); \
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set_vector( (handler), TEST_VECTOR2, 1 );
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#define Cause_tm27_intr() \
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do { \
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LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \
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nop(); \
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nop(); \
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nop(); \
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} while (0)
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#define Clear_tm27_intr() \
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LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE )
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#define Lower_tm27_intr()
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#endif
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/*
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* Simple spin delay in microsecond units for device drivers.
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* This is very dependent on the clock speed of the target.
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79
c/src/lib/libbsp/sparc/leon/include/tm27.h
Normal file
79
c/src/lib/libbsp/sparc/leon/include/tm27.h
Normal file
@@ -0,0 +1,79 @@
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/*
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* tm27.h
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#ifndef _TMTEST27
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#error "This is an RTEMS internal file you must not include directly."
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#endif
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#ifndef __tm27_h
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#define __tm27_h
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/*
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* Define the interrupt mechanism for Time Test 27
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*
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* NOTE: Since the interrupt code for the SPARC supports both synchronous
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* and asynchronous trap handlers, support for testing with both
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* is included.
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*/
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#define SIS_USE_SYNCHRONOUS_TRAP 0
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/*
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* The synchronous trap is an arbitrarily chosen software trap.
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*/
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#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
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#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 );
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#define Cause_tm27_intr() \
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asm volatile( "ta 0x10; nop " );
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#define Clear_tm27_intr()
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#define Lower_tm27_intr()
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/*
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* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
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*/
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#else /* use a regular asynchronous trap */
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#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1
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#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
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#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1
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#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 ); \
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set_vector( (handler), TEST_VECTOR2, 1 );
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#define Cause_tm27_intr() \
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do { \
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LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \
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nop(); \
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nop(); \
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nop(); \
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} while (0)
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#define Clear_tm27_intr() \
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LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE )
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#define Lower_tm27_intr()
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#endif
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#endif
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