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2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>

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* include/bsp.h: Split out tmtest27 support.
	* include/tm27.h: New.
This commit is contained in:
Ralf Corsepius
2004-04-23 02:10:31 +00:00
parent 4133bfe49a
commit f850b756a4
6 changed files with 169 additions and 123 deletions
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5
c/src/lib/libbsp/sparc/erc32/ChangeLog
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@@ -1,3 +1,8 @@
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support.
* include/tm27.h: New.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org> 2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps PR 613/bsps

62
c/src/lib/libbsp/sparc/erc32/include/bsp.h
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@@ -53,68 +53,6 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
#define RTEMS_BSP_NETWORK_DRIVER_NAME "sonic1" #define RTEMS_BSP_NETWORK_DRIVER_NAME "sonic1"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_erc32_sonic_driver_attach #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_erc32_sonic_driver_attach
/*
* Define the interrupt mechanism for Time Test 27
*
* NOTE: Since the interrupt code for the SPARC supports both synchronous
* and asynchronous trap handlers, support for testing with both
* is included.
*/
#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0
/*
* The synchronous trap is an arbitrarily chosen software trap.
*/
#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1)
#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 );
#define Cause_tm27_intr() \
asm volatile( "ta 0x10; nop " );
#define Clear_tm27_intr()
#define Lower_tm27_intr()
/*
* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
*/
#else /* use a regular asynchronous trap */
#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 ); \
set_vector( (handler), TEST_VECTOR2, 1 );
#define Cause_tm27_intr() \
do { \
ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
nop(); \
nop(); \
nop(); \
} while (0)
#define Clear_tm27_intr() \
ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
#define Lower_tm27_intr()
#endif
/* /*
* Simple spin delay in microsecond units for device drivers. * Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target. * This is very dependent on the clock speed of the target.

80
c/src/lib/libbsp/sparc/erc32/include/tm27.h Normal file
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@@ -0,0 +1,80 @@
/*
* tm27.h
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Define the interrupt mechanism for Time Test 27
*
* NOTE: Since the interrupt code for the SPARC supports both synchronous
* and asynchronous trap handlers, support for testing with both
* is included.
*/
#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0
/*
* The synchronous trap is an arbitrarily chosen software trap.
*/
#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1)
#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 );
#define Cause_tm27_intr() \
asm volatile( "ta 0x10; nop " );
#define Clear_tm27_intr()
#define Lower_tm27_intr()
/*
* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
*/
#else /* use a regular asynchronous trap */
#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 ); \
set_vector( (handler), TEST_VECTOR2, 1 );
#define Cause_tm27_intr() \
do { \
ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
nop(); \
nop(); \
nop(); \
} while (0)
#define Clear_tm27_intr() \
ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
#define Lower_tm27_intr()
#endif
#endif

5
c/src/lib/libbsp/sparc/leon/ChangeLog
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@@ -1,3 +1,8 @@
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support.
* include/tm27.h: New.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org> 2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps PR 613/bsps

61
c/src/lib/libbsp/sparc/leon/include/bsp.h
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@@ -53,67 +53,6 @@ extern int rtems_leon_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *conf
#define RTEMS_BSP_NETWORK_DRIVER_NAME "open_eth1" #define RTEMS_BSP_NETWORK_DRIVER_NAME "open_eth1"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_leon_open_eth_driver_attach #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_leon_open_eth_driver_attach
/*
* Define the interrupt mechanism for Time Test 27
*
* NOTE: Since the interrupt code for the SPARC supports both synchronous
* and asynchronous trap handlers, support for testing with both
* is included.
*/
#define SIS_USE_SYNCHRONOUS_TRAP 0
/*
* The synchronous trap is an arbitrarily chosen software trap.
*/
#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 );
#define Cause_tm27_intr() \
asm volatile( "ta 0x10; nop " );
#define Clear_tm27_intr()
#define Lower_tm27_intr()
/*
* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
*/
#else /* use a regular asynchronous trap */
#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1
#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1
#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 ); \
set_vector( (handler), TEST_VECTOR2, 1 );
#define Cause_tm27_intr() \
do { \
LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \
nop(); \
nop(); \
nop(); \
} while (0)
#define Clear_tm27_intr() \
LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE )
#define Lower_tm27_intr()
#endif
/* /*
* Simple spin delay in microsecond units for device drivers. * Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target. * This is very dependent on the clock speed of the target.

79
c/src/lib/libbsp/sparc/leon/include/tm27.h Normal file
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@@ -0,0 +1,79 @@
/*
* tm27.h
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Define the interrupt mechanism for Time Test 27
*
* NOTE: Since the interrupt code for the SPARC supports both synchronous
* and asynchronous trap handlers, support for testing with both
* is included.
*/
#define SIS_USE_SYNCHRONOUS_TRAP 0
/*
* The synchronous trap is an arbitrarily chosen software trap.
*/
#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 );
#define Cause_tm27_intr() \
asm volatile( "ta 0x10; nop " );
#define Clear_tm27_intr()
#define Lower_tm27_intr()
/*
* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
*/
#else /* use a regular asynchronous trap */
#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1
#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1
#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 ); \
set_vector( (handler), TEST_VECTOR2, 1 );
#define Cause_tm27_intr() \
do { \
LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \
nop(); \
nop(); \
nop(); \
} while (0)
#define Clear_tm27_intr() \
LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE )
#define Lower_tm27_intr()
#endif
#endif