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bsp/lpc24xx: Simplify EMC configuration

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This commit is contained in:
Sebastian Huber
2012-06-11 08:51:32 +02:00
parent d40b09d7e8
commit f7deb58df0
3 changed files with 116 additions and 124 deletions
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14
c/src/lib/libbsp/arm/lpc24xx/include/start-config.h
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@@ -34,6 +34,20 @@
extern "C" { extern "C" {
#endif /* __cplusplus */ #endif /* __cplusplus */
/**
* @brief Pico seconds @a ps to clock ticks for clock frequency @a f.
*/
#define LPC24XX_PS_TO_CLK(ps, f) \
(((((uint64_t) (ps)) * ((uint64_t) (f))) + 1000000000000ULL - 1ULL) \
/ 1000000000000ULL)
/**
* @brief Pico seconds @a ps to EMCCLK clock ticks adjusted by @a m.
*/
#define LPC24XX_PS_TO_EMCCLK(ps, m) \
(LPC24XX_PS_TO_CLK(ps, LPC24XX_EMCCLK) > (m) ? \
LPC24XX_PS_TO_CLK(ps, LPC24XX_EMCCLK) - (m) : 0)
typedef struct { typedef struct {
uint32_t refresh; uint32_t refresh;
uint32_t readconfig; uint32_t readconfig;

174
c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
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@@ -7,7 +7,7 @@
*/ */
/* /*
* Copyright (c) 2011 embedded brains GmbH. All rights reserved. * Copyright (c) 2011-2012 embedded brains GmbH. All rights reserved.
* *
* embedded brains GmbH * embedded brains GmbH
* Obere Lagerstr. 30 * Obere Lagerstr. 30
@@ -28,8 +28,8 @@ BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
#if defined(LPC24XX_EMC_MT48LC4M16A2) #if defined(LPC24XX_EMC_MT48LC4M16A2)
/* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */ /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
{ {
/* Auto-refresh command every 15.6 us */ /* 15.6 us */
.refresh = 0x46, .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
/* Use command delayed strategy */ /* Use command delayed strategy */
.readconfig = 1, .readconfig = 1,
@@ -68,82 +68,82 @@ BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
.tmrd = 1 .tmrd = 1
} }
#elif defined(LPC24XX_EMC_IS42S32800D7) #elif defined(LPC24XX_EMC_IS42S32800D7)
/* Dynamic Memory 0: ISSI IS42S32800D7 at 51612800Hz (tCK = 19.4ns) */ /* Dynamic Memory 0: ISSI IS42S32800D7 */
{ {
/* (n * 16) clock cycles -> 15.5us <= 15.6 us */ /* 15.6 us */
.refresh = 50, .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
/* Use command delayed strategy */ /* Use command delayed strategy */
.readconfig = 1, .readconfig = 1,
/* (n + 1) clock cycles -> 38.8ns >= 20ns */ /* 20ns */
.trp = 1, .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
/* (n + 1) clock cycles -> 58.1ns >= 45ns */ /* 45ns */
.tras = 2, .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
/* (n + 1) clock cycles -> 77.5ns >= 70ns (tXSR) */ /* 70ns (tXSR) */
.tsrex = 3, .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 1) clock cycles -> 38.8ns >= 20ns (tRCD) */ /* 20ns (tRCD) */
.tapr = 1, .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
/* n clock cycles -> 38.8ns >= 35ns */ /* n clock cycles -> 38.8ns >= 35ns */
.tdal = 2, .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0),
/* (n + 1) clock cycles = 19.4ns >= 14ns (tDPL) */ /* 14ns (tDPL) */
.twr = 0, .twr = LPC24XX_PS_TO_EMCCLK(14000, 1),
/* (n + 1) clock cycles = 77.5ns >= 67.5ns */ /* 67.5ns */
.trc = 3, .trc = LPC24XX_PS_TO_EMCCLK(67500, 1),
/* (n + 1) clock cycles = 77.5ns >= 67.5ns (tRC) */ /* 67.5ns (tRC) */
.trfc = 3, .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1),
/* (n + 1) clock cycles = 77.5ns >= 70ns */ /* 70ns */
.txsr = 3, .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 1) clock cycles = 19.4ns >= 14ns */ /* 14ns */
.trrd = 0, .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
/* (n + 1) clock cycles = 19.4ns >= 14ns */ /* 14ns */
.tmrd = 0 .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1)
} }
#elif defined(LPC24XX_EMC_W9825G2JB75I) #elif defined(LPC24XX_EMC_W9825G2JB75I)
/* Dynamic Memory 0: Winbond W9825G2JB75I at 51612800Hz (tCK = 19.4ns) */ /* Dynamic Memory 0: Winbond W9825G2JB75I */
{ {
/* (n * 16) clock cycles -> 15.5us <= 15.6 us */ /* 15.6 us */
.refresh = 50, .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
/* Use command delayed strategy */ /* Use command delayed strategy */
.readconfig = 1, .readconfig = 1,
/* (n + 1) clock cycles -> 38.8ns >= 20ns */ /* 20ns */
.trp = 1, .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
/* (n + 1) clock cycles -> 58.1ns >= 45ns */ /* 45ns */
.tras = 2, .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
/* (n + 1) clock cycles -> 77.5ns >= 75ns (tXSR) */ /* 75ns (tXSR) */
.tsrex = 3, .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
/* (n + 1) clock cycles -> 38.8ns >= 20ns (tRCD) */ /* 20ns (tRCD) */
.tapr = 1, .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
/* n clock cycles -> 77.5ns >= tWR + tRP -> 2 * tCK + 20ns */ /* tWR + tRP -> 2 * tCK + 20ns */
.tdal = 4, .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
/* (n + 1) clock cycles == 2 * tCK */ /* (n + 1) clock cycles == 2 * tCK */
.twr = 1, .twr = 1,
/* (n + 1) clock cycles = 77.5ns >= 65ns */ /* 65ns */
.trc = 3, .trc = LPC24XX_PS_TO_EMCCLK(65000, 1),
/* (n + 1) clock cycles = 77.5ns >= 65ns (tRC) */ /* 65ns (tRC) */
.trfc = 3, .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1),
/* (n + 1) clock cycles = 77.5ns >= 75ns */ /* 75ns */
.txsr = 3, .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1),
/* (n + 1) clock cycles == 2 * tCK */ /* (n + 1) clock cycles == 2 * tCK */
.trrd = 1, .trrd = 1,
@@ -168,71 +168,49 @@ BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
.tmrd = 2 .tmrd = 2
} }
#elif defined(LPC24XX_EMC_IS42S32800B) #elif defined(LPC24XX_EMC_IS42S32800B)
#if LPC24XX_EMCCLK == 72000000U {
{ /* 15.6us */
/* tCK = 13.888ns at 72MHz */ .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
/* (n * 16) clock cycles -> 15.556us <= 15.6us */ /* Use command delayed strategy */
.refresh = 70, .readconfig = 1,
.readconfig = 1, /* 20ns */
.trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
/* (n + 1) clock cycles -> 27.8ns >= 20ns */ /* 45ns */
.trp = 1, .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
/* (n + 1) clock cycles -> 55.5ns >= 45ns */ /* 70ns (tRC) */
.tras = 3, .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 1) clock cycles -> 69.4ns >= 70ns (tRC) */ /* FIXME */
.tsrex = 5, .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1),
/* (n + 1) clock cycles -> 41.7ns >= FIXME */ /* tWR + tRP -> 2 * tCK + 20ns */
.tapr = 2, .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
/* n clock cycles -> 55.5ns >= tWR + tRP = 47.8ns */ /* (n + 1) clock cycles == 2 * tCK */
.tdal = 4, .twr = 1,
/* (n + 1) clock cycles == 2 * tCK */ /* 70ns */
.twr = 1, .trc = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 1) clock cycles -> 83.3ns >= 70ns */ /* 70ns */
.trc = 5, .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 1) clock cycles -> 83.3ns >= 70ns */ /* 70ns (tRC) */
.trfc = 5, .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 1) clock cycles -> 69.4ns >= 70ns (tRC) */ /* 14ns */
.txsr = 5, .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
/* (n + 1) clock cycles -> 27.8ns >= 14ns */ /* (n + 1) clock cycles == 2 * tCK */
.trrd = 1, .tmrd = 1,
/* (n + 1) clock cycles == 2 * tCK */ /* FIXME */
.tmrd = 1, .emcdlyctl = 0x1112
}
/* FIXME */
.emcdlyctl = 0x1112
}
#elif LPC24XX_EMCCLK == 60000000U
{
.refresh = 0x3a,
.readconfig = 1,
.trp = 1,
.tras = 3,
.tsrex = 5,
.tapr = 2,
.tdal = 3,
.twr = 1,
.trc = 4,
.trfc = 4,
.txsr = 5,
.trrd = 1,
.tmrd = 1,
.emcdlyctl = 0x1112
}
#else
#error "unexpected EMCCLK"
#endif
#endif #endif
}; };

52
c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-static.c
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@@ -65,7 +65,7 @@ BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
} }
} }
#elif defined(LPC24XX_EMC_M29W320E70) #elif defined(LPC24XX_EMC_M29W320E70)
/* Static Memory 0: M29W320E70 at 51612800Hz (tCK = 19.4ns) */ /* Static Memory 0: M29W320E70 */
{ {
.chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0, .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
.config = { .config = {
@@ -75,27 +75,27 @@ BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
*/ */
.config = 0x81, .config = 0x81,
/* (n + 1) clock cycles -> 38.8ns >= 30ns (tWHWL) */ /* 30ns (tWHWL) */
.waitwen = 1, .waitwen = LPC24XX_PS_TO_EMCCLK(30000, 1),
/* (n + 1) clock cycles -> 19.4ns >= 0ns */ /* 0ns */
.waitoen = 0, .waitoen = LPC24XX_PS_TO_EMCCLK(0, 1),
/* (n + 1) clock cycles -> 77.5ns >= 70ns (tAVQV, tELQV) */ /* 70ns (tAVQV, tELQV) */
.waitrd = 3, .waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 1) clock cycles -> 77.5ns >= 70ns (tAVQV, tELQV) */ /* 70ns (tAVQV, tELQV) */
.waitpage = 3, .waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 2) clock cycles -> 58.1ns >= 45ns (tWLWH) */ /* 45ns (tWLWH) */
.waitwr = 1, .waitwr = LPC24XX_PS_TO_EMCCLK(45000, 2),
/* (n + 1) clock cycles -> 38.8ns >= 25ns (tEHQZ) */ /* 25ns (tEHQZ) */
.waitrun = 1 .waitrun = LPC24XX_PS_TO_EMCCLK(25000, 1)
} }
} }
#elif defined(LPC24XX_EMC_SST39VF3201) #elif defined(LPC24XX_EMC_SST39VF3201)
/* Static Memory 0: SST39VF3201 at 51612800Hz (tCK = 19.4ns) */ /* Static Memory 0: SST39VF3201 */
{ {
.chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0, .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
.config = { .config = {
@@ -105,23 +105,23 @@ BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
*/ */
.config = 0x81, .config = 0x81,
/* (n + 1) clock cycles -> 19.4ns >= 0ns (tCS, tAS) */ /* 0ns (tCS, tAS) */
.waitwen = 0, .waitwen = LPC24XX_PS_TO_EMCCLK(0, 1),
/* (n + 1) clock cycles -> 19.4ns >= 0ns (tOES) */ /* 0ns (tOES) */
.waitoen = 0, .waitoen = LPC24XX_PS_TO_EMCCLK(0, 1),
/* (n + 1) clock cycles -> 77.5ns >= 70ns (tRC) */ /* 70ns (tRC) */
.waitrd = 2, .waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 1) clock cycles -> 77.5ns >= 70ns (tRC) */ /* 70ns (tRC) */
.waitpage = 2, .waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1),
/* (n + 2) clock cycles -> 38.8ns >= 20ns (tCHZ, TOHZ) */ /* 20ns (tCHZ, TOHZ) */
.waitwr = 0, .waitwr = LPC24XX_PS_TO_EMCCLK(20000, 2),
/* (n + 1) clock cycles -> 38.8ns >= 20ns (tCHZ, TOHZ) */ /* 20ns (tCHZ, TOHZ) */
.waitrun = 1 .waitrun = LPC24XX_PS_TO_EMCCLK(20000, 1)
} }
} }
#endif #endif