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bsps/sparc: Order load/store by increasing offsets

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This may increase the cache hit performance.
This commit is contained in:
Sebastian Huber
2014-02-04 16:44:50 +01:00
parent a54179d2ba
commit f715433ae9
1 changed files with 7 additions and 7 deletions
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14
c/src/lib/libbsp/sparc/shared/irq_asm.S
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@@ -422,15 +422,15 @@ save_isf:
GET_SELF_CPU_CONTROL %l5, %l7 GET_SELF_CPU_CONTROL %l5, %l7
ld [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6 ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7 ld [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
add %l6, 1, %l6
st %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
add %l7, 1, %l7 add %l7, 1, %l7
st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL] st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
add %l6, 1, %l6
st %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
/* /*
* If ISR nest level was zero (now 1), then switch stack. * If ISR nest level was zero (now 1), then switch stack.
*/ */
@@ -581,11 +581,11 @@ dont_fix_pil2:
* l7 = _ISR_Nest_level value * l7 = _ISR_Nest_level value
*/ */
st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
sub %l6, 1, %l6 sub %l6, 1, %l6
st %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] st %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
/* /*
* If dispatching is disabled (includes nested interrupt case), * If dispatching is disabled (includes nested interrupt case),
* then do a "simple" exit. * then do a "simple" exit.