forked from Imagelibrary/rtems
Implement a generic atomic ops for all UP mode architectures with disable/enable-IRQ function simulated.
This commit is contained in:
WeiY
@@ -60,6 +60,7 @@ include_rtems_score_HEADERS += include/rtems/score/basedefs.h
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if ATOMIC
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include_rtems_score_HEADERS += include/rtems/score/atomic.h
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include_rtems_score_HEADERS += include/rtems/score/genericcpuatomic.h
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include_rtems_score_HEADERS += include/rtems/score/genericatomicops.h
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endif
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if HAS_SMP
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include_rtems_score_HEADERS += include/rtems/score/smplock.h
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274
cpukit/score/include/rtems/score/genericatomicops.h
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274
cpukit/score/include/rtems/score/genericatomicops.h
Normal file
@@ -0,0 +1,274 @@
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/**
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* @file rtems/score/genericatomicops.h
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*
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* This include file includes the general atomic functions
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* for all the uniprocessors or working in UP mode architectures.
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* If the architecture is working at the UP mode, the atomic
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* operations will be simulated by disable/enable-irq functions.
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* Supposing that if the macro "RTEMS_SMP" is defined it works
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* in SMP mode, otherwise UP mode.
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*/
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/*
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* COPYRIGHT (c) 2013 Deng Hengyi.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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*/
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#ifndef _RTEMS_SCORE_GENERAL_ATOMIC_OPS_H
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#define _RTEMS_SCORE_GEMERAL_ATOMIC_OPS_H
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#include <rtems/score/genericcpuatomic.h>
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#include <rtems/score/isr.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup RTEMS generic UP atomic implementation
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*
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*/
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/**@{*/
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/**
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* @brief Atomically load an atomic type value from address @a address.
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*/
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#define ATOMIC_LOAD(NAME, TYPE) \
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RTEMS_INLINE_ROUTINE Atomic_##TYPE _CPU_Atomic_Load_##NAME( \
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volatile Atomic_##TYPE *address \
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) \
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{ \
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Atomic_##TYPE tmp; \
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ISR_Level level; \
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\
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_ISR_Disable( level ); \
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tmp = *address; \
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_ISR_Enable( level ); \
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return tmp; \
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} \
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ATOMIC_LOAD(int, Int);
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ATOMIC_LOAD(acq_int, Int);
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ATOMIC_LOAD(long, Long);
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ATOMIC_LOAD(acq_long, Long);
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ATOMIC_LOAD(ptr, Pointer);
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ATOMIC_LOAD(acq_ptr, Pointer);
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ATOMIC_LOAD(32, Int32);
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ATOMIC_LOAD(acq_32, Int32);
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ATOMIC_LOAD(64, Int64);
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ATOMIC_LOAD(acq_64, Int64);
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/**
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* @brief Atomically store an atomic type value @a value into address @a
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* address.
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*/
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#define ATOMIC_STORE(NAME, TYPE) \
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RTEMS_INLINE_ROUTINE void _CPU_Atomic_Store_##NAME( \
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volatile Atomic_##TYPE *address, \
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Atomic_##TYPE value \
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) \
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{ \
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ISR_Level level; \
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\
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_ISR_Disable( level ); \
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*address = value; \
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_ISR_Enable( level ); \
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} \
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ATOMIC_STORE(int, Int);
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ATOMIC_STORE(rel_int, Int);
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ATOMIC_STORE(long, Long);
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ATOMIC_STORE(rel_long, Long);
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ATOMIC_STORE(ptr, Pointer);
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ATOMIC_STORE(rel_ptr, Pointer);
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ATOMIC_STORE(32, Int32);
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ATOMIC_STORE(rel_32, Int32);
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ATOMIC_STORE(64, Int64);
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ATOMIC_STORE(rel_64, Int64);
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/**
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* @brief Atomically load-add-store an atomic type value @a value into address
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* @a address.
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*/
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#define ATOMIC_FETCH_ADD(NAME, TYPE) \
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RTEMS_INLINE_ROUTINE void _CPU_Atomic_Fetch_add_##NAME( \
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volatile Atomic_##TYPE *address, \
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Atomic_##TYPE value \
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) \
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{ \
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ISR_Level level; \
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\
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_ISR_Disable( level ); \
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*address += value; \
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_ISR_Enable( level ); \
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} \
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ATOMIC_FETCH_ADD(int, Int);
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ATOMIC_FETCH_ADD(acq_int, Int);
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ATOMIC_FETCH_ADD(rel_int, Int);
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ATOMIC_FETCH_ADD(long, Long);
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ATOMIC_FETCH_ADD(acq_long, Long);
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ATOMIC_FETCH_ADD(rel_long, Long);
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ATOMIC_FETCH_ADD(ptr, Pointer);
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ATOMIC_FETCH_ADD(acq_ptr, Pointer);
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ATOMIC_FETCH_ADD(rel_ptr, Pointer);
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ATOMIC_FETCH_ADD(32, Int32);
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ATOMIC_FETCH_ADD(acq_32, Int32);
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ATOMIC_FETCH_ADD(rel_32, Int32);
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ATOMIC_FETCH_ADD(64, Int64);
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ATOMIC_FETCH_ADD(acq_64, Int64);
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ATOMIC_FETCH_ADD(rel_64, Int64);
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/**
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* @brief Atomically load-sub-store an atomic type value @a value into address
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* @a address.
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*/
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#define ATOMIC_FETCH_SUB(NAME, TYPE) \
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RTEMS_INLINE_ROUTINE void _CPU_Atomic_Fetch_sub_##NAME( \
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volatile Atomic_##TYPE *address, \
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Atomic_##TYPE value \
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) \
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{ \
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ISR_Level level; \
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\
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_ISR_Disable( level ); \
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*address -= value; \
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_ISR_Enable( level ); \
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} \
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ATOMIC_FETCH_SUB(int, Int);
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ATOMIC_FETCH_SUB(acq_int, Int);
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ATOMIC_FETCH_SUB(rel_int, Int);
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ATOMIC_FETCH_SUB(long, Long);
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ATOMIC_FETCH_SUB(acq_long, Long);
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ATOMIC_FETCH_SUB(rel_long, Long);
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ATOMIC_FETCH_SUB(ptr, Pointer);
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ATOMIC_FETCH_SUB(acq_ptr, Pointer);
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ATOMIC_FETCH_SUB(rel_ptr, Pointer);
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ATOMIC_FETCH_SUB(32, Int32);
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ATOMIC_FETCH_SUB(acq_32, Int32);
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ATOMIC_FETCH_SUB(rel_32, Int32);
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ATOMIC_FETCH_SUB(64, Int64);
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ATOMIC_FETCH_SUB(acq_64, Int64);
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ATOMIC_FETCH_SUB(rel_64, Int64);
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/**
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* @brief Atomically load-or-store an atomic type value @a value into address
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* @a address.
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*/
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#define ATOMIC_FETCH_OR(NAME, TYPE) \
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RTEMS_INLINE_ROUTINE void _CPU_Atomic_Fetch_or_##NAME( \
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volatile Atomic_##TYPE *address, \
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Atomic_##TYPE value \
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) \
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{ \
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ISR_Level level; \
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\
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_ISR_Disable( level ); \
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*address |= value; \
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_ISR_Enable( level ); \
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} \
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ATOMIC_FETCH_OR(int, Int);
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ATOMIC_FETCH_OR(acq_int, Int);
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ATOMIC_FETCH_OR(rel_int, Int);
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ATOMIC_FETCH_OR(long, Long);
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ATOMIC_FETCH_OR(acq_long, Long);
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ATOMIC_FETCH_OR(rel_long, Long);
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ATOMIC_FETCH_OR(ptr, Pointer);
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ATOMIC_FETCH_OR(acq_ptr, Pointer);
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ATOMIC_FETCH_OR(rel_ptr, Pointer);
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ATOMIC_FETCH_OR(32, Int32);
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ATOMIC_FETCH_OR(acq_32, Int32);
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ATOMIC_FETCH_OR(rel_32, Int32);
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ATOMIC_FETCH_OR(64, Int64);
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ATOMIC_FETCH_OR(acq_64, Int64);
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ATOMIC_FETCH_OR(rel_64, Int64);
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/**
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* @brief Atomically load-and-store an atomic type value @a value into address
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* @a address.
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*/
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#define ATOMIC_FETCH_AND(NAME, TYPE) \
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RTEMS_INLINE_ROUTINE void _CPU_Atomic_Fetch_and_##NAME( \
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volatile Atomic_##TYPE *address, \
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Atomic_##TYPE value \
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) \
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{ \
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ISR_Level level; \
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\
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_ISR_Disable( level ); \
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*address &= value; \
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_ISR_Enable( level ); \
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} \
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ATOMIC_FETCH_AND(int, Int);
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ATOMIC_FETCH_AND(acq_int, Int);
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ATOMIC_FETCH_AND(rel_int, Int);
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ATOMIC_FETCH_AND(long, Long);
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ATOMIC_FETCH_AND(acq_long, Long);
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ATOMIC_FETCH_AND(rel_long, Long);
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ATOMIC_FETCH_AND(ptr, Pointer);
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ATOMIC_FETCH_AND(acq_ptr, Pointer);
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ATOMIC_FETCH_AND(rel_ptr, Pointer);
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ATOMIC_FETCH_AND(32, Int32);
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ATOMIC_FETCH_AND(acq_32, Int32);
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ATOMIC_FETCH_AND(rel_32, Int32);
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ATOMIC_FETCH_AND(64, Int64);
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ATOMIC_FETCH_AND(acq_64, Int64);
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ATOMIC_FETCH_AND(rel_64, Int64);
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/**
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* @brief Atomically compare the value stored at @a address with @a
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* old_value and if the two values are equal, update the value of @a
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* address with @a new_value. Returns zero if the compare failed,
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* nonzero otherwise.
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*/
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#define ATOMIC_COMPARE_EXCHANGE(NAME, TYPE) \
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RTEMS_INLINE_ROUTINE int _CPU_Atomic_Compare_exchange_##NAME( \
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volatile Atomic_##TYPE *address, \
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Atomic_##TYPE old_value, \
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Atomic_##TYPE new_value \
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) \
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{ \
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ISR_Level level; \
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int ret; \
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\
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_ISR_Disable( level ); \
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if (*address == old_value) { \
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*address = new_value; \
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ret = TRUE; \
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} else { \
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ret = FALSE; \
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} \
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_ISR_Enable( level ); \
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\
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return ret; \
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} \
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ATOMIC_COMPARE_EXCHANGE(int, Int);
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ATOMIC_COMPARE_EXCHANGE(acq_int, Int);
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ATOMIC_COMPARE_EXCHANGE(rel_int, Int);
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ATOMIC_COMPARE_EXCHANGE(long, Long);
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ATOMIC_COMPARE_EXCHANGE(acq_long, Long);
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ATOMIC_COMPARE_EXCHANGE(rel_long, Long);
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ATOMIC_COMPARE_EXCHANGE(ptr, Pointer);
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ATOMIC_COMPARE_EXCHANGE(acq_ptr, Pointer);
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ATOMIC_COMPARE_EXCHANGE(rel_ptr, Pointer);
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ATOMIC_COMPARE_EXCHANGE(32, Int32);
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ATOMIC_COMPARE_EXCHANGE(acq_32, Int32);
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ATOMIC_COMPARE_EXCHANGE(rel_32, Int32);
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ATOMIC_COMPARE_EXCHANGE(64, Int64);
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ATOMIC_COMPARE_EXCHANGE(acq_64, Int64);
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ATOMIC_COMPARE_EXCHANGE(rel_64, Int64);
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#ifdef __cplusplus
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}
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#endif
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/**@}*/
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#endif
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/* end of include file */
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@@ -219,6 +219,10 @@ PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/atomic.h
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$(PROJECT_INCLUDE)/rtems/score/genericcpuatomic.h: include/rtems/score/genericcpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/genericcpuatomic.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/genericcpuatomic.h
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$(PROJECT_INCLUDE)/rtems/score/genericatomicops.h: include/rtems/score/genericatomicops.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/genericatomicops.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/genericatomicops.h
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endif
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if HAS_SMP
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$(PROJECT_INCLUDE)/rtems/score/smplock.h: include/rtems/score/smplock.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
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