forked from Imagelibrary/rtems
@@ -118,6 +118,7 @@ void _CPU_Context_Initialize(
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the_ppc_context->gpr1 = sp;
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the_ppc_context->gpr1 = sp;
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the_ppc_context->msr = msr_value;
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the_ppc_context->msr = msr_value;
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the_ppc_context->lr = (uint32_t) entry_point;
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the_ppc_context->lr = (uint32_t) entry_point;
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the_ppc_context->isr_dispatch_disable = 0;
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#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
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#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
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_CPU_Context_initialize_altivec( the_ppc_context );
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_CPU_Context_initialize_altivec( the_ppc_context );
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@@ -109,6 +109,7 @@ void _CPU_Context_Initialize(
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the_context->register_lr = (uint32_t) entry_point;
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the_context->register_lr = (uint32_t) entry_point;
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the_context->register_cpsr = ( ( new_level != 0 ) ? ARM_PSR_I : 0 )
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the_context->register_cpsr = ( ( new_level != 0 ) ? ARM_PSR_I : 0 )
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| arm_cpu_mode;
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| arm_cpu_mode;
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the_context->isr_dispatch_disable = 0;
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#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
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#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
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the_context->thread_id = (uint32_t) tls_area;
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the_context->thread_id = (uint32_t) tls_area;
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@@ -872,6 +872,10 @@ uint32_t _CPU_ISR_Get_level( void );
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* in the context. The state of the "general data" registers is
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* in the context. The state of the "general data" registers is
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* undefined at task start time.
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* undefined at task start time.
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*
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*
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* The ISR dispatch disable field of the context must be cleared to zero if it
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* is used by the CPU port. Otherwise, a thread restart results in
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* unpredictable behaviour.
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*
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* @param[in] _the_context is the context structure to be initialized
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* @param[in] _the_context is the context structure to be initialized
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* @param[in] _stack_base is the lowest physical address of this task's stack
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* @param[in] _stack_base is the lowest physical address of this task's stack
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* @param[in] _size is the size of this task's stack
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* @param[in] _size is the size of this task's stack
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