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2011-05-19 Sebastian Huber <sebastian.huber@embedded-brains.de>

Browse Source 
* shared/lpc/include/lpc-emc.h, shared/lpc/include/lpc-lcd.h: New
	files.
	* shared/lpc/include/lpc-dma.h: API changes.
	* shared/lpc/clock/lpc-clock-config.c: Fixed nano seconds extension.
	* shared/lpc/network/lpc-ethernet.c: Format.  Multicast hash filter
	support.
This commit is contained in:
Sebastian Huber
2011-05-19 12:09:04 +00:00
parent 00d95ce002
commit f6083f08dd
6 changed files with 587 additions and 141 deletions
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9
c/src/lib/libbsp/arm/ChangeLog
View File

@@ -1,3 +1,12 @@
2011-05-19 Sebastian Huber <sebastian.huber@embedded-brains.de>
* shared/lpc/include/lpc-emc.h, shared/lpc/include/lpc-lcd.h: New
files.
* shared/lpc/include/lpc-dma.h: API changes.
* shared/lpc/clock/lpc-clock-config.c: Fixed nano seconds extension.
* shared/lpc/network/lpc-ethernet.c: Format. Multicast hash filter
support.
2011-03-29 Sebastian Huber <sebastian.huber@embedded-brains.de> 2011-03-29 Sebastian Huber <sebastian.huber@embedded-brains.de>
* shared/start/start.S: Default exception handler will result in * shared/start/start.S: Default exception handler will result in

16
c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c
View File

@@ -7,10 +7,11 @@
*/ */
/* /*
* Copyright (c) 2009 * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH * embedded brains GmbH
* Obere Lagerstr. 30 * Obere Lagerstr. 30
* D-82178 Puchheim * 82178 Puchheim
* Germany * Germany
* <rtems@embedded-brains.de> * <rtems@embedded-brains.de>
* *
@@ -102,11 +103,14 @@ static void lpc_clock_cleanup(void)
static uint32_t lpc_clock_nanoseconds_since_last_tick(void) static uint32_t lpc_clock_nanoseconds_since_last_tick(void)
{ {
uint64_t clock = LPC_CLOCK_REFERENCE; uint64_t k = (1000000000ULL << 32) / LPC_CLOCK_REFERENCE;
uint64_t clicks = lpc_clock->tc; uint64_t c = lpc_clock->tc;
uint64_t ns = (clicks * 1000000000) / clock;
return (uint32_t) ns; if ((lpc_clock->ir & LPC_TIMER_IR_MR0) != 0) {
c = lpc_clock->tc + lpc_clock->mr0;
}
return (uint32_t) ((c * k) >> 32);
} }
#define Clock_driver_support_at_tick() lpc_clock_at_tick() #define Clock_driver_support_at_tick() lpc_clock_at_tick()

203
c/src/lib/libbsp/arm/shared/lpc/include/lpc-dma.h
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@@ -3,14 +3,15 @@
* *
* @ingroup lpc_dma * @ingroup lpc_dma
* *
* @brief DMA API. * @brief DMA support API.
*/ */
/* /*
* Copyright (c) 2010 * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH * embedded brains GmbH
* Obere Lagerstr. 30 * Obere Lagerstr. 30
* D-82178 Puchheim * 82178 Puchheim
* Germany * Germany
* <rtems@embedded-brains.de> * <rtems@embedded-brains.de>
* *
@@ -22,7 +23,7 @@
#ifndef LIBBSP_ARM_SHARED_LPC_DMA_H #ifndef LIBBSP_ARM_SHARED_LPC_DMA_H
#define LIBBSP_ARM_SHARED_LPC_DMA_H #define LIBBSP_ARM_SHARED_LPC_DMA_H
#include <stdint.h> #include <bsp/utility.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -31,7 +32,8 @@ extern "C" {
/** /**
* @defgroup lpc_dma DMA Support * @defgroup lpc_dma DMA Support
* *
* @ingroup lpc * @ingroup lpc24xx
* @ingroup lpc32xx
* *
* @brief DMA support. * @brief DMA support.
* *
@@ -80,129 +82,132 @@ typedef struct {
} lpc_dma; } lpc_dma;
/** /**
* @name DMA Configuration Register Defines * @name DMA Configuration Register
* *
* @{ * @{
*/ */
#define LPC_DMA_CFG_EN (1U << 0) #define DMA_CFG_E BSP_BIT32(0)
#define LPC_DMA_CFG_M_0 (1U << 1) #define DMA_CFG_M_0 BSP_BIT32(1)
#define LPC_DMA_CFG_M_1 (1U << 2) #define DMA_CFG_M_1 BSP_BIT32(2)
/** @} */ /** @} */
/** /**
* @name DMA Channel Control Register Defines * @name DMA Channel Control Register
* *
* @{ * @{
*/ */
#define LPC_DMA_CH_CTRL_TSZ_MASK 0xfffU #define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11)
#define LPC_DMA_CH_CTRL_TSZ_MAX 0xfffU #define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff)
#define LPC_DMA_CH_CTRL_SB_MASK (0x7U << 12) #define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14)
#define LPC_DMA_CH_CTRL_SB_1 (0x0U << 12) #define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0)
#define LPC_DMA_CH_CTRL_SB_4 (0x1U << 12) #define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1)
#define LPC_DMA_CH_CTRL_SB_8 (0x2U << 12) #define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2)
#define LPC_DMA_CH_CTRL_SB_16 (0x3U << 12) #define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3)
#define LPC_DMA_CH_CTRL_SB_32 (0x4U << 12) #define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4)
#define LPC_DMA_CH_CTRL_SB_64 (0x5U << 12) #define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5)
#define LPC_DMA_CH_CTRL_SB_128 (0x6U << 12) #define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6)
#define LPC_DMA_CH_CTRL_SB_256 (0x7U << 12) #define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7)
#define LPC_DMA_CH_CTRL_DB_MASK (0x7U << 15) #define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17)
#define LPC_DMA_CH_CTRL_DB_1 (0x0U << 15) #define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0)
#define LPC_DMA_CH_CTRL_DB_4 (0x1U << 15) #define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1)
#define LPC_DMA_CH_CTRL_DB_8 (0x2U << 15) #define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2)
#define LPC_DMA_CH_CTRL_DB_16 (0x3U << 15) #define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3)
#define LPC_DMA_CH_CTRL_DB_32 (0x4U << 15) #define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4)
#define LPC_DMA_CH_CTRL_DB_64 (0x5U << 15) #define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5)
#define LPC_DMA_CH_CTRL_DB_128 (0x6U << 15) #define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6)
#define LPC_DMA_CH_CTRL_DB_256 (0x7U << 15) #define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7)
#define LPC_DMA_CH_CTRL_SW_MASK (0x7U << 18) #define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20)
#define LPC_DMA_CH_CTRL_SW_8 (0x0U << 18) #define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0)
#define LPC_DMA_CH_CTRL_SW_16 (0x1U << 18) #define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1)
#define LPC_DMA_CH_CTRL_SW_32 (0x2U << 18) #define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2)
#define LPC_DMA_CH_CTRL_DW_MASK (0x7U << 21) #define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23)
#define LPC_DMA_CH_CTRL_DW_8 (0x0U << 21) #define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0)
#define LPC_DMA_CH_CTRL_DW_16 (0x1U << 21) #define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1)
#define LPC_DMA_CH_CTRL_DW_32 (0x2U << 21) #define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2)
#define LPC_DMA_CH_CTRL_SM_0 (0U << 24) #define DMA_CH_CTRL_S BSP_BIT32(24)
#define LPC_DMA_CH_CTRL_SM_1 (1U << 24) #define DMA_CH_CTRL_D BSP_BIT32(25)
#define DMA_CH_CTRL_SI BSP_BIT32(26)
#define LPC_DMA_CH_CTRL_DM_0 (0U << 25) #define DMA_CH_CTRL_DI BSP_BIT32(27)
#define LPC_DMA_CH_CTRL_DM_1 (1U << 25) #define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30)
#define DMA_CH_CTRL_I BSP_BIT32(31)
#define LPC_DMA_CH_CTRL_SI (1U << 26)
#define LPC_DMA_CH_CTRL_DI (1U << 27)
#define LPC_DMA_CH_CTRL_ITC (1U << 31)
/** @} */ /** @} */
/** /**
* @name DMA Channel Configuration Register Defines * @name DMA Channel Configuration Register
* *
* @{ * @{
*/ */
#define LPC_DMA_CH_CFG_EN (1U << 0) #define DMA_CH_CFG_E BSP_BIT32(0)
#define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5)
#define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10)
#define LPC_DMA_CH_CFG_SPER_MASK (0xfU << 1) #define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13)
#define LPC_DMA_CH_CFG_SPER_SHIFT 1 #define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0)
#define LPC_DMA_CH_CFG_SPER_0 (0x0U << 1) #define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1)
#define LPC_DMA_CH_CFG_SPER_1 (0x1U << 1) #define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2)
#define LPC_DMA_CH_CFG_SPER_2 (0x2U << 1) #define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3)
#define LPC_DMA_CH_CFG_SPER_3 (0x3U << 1) #define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4)
#define LPC_DMA_CH_CFG_SPER_4 (0x4U << 1) #define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5)
#define LPC_DMA_CH_CFG_SPER_5 (0x5U << 1) #define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6)
#define LPC_DMA_CH_CFG_SPER_6 (0x6U << 1) #define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7)
#define LPC_DMA_CH_CFG_SPER_7 (0x7U << 1)
#define LPC_DMA_CH_CFG_SPER_8 (0x8U << 1)
#define LPC_DMA_CH_CFG_SPER_9 (0x9U << 1)
#define LPC_DMA_CH_CFG_SPER_10 (0xaU << 1)
#define LPC_DMA_CH_CFG_SPER_11 (0xbU << 1)
#define LPC_DMA_CH_CFG_SPER_12 (0xcU << 1)
#define LPC_DMA_CH_CFG_SPER_13 (0xdU << 1)
#define LPC_DMA_CH_CFG_SPER_14 (0xeU << 1)
#define LPC_DMA_CH_CFG_SPER_15 (0xfU << 1)
#define LPC_DMA_CH_CFG_DPER_MASK (0xfU << 6) #define DMA_CH_CFG_IE BSP_BIT32(14)
#define LPC_DMA_CH_CFG_DPER_SHIFT 6 #define DMA_CH_CFG_ITC BSP_BIT32(15)
#define LPC_DMA_CH_CFG_DPER_0 (0x0U << 6) #define DMA_CH_CFG_L BSP_BIT32(16)
#define LPC_DMA_CH_CFG_DPER_1 (0x1U << 6) #define DMA_CH_CFG_A BSP_BIT32(17)
#define LPC_DMA_CH_CFG_DPER_2 (0x2U << 6) #define DMA_CH_CFG_H BSP_BIT32(18)
#define LPC_DMA_CH_CFG_DPER_3 (0x3U << 6)
#define LPC_DMA_CH_CFG_DPER_4 (0x4U << 6)
#define LPC_DMA_CH_CFG_DPER_5 (0x5U << 6)
#define LPC_DMA_CH_CFG_DPER_6 (0x6U << 6)
#define LPC_DMA_CH_CFG_DPER_7 (0x7U << 6)
#define LPC_DMA_CH_CFG_DPER_8 (0x8U << 6)
#define LPC_DMA_CH_CFG_DPER_9 (0x9U << 6)
#define LPC_DMA_CH_CFG_DPER_10 (0xaU << 6)
#define LPC_DMA_CH_CFG_DPER_11 (0xbU << 6)
#define LPC_DMA_CH_CFG_DPER_12 (0xcU << 6)
#define LPC_DMA_CH_CFG_DPER_13 (0xdU << 6)
#define LPC_DMA_CH_CFG_DPER_14 (0xeU << 6)
#define LPC_DMA_CH_CFG_DPER_15 (0xfU << 6)
#define LPC_DMA_CH_CFG_FLOW_MASK (0x7U << 11) /** @} */
#define LPC_DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA (0x0U << 11)
#define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_DMA (0x1U << 11)
#define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_DMA (0x2U << 11)
#define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DMA (0x3U << 11)
#define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DEST (0x4U << 11)
#define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_PER (0x5U << 11)
#define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_PER (0x6U << 11)
#define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_SRC (0x7U << 11)
#define LPC_DMA_CH_CFG_IE (1U << 14) /**
#define LPC_DMA_CH_CFG_ITC (1U << 15) * @name LPC24XX DMA Peripherals
#define LPC_DMA_CH_CFG_LOCK (1U << 16) *
#define LPC_DMA_CH_CFG_ACTIVE (1U << 17) * @{
#define LPC_DMA_CH_CFG_HALT (1U << 18) */
#define LPC24XX_DMA_PER_SSP_0_TX 0
#define LPC24XX_DMA_PER_SSP_0_RX 1
#define LPC24XX_DMA_PER_SSP_1_TX 2
#define LPC24XX_DMA_PER_SSP_1_RX 3
#define LPC24XX_DMA_PER_SD_MMC 4
#define LPC24XX_DMA_PER_I2S_CH_0 5
#define LPC24XX_DMA_PER_I2S_CH_1 6
/** @} */
/**
* @name LPC32XX DMA Peripherals
*
* @{
*/
#define LPC32XX_DMA_PER_I2S_0_CH_0 0
#define LPC32XX_DMA_PER_I2S_0_CH_1 13
#define LPC32XX_DMA_PER_I2S_1_CH_0 2
#define LPC32XX_DMA_PER_I2S_1_CH_1 10
#define LPC32XX_DMA_PER_NAND_0 1
#define LPC32XX_DMA_PER_NAND_1 12
#define LPC32XX_DMA_PER_SD_MMC 4
#define LPC32XX_DMA_PER_SSP_0_RX 14
#define LPC32XX_DMA_PER_SSP_0_TX 15
#define LPC32XX_DMA_PER_SSP_1_RX 3
#define LPC32XX_DMA_PER_SSP_1_TX 11
#define LPC32XX_DMA_PER_UART_1_RX 6
#define LPC32XX_DMA_PER_UART_1_TX 5
#define LPC32XX_DMA_PER_UART_2_RX 8
#define LPC32XX_DMA_PER_UART_2_TX 7
#define LPC32XX_DMA_PER_UART_7_RX 10
#define LPC32XX_DMA_PER_UART_7_TX 9
/** @} */ /** @} */

170
c/src/lib/libbsp/arm/shared/lpc/include/lpc-emc.h Normal file
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@@ -0,0 +1,170 @@
/**
* @file
*
* @ingroup lpc_emc
*
* @brief EMC support API.
*/
/*
* Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_SHARED_LPC_EMC_H
#define LIBBSP_ARM_SHARED_LPC_EMC_H
#include <bsp/utility.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
* @defgroup lpc_emc EMC Support
*
* @ingroup lpc24xx
* @ingroup lpc32xx
*
* @brief EMC Support
*
* @{
*/
/**
* @name EMC Control Register (EMCControl)
*
* @{
*/
#define EMC_CTRL_E BSP_BIT32(0)
#define EMC_CTRL_M BSP_BIT32(0)
#define EMC_CTRL_L BSP_BIT32(2)
/** @} */
/**
* @name EMC Dynamic Memory Control Register (EMCDynamicControl)
*
* @{
*/
#define EMC_DYN_CTRL_CE BSP_BIT32(0)
#define EMC_DYN_CTRL_CS BSP_BIT32(1)
#define EMC_DYN_CTRL_SR BSP_BIT32(2)
#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3)
#define EMC_DYN_CTRL_IMCC BSP_BIT32(4)
#define EMC_DYN_CTRL_MCC BSP_BIT32(5)
#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8)
#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8)
#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8)
#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8)
#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8)
#define EMC_DYN_CTRL_DP BSP_BIT32(13)
/** @} */
/**
* @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
*
* @{
*/
#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1)
#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4)
#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9)
#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12)
/** @} */
/**
* @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN)
*
* @{
*/
#define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4)
#define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2)
#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14)
#define EMC_DYN_CFG_B BSP_BIT32(19)
#define EMC_DYN_CFG_P BSP_BIT32(20)
/** @} */
/**
* @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN)
*
* @{
*/
#define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3)
#define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10)
/** @} */
#define EMC_DYN_CHIP_COUNT 4
#define EMC_STATIC_CHIP_COUNT 4
typedef struct {
uint32_t config;
uint32_t rascas;
uint32_t reserved_0 [6];
} lpc_emc_dynamic;
typedef struct {
uint32_t config;
uint32_t waitwen;
uint32_t waitoen;
uint32_t waitrd;
uint32_t waitpage;
uint32_t waitwr;
uint32_t waitturn;
uint32_t reserved_0 [1];
} lpc_emc_static;
typedef struct {
uint32_t control;
uint32_t status;
uint32_t config;
uint32_t reserved_0 [5];
uint32_t dynamiccontrol;
uint32_t dynamicrefresh;
uint32_t dynamicreadconfig;
uint32_t reserved_1;
uint32_t dynamictrp;
uint32_t dynamictras;
uint32_t dynamictsrex;
uint32_t dynamictapr;
uint32_t dynamictdal;
uint32_t dynamictwr;
uint32_t dynamictrc;
uint32_t dynamictrfc;
uint32_t dynamictxsr;
uint32_t dynamictrrd;
uint32_t dynamictmrd;
uint32_t dynamictcdlr;
uint32_t reserved_3 [8];
uint32_t staticextendedwait;
uint32_t reserved_4 [31];
lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT];
uint32_t reserved_5 [32];
lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT];
} lpc_emc;
/** @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */

213
c/src/lib/libbsp/arm/shared/lpc/include/lpc-lcd.h Normal file
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@@ -0,0 +1,213 @@
/**
* @file
*
* @ingroup lpc_lcd
*
* @brief LCD support API.
*/
/*
* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_SHARED_LPC_LCD_H
#define LIBBSP_ARM_SHARED_LPC_LCD_H
#include <bsp/utility.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup lpc_lcd LCD Support
*
* @ingroup lpc
* @ingroup lpc32xx
*
* @brief LCD support.
*
* @{
*/
typedef struct {
uint8_t img [1024];
uint32_t ctrl;
uint32_t cfg;
uint32_t pal0;
uint32_t pal1;
uint32_t xy;
uint32_t clip;
uint32_t intmsk;
uint32_t intclr;
uint32_t intraw;
uint32_t intstat;
} lpc_cursor;
typedef struct {
uint32_t timh;
uint32_t timv;
uint32_t pol;
uint32_t le;
uint32_t upbase;
uint32_t lpbase;
uint32_t ctrl;
uint32_t intmsk;
uint32_t intraw;
uint32_t intstat;
uint32_t intclr;
uint32_t upcurr;
uint32_t lpcurr;
uint8_t reserved_0 [0x200 - 0x034];
uint16_t pal [256];
uint8_t reserved_1 [0x800 - 0x400];
lpc_cursor crsr;
} lpc_lcd;
/**
* @name LCD Configuration Register
*
* @{
*/
#define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4)
#define LCD_CFG_HCLK_ENABLE BSP_BIT32(5)
#define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7)
#define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8)
/** @} */
/**
* @name LCD Horizontal Timing Register
*
* @{
*/
#define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7)
#define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
#define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15)
#define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
#define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23)
#define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
#define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31)
#define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
/** @} */
/**
* @name LCD Vertical Timing Register
*
* @{
*/
#define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9)
#define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
#define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15)
#define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
#define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23)
#define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
#define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31)
#define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
/** @} */
/**
* @name LCD Clock and Signal Polarity Register
*
* @{
*/
#define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4)
#define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
#define LCD_POL_CLKSEL BSP_BIT32(5)
#define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10)
#define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
#define LCD_POL_IVS BSP_BIT32(11)
#define LCD_POL_IHS BSP_BIT32(12)
#define LCD_POL_IPC BSP_BIT32(13)
#define LCD_POL_IOE BSP_BIT32(14)
#define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25)
#define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
#define LCD_POL_BCD BSP_BIT32(26)
#define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31)
#define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
/** @} */
/**
* @name LCD Line End Control Register
*
* @{
*/
#define LCD_LE_LED(val) BSP_FLD32(val, 0, 6)
#define LCD_LE_LEE BSP_BIT32(16)
/** @} */
/**
* @name LCD Control Register
*
* @{
*/
#define LCD_CTRL_LCDEN BSP_BIT32(0)
#define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3)
#define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
#define LCD_CTRL_LCDBW BSP_BIT32(4)
#define LCD_CTRL_LCDTFT BSP_BIT32(5)
#define LCD_CTRL_LCDMONO8 BSP_BIT32(6)
#define LCD_CTRL_LCDDUAL BSP_BIT32(7)
#define LCD_CTRL_BGR BSP_BIT32(8)
#define LCD_CTRL_BEBO BSP_BIT32(9)
#define LCD_CTRL_BEPO BSP_BIT32(10)
#define LCD_CTRL_LCDPWR BSP_BIT32(11)
#define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13)
#define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
#define LCD_CTRL_WATERMARK BSP_BIT32(16)
/** @} */
/**
* @name LCD Interrupt Registers
*
* @{
*/
#define LCD_INT_FUF BSP_BIT32(1)
#define LCD_INT_LNBU BSP_BIT32(2)
#define LCD_INT_VCOMP BSP_BIT32(3)
#define LCD_INT_BER BSP_BIT32(4)
/** @} */
/**
* @name LCD Color Palette Register
*
* @{
*/
#define LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
#define LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
#define LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
#define LCD_PAL_I BSP_BIT16(15)
/** @} */
/** @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */

87
c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c
View File

@@ -360,7 +360,7 @@ static void lpc_eth_enable_promiscous_mode(bool enable)
| ETH_RX_FIL_CTRL_ACCEPT_BROADCAST; | ETH_RX_FIL_CTRL_ACCEPT_BROADCAST;
} else { } else {
lpc_eth->rxfilterctrl = ETH_RX_FIL_CTRL_ACCEPT_PERFECT lpc_eth->rxfilterctrl = ETH_RX_FIL_CTRL_ACCEPT_PERFECT
| ETH_RX_FIL_CTRL_ACCEPT_MULTICAST | ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH
| ETH_RX_FIL_CTRL_ACCEPT_BROADCAST; | ETH_RX_FIL_CTRL_ACCEPT_BROADCAST;
} }
} }
@@ -502,8 +502,10 @@ static bool lpc_eth_add_new_mbuf(
| ETH_RX_CTRL_INTERRUPT; | ETH_RX_CTRL_INTERRUPT;
/* Cache flush of descriptor */ /* Cache flush of descriptor */
rtems_cache_flush_multiple_data_lines((void *)&desc [i], rtems_cache_flush_multiple_data_lines(
sizeof(desc [0])); (void *) &desc [i],
sizeof(desc [0])
);
/* Add mbuf to table */ /* Add mbuf to table */
mbufs [i] = m; mbufs [i] = m;
@@ -616,8 +618,8 @@ static void lpc_eth_receive_task(void *arg)
struct mbuf *m = mbufs [receive_index]; struct mbuf *m = mbufs [receive_index];
/* Fragment status */ /* Fragment status */
rtems_cache_invalidate_multiple_data_lines rtems_cache_invalidate_multiple_data_lines(
((void *)&status [receive_index], (void *) &status [receive_index],
sizeof(status [0]) sizeof(status [0])
); );
stat = status [receive_index].info; stat = status [receive_index].info;
@@ -944,8 +946,8 @@ static void lpc_eth_transmit_task(void *arg)
); );
desc [produce_index].start = mtod(m, uint32_t); desc [produce_index].start = mtod(m, uint32_t);
desc [produce_index].control = ctrl; desc [produce_index].control = ctrl;
rtems_cache_flush_multiple_data_lines rtems_cache_flush_multiple_data_lines(
((void *)&desc [produce_index], (void *) &desc [produce_index],
sizeof(desc [0]) sizeof(desc [0])
); );
mbufs [produce_index] = m; mbufs [produce_index] = m;
@@ -1018,8 +1020,8 @@ static void lpc_eth_transmit_task(void *arg)
); );
/* Cache flush of descriptor */ /* Cache flush of descriptor */
rtems_cache_flush_multiple_data_lines rtems_cache_flush_multiple_data_lines(
((void *)&desc [produce_index], (void *) &desc [produce_index],
sizeof(desc [0]) sizeof(desc [0])
); );
@@ -1285,9 +1287,58 @@ static void lpc_eth_interface_stats(lpc_eth_driver_entry *e)
rtems_bsdnet_semaphore_obtain(); rtems_bsdnet_semaphore_obtain();
} }
static int lpc_eth_multicast_control(
bool add,
struct ifreq *ifr,
struct arpcom *ac
)
{
int eno = 0;
if (add) {
eno = ether_addmulti(ifr, ac);
} else {
eno = ether_delmulti(ifr, ac);
}
if (eno == ENETRESET) {
struct ether_multistep step;
struct ether_multi *enm;
eno = 0;
lpc_eth->hashfilterl = 0;
lpc_eth->hashfilterh = 0;
ETHER_FIRST_MULTI(step, ac, enm);
while (enm != NULL) {
uint64_t addrlo = 0;
uint64_t addrhi = 0;
memcpy(&addrlo, enm->enm_addrlo, ETHER_ADDR_LEN);
memcpy(&addrhi, enm->enm_addrhi, ETHER_ADDR_LEN);
while (addrlo <= addrhi) {
/* XXX: ether_crc32_le() does not work, why? */
uint32_t crc = ether_crc32_be((uint8_t *) &addrlo, ETHER_ADDR_LEN);
uint32_t index = (crc >> 23) & 0x3f;
if (index < 32) {
lpc_eth->hashfilterl |= 1U << index;
} else {
lpc_eth->hashfilterh |= 1U << (index - 32);
}
++addrlo;
}
ETHER_NEXT_MULTI(step, enm);
}
}
return eno;
}
static int lpc_eth_interface_ioctl( static int lpc_eth_interface_ioctl(
struct ifnet *ifp, struct ifnet *ifp,
ioctl_command_t command, ioctl_command_t cmd,
caddr_t data caddr_t data
) )
{ {
@@ -1297,14 +1348,14 @@ static int lpc_eth_interface_ioctl(
LPC_ETH_PRINTF("%s\n", __func__); LPC_ETH_PRINTF("%s\n", __func__);
switch (command) { switch (cmd) {
case SIOCGIFMEDIA: case SIOCGIFMEDIA:
case SIOCSIFMEDIA: case SIOCSIFMEDIA:
rtems_mii_ioctl(&e->mdio, e, command, (int *) data); rtems_mii_ioctl(&e->mdio, e, cmd, (int *) data);
break; break;
case SIOCGIFADDR: case SIOCGIFADDR:
case SIOCSIFADDR: case SIOCSIFADDR:
ether_ioctl(ifp, command, data); ether_ioctl(ifp, cmd, data);
break; break;
case SIOCSIFFLAGS: case SIOCSIFFLAGS:
if (ifp->if_flags & IFF_RUNNING) { if (ifp->if_flags & IFF_RUNNING) {
@@ -1316,15 +1367,9 @@ static int lpc_eth_interface_ioctl(
} }
break; break;
case SIOCADDMULTI: case SIOCADDMULTI:
case SIOCDELMULTI: { case SIOCDELMULTI:
eno = (command == SIOCADDMULTI) ? ether_addmulti(ifr, &e->arpcom) eno = lpc_eth_multicast_control(cmd == SIOCADDMULTI, ifr, &e->arpcom);
: ether_delmulti(ifr, &e->arpcom);
if (eno == ENETRESET) {
/* TODO: Use imperfect hash filter */
eno = 0;
}
break; break;
}
case SIO_RTEMS_SHOW_STATS: case SIO_RTEMS_SHOW_STATS:
lpc_eth_interface_stats(e); lpc_eth_interface_stats(e);
break; break;