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2001-11-28 Joel Sherrill <joel@OARcorp.com>,

Browse Source 
This was tracked as PR87.
	* README, configure.ac, include/Makefile.am, include/bsp.h,
	start/start.S, startup/FPGA.c, startup/Makefile.am, tod/Makefile.am:
	Eliminated conditional code for generation 1 boards as these are
	no longer available.
	* include/gen1.h, startup/82378zb.c, tod/tod_g1.c: Deleted.
This commit is contained in:
Joel Sherrill
2001-11-28 18:20:10 +00:00
parent 4db3028304
commit f5e7b4c36a
12 changed files with 28 additions and 528 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
c/src/lib/libbsp/powerpc/score603e/ChangeLog
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@@ -1,3 +1,12 @@
2001-11-28 Joel Sherrill <joel@OARcorp.com>,
This was tracked as PR87.
* README, configure.ac, include/Makefile.am, include/bsp.h,
start/start.S, startup/FPGA.c, startup/Makefile.am, tod/Makefile.am:
Eliminated conditional code for generation 1 boards as these are
no longer available.
* include/gen1.h, startup/82378zb.c, tod/tod_g1.c: Deleted.
2001-11-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add @exceptions@ to SUBDIRS.

10
c/src/lib/libbsp/powerpc/score603e/README
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@@ -3,7 +3,7 @@
#
BSP NAME: score603e
BOARD: VISTA SCORE 603e Generation I and II
BOARD: VISTA SCORE 603e Generation II and beyond
BUS: N/A
CPU FAMILY: ppc
CPU: PowerPC 603e
@@ -17,8 +17,7 @@ PERIPHERALS
TIMERS: PPC internal Timebase register
RESOLUTION:
SERIAL PORTS: 2 Z85C30s
REAL-TIME CLOCK: Generation I: SGSM48T18
Generation II: ICM7170AIBG
REAL-TIME CLOCK: Generation II and beyond: ICM7170AIBG
DMA: none
VIDEO: none
SCSI: none
@@ -51,5 +50,6 @@ the OAR Boot chip. The OAR Boot chip contains the basic
initialization from the SDS debugger and a jump to flash
location 0x04001200.
The compiler option SCORE603E_GENERATION is set to 1 or 2,
for the generation to be produced.
The SCORE603e first generation board is no longer available,
does not appear to be in use by any RTEMS users, and thus
is no longer supported.

7
c/src/lib/libbsp/powerpc/score603e/configure.ac
View File

@@ -20,11 +20,6 @@ RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
RTEMS_CANONICAL_HOST
## bsp-specific options
RTEMS_BSPOPTS_SET([SCORE603E_GENERATION],[*],[2])
RTEMS_BSPOPTS_HELP([SCORE603E_GENERATION],
[FIXME: Missing explanation])
RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
[whether using console interrupts])
@@ -78,8 +73,6 @@ RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
AM_CONFIG_HEADER(include/bspopts.h)
AM_CONDITIONAL(SCORE603E_GENERATION_1, test "${SCORE603E_GENERATION}" = "1")
RTEMS_PROJECT_ROOT
# Explicitly list all Makefiles here

2
c/src/lib/libbsp/powerpc/score603e/include/Makefile.am
View File

@@ -4,7 +4,7 @@
AUTOMAKE_OPTIONS = foreign 1.4
include_HEADERS = bsp.h coverhd.h gen1.h gen2.h tod.h bspopts.h
include_HEADERS = bsp.h coverhd.h gen2.h tod.h bspopts.h
$(PROJECT_INCLUDE):
$(mkinstalldirs) $@

10
c/src/lib/libbsp/powerpc/score603e/include/bsp.h
View File

@@ -44,15 +44,11 @@ extern "C" {
#include <clockdrv.h>
#include <iosupp.h>
/*
* We no longer support the first generation board.
*/
#if (SCORE603E_GENERATION == 1)
#include <gen1.h>
#elif (SCORE603E_GENERATION == 2)
#include <gen2.h>
#else
#error "Unknown Generation of Score603e"
#endif
/*
* The following macro calculates the Baud constant. For the Z8530 chip.

154
c/src/lib/libbsp/powerpc/score603e/include/gen1.h
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@@ -1,154 +0,0 @@
/* Gen1.h
*
* This include file contains all Generation 1 board addreses
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id:
*/
#ifndef __SCORE_GENERATION_1_h
#define __SCORE_GENERATION_1_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems.h>
/*
* ISA/PCI I/O space.
*/
#define SCORE603E_VME_JUMPER_ADDR 0x00e20000
#define SCORE603E_FLASH_BASE_ADDR 0x01000000
#define SCORE603E_ISA_PCI_IO_BASE 0x80000000
#define SCORE603E_TIMER_PORT_C 0x80000278
#define SCORE603E_TIMER_INT_ACK 0x8000027a
#define SCORE603E_TIMER_PORT_B 0x8000027b
#define SCORE603E_TIMER_PORT_A 0x8000027c
#define SCORE603E_85C30_CTRL_1 ((volatile rtems_unsigned8 *)0x800002f8)
#define SCORE603E_85C30_INT_ACK ((volatile rtems_unsigned8 *)0x800002fa)
#define SCORE603E_85C30_CTRL_0 ((volatile rtems_unsigned8 *)0x800002fb)
#define SCORE603E_85C30_DATA_1 ((volatile rtems_unsigned8 *)0x800002fc)
#define SCORE603E_85C30_DATA_0 ((volatile rtems_unsigned8 *)0x800002ff)
#define SCORE603E_85C30_CTRL_3 ((volatile rtems_unsigned8 *)0x800003f8)
#define SCORE603E_85C30_CTRL_2 ((volatile rtems_unsigned8 *)0x800003fb)
#define SCORE603E_85C30_DATA_3 ((volatile rtems_unsigned8 *)0x800003fc)
#define SCORE603E_85C30_DATA_2 ((volatile rtems_unsigned8 *)0x800003ff)
#define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8
#define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc
#define SCORE603E_UNIVERSE_BASE 0x80030000
#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
#define SCORE603E_PCI_MEM_BASE 0xc0000000
#define SCORE603E_NVRAM_BASE 0xc00f0000
#define SCORE603E_RTC_ADDRESS ((volatile unsigned char *)0xc00f1ff8)
#define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000
#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000
#define SCORE603E_VME_A16_OFFSET 0x04000000
#define SCORE603E_VME_A16_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
#define SCORE603E_BOARD_CTRL_REG ((volatile rtems_unsigned32*)0x80000800)
#define SCORE603E_BRD_FLASH_DISABLE_MASK 0x02000000
/*
* Z85C30 Definations for the 232 interface.
*/
#define SCORE603E_85C30_0_CLOCK 10000000 /* 10,000,000 */
#define SCORE603E_85C30_0_CLOCK_X 16
/*
* Z85C30 Definations for the 422 interface.
*/
#define SCORE603E_85C30_1_CLOCK 10000000 /* 10,000,000 */
#define SCORE603E_85C30_1_CLOCK_X 16
#define SCORE603E_UNIVERSE_CHIP_ID 0x000010E3
/*
* Score603e Interupt Definations.
*/
/*
* First Score Unique IRQ
*/
#define Score_IRQ_First ( PPC_IRQ_LAST + 1 )
/*
* 82378ZB IRQ definations.
*/
#define SCORE603E_IRQ00_82378ZB ( Score_IRQ_First + 0 )
#define SCORE603E_IRQ01_82378ZB ( Score_IRQ_First + 1 )
#define SCORE603E_IRQ02_82378ZB ( Score_IRQ_First + 2 )
#define SCORE603E_IRQ03_82378ZB ( Score_IRQ_First + 3 )
#define SCORE603E_IRQ04_82378ZB ( Score_IRQ_First + 4 )
#define SCORE603E_IRQ05_82378ZB ( Score_IRQ_First + 5 )
#define SCORE603E_IRQ06_82378ZB ( Score_IRQ_First + 6 )
#define SCORE603E_IRQ07_82378ZB ( Score_IRQ_First + 7 )
#define SCORE603E_IRQ08_82378ZB ( Score_IRQ_First + 8 )
#define SCORE603E_IRQ09_82378ZB ( Score_IRQ_First + 9 )
#define SCORE603E_IRQ10_82378ZB ( Score_IRQ_First + 10 )
#define SCORE603E_IRQ11_82378ZB ( Score_IRQ_First + 11 )
#define SCORE603E_IRQ12_82378ZB ( Score_IRQ_First + 12 )
#define SCORE603E_IRQ13_82378ZB ( Score_IRQ_First + 13 )
#define SCORE603E_IRQ14_82378ZB ( Score_IRQ_First + 14 )
#define SCORE603E_IRQ15_82378ZB ( Score_IRQ_First + 15 )
#define MAX_BOARD_IRQS SCORE603E_IRQ15_82378ZB
#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03_82378ZB
#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04_82378ZB
#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ12_82378ZB
#define Write_82378ZB( _offset, _data ) { \
volatile rtems_unsigned8 *addr; \
addr = (volatile rtems_unsigned8 *)(SCORE603E_ISA_PCI_IO_BASE + _offset);\
*addr = _data; }
#define Read_82378ZB( _offset, _data ) { \
volatile rtems_unsigned8 *addr; \
addr = (volatile rtems_unsigned8 *)(SCORE603E_ISA_PCI_IO_BASE + _offset);\
_data = *addr; }
/*
* BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
* driver.
*/
#define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */
/* to start/stop the timer. */
#define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */
/*
* Convert decrement value to tenths of microsecnds (used by
* shared timer driver).
*
* + CPU has a 66.67 Mhz bus,
* + There are 4 bus cycles per click
* + We return value in 1/10 microsecond units.
* Modified following equation to integer equation to remove
* floating point math.
* (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
*/
#define BSP_Convert_decrementer( _value ) \
(int) (((_value) * 4000) / 6667)
#ifdef __cplusplus
}
#endif
#endif

40
c/src/lib/libbsp/powerpc/score603e/start/start.S
View File

@@ -17,7 +17,6 @@
* $Id$
*/
#include <bspopts.h> /* for SCORE603E_GENERATION */
#include "ppc-asm.h"
.file "start.s"
@@ -68,43 +67,8 @@ past_constants:
ori r4,r4,0x0000 /* 0x2030 */
mtmsr r4
#if (SCORE603E_GENERATION == 1)
lis r4,0
mtspr 530,r4 /* Set IBAT1U */
mtspr 531,r4 /* Set IBAT1L */
mtspr 534,r4 /* Set IBAT3U */
mtspr 535,r4 /* Set IBAT3L */
mtspr 538,r4 /* Set DBAT1U */
mtspr 539,r4 /* Set DBAT1L */
lis r4,0
ori r4,r4,0x1fff
mtspr 528,r4 /* Set IBAT0U */
mtspr 536,r4 /* Set DBAT0U */
lis r4,0
ori r4,r4,0x0002
mtspr 529,r4 /* Set IBAT0L */
mtspr 537,r4 /* Set DBAT0L */
lis r4,-4096 /* 0xf000 */
ori r4,r4,8191 /* 0x1fff */
mtspr 532,r4 /* Set IBAT2U */
mtspr 540,r4 /* Set DBAT2U */
lis r4,-4096 /* 0xf000 */
ori r4,r4,1
mtspr 533,r4 /* Set IBAT2L */
mtspr 541,r4 /* Set DBAT2L */
lis r4,-32768 /* 0x8000 */
ori r4,r4,8191 /* 0x1fff */
mtspr 542,r4 /* Set DBAT3U */
lis r4,-32768 /* 0x8000 */
ori r4,r4,0x003a
mtspr 543,r4 /* Set DBAT3L */
#elif (SCORE603E_GENERATION == 2)
/* XXX FILL THIS IN WHEN I GET HELLO TO COME UP. */
#else
#error "Unknown Generation of Score603e"
#endif
/* The first generation board needed initialization here but the */
/* second does not. */
bl .Laddr /* get current address */
.Laddr:

161
c/src/lib/libbsp/powerpc/score603e/startup/82378zb.c
View File

@@ -1,161 +0,0 @@
/* 82378zb.c
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id:
*/
#include <bsp.h>
#if (SCORE603E_GENERATION == 1)
#include <string.h>
#include <fcntl.h>
#include <assert.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
/*
* initialize 82378zb
*/
void initialize_PCI_bridge ()
{
/*
* INT CNTRL-1 ICW1
* LTIM and ICW4
*/
Write_82378ZB( 0x20, 0x19);
/*
* INT CNTRL-1 ICW 2
* Sets 5 msbs of the base address in the interrupt vector table
* for the vector routines to 0100 0 ??
*/
Write_82378ZB( 0x21, 0x40 );
/*
* INT CNTRL-1 ICW 3
* Cascade CNTRL-2 INT output to IRQ[2] input of CNTRL-1
*/
Write_82378ZB( 0x21, 0x04 );
/*
* INT CNTRL-1 ICW 4
* Set Microprocessor mode for 80x86 system.
*/
Write_82378ZB( 0x21, 0x01 );
/*
* INT CNTRL-1 OCW 2
* Set Non-specific EOI command
*/
Write_82378ZB( 0x20, 0x20 );
/*
* INT CNTRL-1 OCW 3
* Interrupt controller in normal mask mode.
* Disable Poll mode command
* Read IRQ register.
*/
Write_82378ZB( 0x20, 0x2a );
/*
* INT CNTRL-1 OCW 1
* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for
* a masked IRQ will not set the interrupt request register (IRR) bit for
* that channel.
*
* XXXX - Was 0xfd Only allowing Timer interrupt through changed to
* 0xe1.
*/
Write_82378ZB( 0x21, 0xe1 );
/*
* INT CNTRL-2 ICW 1
* LTIM and ICW4
*/
Write_82378ZB( 0xa0, 0x19 );
/*
* INT CNTRL-2 ICW 2
* Sets 5 msbs of the base address in the interrupt vector table
* for the vector routines to 0100 1 ??
*/
Write_82378ZB( 0xa1, 0x48 );
/*
* INT CNTRL-1 ICW 3
* Slave Identification Code (Must be intialized to 2).
*/
Write_82378ZB( 0xa1, 0x02 );
/*
* INT CNTRL-1 ICW 4
* Set Microprocessor mode for 80x86 system.
*/
Write_82378ZB( 0xa1, 0x01 );
/*
* INT CNTRL-1 OCW 2
* Set Non-specific EOI command
*/
Write_82378ZB( 0xa0, 0x20 );
/*
* INT CNTRL-1 OCW 3
* Interrupt controller in normal mask mode.
* Disable Poll mode command
* Read IRQ register.
*/
Write_82378ZB( 0xa0, 0x2a );
/*
* INT CNTRL-1 OCW 1
* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for
* a masked IRQ will not set the interrupt request register (IRR) bit for
* that channel.
*
* XXXX - All interrupts masked.
*/
Write_82378ZB( 0xa1, 0xff );
}
rtems_unsigned16 read_and_clear_irq ()
{
rtems_unsigned16 irq;
/*
* XXX - Fix this for all interrupts later
*/
Write_82378ZB( 0x20, 0x0c);
Read_82378ZB( 0x20, irq );
irq &= 0x7;
Write_82378ZB( 0x20, 0x20 );
return irq;
}
void init_irq_data_register()
{
assert (0);
}
rtems_unsigned16 get_irq_mask()
{
assert (0);
return 0;
}
void set_irq_mask(
rtems_unsigned16 value
)
{
assert (0);
}
#endif /* end of generation 1 */

8
c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c
View File

@@ -1,6 +1,6 @@
/* FPGA.c
/* FPGA.c -- Bridge for second and subsequent generations
*
* COPYRIGHT (c) 1989-1997.
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
@@ -11,7 +11,6 @@
*/
#include <bsp.h>
#if (SCORE603E_GENERATION == 2)
#include <string.h>
#include <fcntl.h>
#include <assert.h>
@@ -164,6 +163,3 @@ rtems_unsigned16 read_and_clear_irq()
return irq;
}
#endif /* end of generation 2 */

8
c/src/lib/libbsp/powerpc/score603e/startup/Makefile.am
View File

@@ -9,10 +9,10 @@ VPATH = @srcdir@:@srcdir@/../../../shared
PGM = $(ARCH)/startup.rel
#
# First and second generation use different Bridge chips :(
# Generation 1 --> 82378zb
# First and second generation used different Bridge chips :(
# Generation 1 --> 82378zb (now in the CVS Attic)
# Generation 2 --> FPGA
STARTUP_C_FILES = 82378zb.c FPGA.c
STARTUP_C_FILES = FPGA.c
C_FILES = bspclean.c bsplibc.c bsppost.c bspstart.c bootcard.c main.c sbrk.c \
setvec.c Hwr_init.c spurious.c genpvec.c $(STARTUP_C_FILES) \
@@ -41,7 +41,7 @@ all-local: $(ARCH) $(OBJS) $(PGM) $(TMPINSTALL_FILES)
.PRECIOUS: $(PGM)
EXTRA_DIST = 82378zb.c FPGA.c Hwr_init.c bspclean.c bspstart.c genpvec.c \
EXTRA_DIST = FPGA.c Hwr_init.c bspclean.c bspstart.c genpvec.c \
linkcmds setvec.c spurious.c vmeintr.c
include $(top_srcdir)/../../../../../../automake/local.am

9
c/src/lib/libbsp/powerpc/score603e/tod/Makefile.am
View File

@@ -10,13 +10,8 @@ include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/compile.am
include $(top_srcdir)/../../../../../../automake/lib.am
# generation 1
if SCORE603E_GENERATION_1
TOD_C_FILES = tod_g1.c
else
# generation 2
# TOD for Generation 2 or later
TOD_C_FILES = tod.c
endif
C_FILES = $(TOD_C_FILES)
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
@@ -36,6 +31,6 @@ all-local: $(ARCH) $(OBJS) $(PGM)
.PRECIOUS: $(PGM)
EXTRA_DIST = tod.c tod_g1.c
EXTRA_DIST = tod.c
include $(top_srcdir)/../../../../../../automake/local.am

138
c/src/lib/libbsp/powerpc/score603e/tod/tod_g1.c
View File

@@ -1,138 +0,0 @@
/*
* Real Time Clock (SGS-Thomson M48T08/M48T18) for RTEMS
*
* This part is only found on the first generation board.
*
* Based on MVME162 TOD Driver by:
* COPYRIGHT (C) 1997
* by Katsutoshi Shibuya - BU Denken Co.,Ltd. - Sapporo - JAPAN
* ALL RIGHTS RESERVED
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems.h>
#include <tod.h>
#include <bsp.h>
/*
* These routines are M48T08 and M48T18 dependent and should be in
* a separate support library.
*/
static int M48T08_GetField(
volatile unsigned char *mk48t08,
int n,
unsigned char mask
)
{
unsigned char x;
x = mk48t08[n] & mask;
return ((x >> 4) * 10) + (x & 0x0f);
}
static void M48T08_SetField(
volatile unsigned char *mk48t08,
int n,
unsigned char d
)
{
mk48t08[n] = ((d / 10) << 4) + (d % 10);
}
static void M48T08_GetTOD(
volatile unsigned char *mk48t08,
rtems_time_of_day *rtc_tod
)
{
int year;
mk48t08[0] |= 0x40; /* Stop read register */
year = M48T08_GetField( mk48t08, 7, 0xff );
if ( year >= 88 )
year += 1900;
else
year += 2000;
rtc_tod->year = year;
rtc_tod->month = M48T08_GetField( mk48t08, 6, 0x1f );
rtc_tod->day = M48T08_GetField( mk48t08, 5, 0x3f );
rtc_tod->hour = M48T08_GetField( mk48t08, 3, 0x3f );
rtc_tod->minute = M48T08_GetField( mk48t08, 2, 0x7f );
rtc_tod->second = M48T08_GetField( mk48t08, 1, 0x7f );
rtc_tod->ticks = 0;
mk48t08[0] &= 0x3f; /* Release read register */
}
static void M48T08_SetTOD(
volatile unsigned char *mk48t08,
rtems_time_of_day *rtc_tod
)
{
int year;
year = rtc_tod->year;
if ( year >= 2088 ) /* plan ahead :) */
rtems_fatal_error_occurred( 0xBAD0BAD0 );
if ( year >= 2000 )
year -= 2000;
else
year -= 1900;
mk48t08[0] |= 0x80; /* Stop write register */
M48T08_SetField( mk48t08, 7, year );
M48T08_SetField( mk48t08, 6, rtc_tod->month );
M48T08_SetField( mk48t08, 5, rtc_tod->day );
M48T08_SetField( mk48t08, 4, 1 ); /* I don't know which day of week is */
M48T08_SetField( mk48t08, 3, rtc_tod->hour );
M48T08_SetField( mk48t08, 2, rtc_tod->minute );
M48T08_SetField( mk48t08, 1, rtc_tod->second );
mk48t08[0] &= 0x3f; /* Write these parameters */
}
/*
* This code is dependent on the Vista 603e's use of the M48T18 RTC/NVRAM
* and should remain in this file.
*/
void setRealTimeToRTEMS()
{
rtems_time_of_day rtc_tod;
M48T08_GetTOD( SCORE603E_RTC_ADDRESS, &rtc_tod );
rtems_clock_set( &rtc_tod );
}
void setRealTimeFromRTEMS()
{
rtems_time_of_day rtems_tod;
rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );
M48T08_SetTOD( SCORE603E_RTC_ADDRESS, &rtems_tod );
}
int checkRealTime()
{
rtems_time_of_day rtems_tod;
rtems_time_of_day rtc_tod;
M48T08_GetTOD( SCORE603E_RTC_ADDRESS, &rtc_tod );
rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );
if( rtems_tod.year == rtc_tod.year &&
rtems_tod.month == rtc_tod.month &&
rtems_tod.day == rtc_tod.day ) {
return ((rtems_tod.hour - rtc_tod.hour) * 3600) +
((rtems_tod.minute - rtc_tod.minute) * 60) +
(rtems_tod.second - rtc_tod.second);
}
return 9999;
}