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mips/genmongoosev: Remove

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updates #2448.
This commit is contained in:
Aun-Ali Zaidi
2015-12-13 23:41:15 -06:00
committed by Gedare Bloom
parent f6a8a77f0e
commit f39e173c47
28 changed files with 0 additions and 5030 deletions
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2
c/src/lib/libbsp/mips/acinclude.m4
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@@ -4,8 +4,6 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
case "$1" in case "$1" in
csb350 ) csb350 )
AC_CONFIG_SUBDIRS([csb350]);; AC_CONFIG_SUBDIRS([csb350]);;
genmongoosev )
AC_CONFIG_SUBDIRS([genmongoosev]);;
hurricane ) hurricane )
AC_CONFIG_SUBDIRS([hurricane]);; AC_CONFIG_SUBDIRS([hurricane]);;
jmr3904 ) jmr3904 )

85
c/src/lib/libbsp/mips/genmongoosev/Makefile.am
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@@ -1,85 +0,0 @@
ACLOCAL_AMFLAGS = -I ../../../../aclocal
include $(top_srcdir)/../../../../automake/compile.am
include_bspdir = $(includedir)/bsp
dist_project_lib_DATA = bsp_specs
include_HEADERS = include/bsp.h
include_HEADERS += include/tm27.h
include_bsp_HEADERS = start/regs.h
#isr
include_bsp_HEADERS += ../../shared/include/irq-generic.h
include_bsp_HEADERS += ../../shared/include/irq-info.h
include_bsp_HEADERS += include/irq.h
nodist_include_HEADERS = include/bspopts.h
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
nodist_include_bsp_HEADERS += include/lr33000.h
nodist_include_bsp_HEADERS += include/lr333x0.h
nodist_include_bsp_HEADERS += include/mongoose-v.h
nodist_include_bsp_HEADERS += include/r3000.h
nodist_include_bsp_HEADERS += console/mg5uart.h
DISTCLEANFILES = include/bspopts.h
noinst_PROGRAMS =
nodist_include_HEADERS += ../../shared/include/coverhd.h
noinst_LIBRARIES = libbspstart.a
libbspstart_a_SOURCES = start/start.S
libbspstart_a_SOURCES += start/regs.h
libbspstart_a_SOURCES += start/mg5.h
project_lib_DATA = start.$(OBJEXT)
dist_project_lib_DATA += startup/linkcmds
noinst_LIBRARIES += libbsp.a
libbsp_a_SOURCES =
# startup
libbsp_a_SOURCES += ../../shared/bspclean.c
libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
libbsp_a_SOURCES += ../../shared/bsplibc.c
libbsp_a_SOURCES += ../../shared/bsppost.c
libbsp_a_SOURCES += startup/bspstart.c
libbsp_a_SOURCES += ../../shared/bootcard.c
libbsp_a_SOURCES += ../../shared/sbrk.c
libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
# clock
libbsp_a_SOURCES += clock/clockdrv.c
libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
# console
libbsp_a_SOURCES += console/conscfg.c
libbsp_a_SOURCES += console/mg5uart.c
libbsp_a_SOURCES += ../../shared/console.c
libbsp_a_SOURCES += ../../shared/console_select.c
libbsp_a_SOURCES += ../../shared/console_control.c
libbsp_a_SOURCES += ../../shared/console_read.c
libbsp_a_SOURCES += ../../shared/console_write.c
# timer
libbsp_a_SOURCES += timer/timer.c
#isr
libbsp_a_SOURCES += ../../shared/src/irq-generic.c
libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
libbsp_a_SOURCES += ../../shared/src/irq-info.c
libbsp_a_SOURCES += ../../shared/src/irq-shell.c
libbsp_a_SOURCES += ../../shared/src/irq-server.c
libbsp_a_SOURCES += ../shared/irq/vectorexceptions.c
libbsp_a_SOURCES += ../shared/irq/irq.c
libbsp_a_SOURCES += irq/vectorisrs.c
libbsp_a_SOURCES += ../shared/irq/interruptmask.c
gdbstub_CPPFLAGS = -I$(srcdir)/../../mips/shared/gdbstub
noinst_PROGRAMS += gdbstub.rel
gdbstub_rel_SOURCES = ../../mips/shared/gdbstub/mips-stub.c
gdbstub_rel_SOURCES += startup/gdb-support.c
gdbstub_rel_SOURCES += ../../shared/gdbstub/rtems-stub-glue.c
gdbstub_rel_CPPFLAGS = $(AM_CPPFLAGS) $(gdbstub_CPPFLAGS)
gdbstub_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
include $(srcdir)/preinstall.am
include $(top_srcdir)/../../../../automake/local.am

225
c/src/lib/libbsp/mips/genmongoosev/README
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@@ -1,225 +0,0 @@
BSP supporting the on-CPU capabilities of the Synova Mongoose-V.
The Synova Mongoose-V is a radiation hardened derivative of the
LSI 33K with on-CPU peripherals.
This BSP assumes that basic HW initialization is performed by PMON.
Status
======
Per-task floating point enable/disable is supported for both immediate
and deferred FPU context swaps.
Interrupt Levels are adapted reasonably well to the MIPS interrupt
model. Bit 0 of the int level is a global enable/disable, corresponding
to bit 0 of the processor's SR register. Bits 1 thru 6 are configured
as masks for the Int0 thru Int5 interrupts. The 2 software interrupt
bits are always enabled by default. Each task maintains its own
Interrupt Level setting, reconfiguring the SR register's interrupt bits
whenever scheduled in. The software ints, though not addressable via
the various Interrupt Level functions, are maintained on a per-task
basis, so if software manipulates them directly, things should behave as
expected. At the time of these udpates, the Interrupt Level was only 8
bits, and completely supporting the global enable, software ints and the
hardware ints would require 9 bits. When more than 8 bits are
available, there is no reason the software interrupts could not be added
to the Interrupt Level.
While supporting the Int0 thru Int5 bits in this way doesn't seem
wonderfully useful, it does increase the level of compliance with the
RTEMS spec.
Interrupt Level 0 corresponds to interrupts globally enabled, software
ints enabled and Int0 thru Int5 enabled. If values other than 0 are
supplied, they should be formulated to impose the desired bitmask.
Interrupt priority is not a strong concept on this bsp, it is provided
only by the order in which interrupts are checked.
If during the vectoring of an interrupt, others arrive, they will all be
processed in accordance with their ordering in SR & the peripheral
register. For example, if while we're vectoring Int4, Int3 and Int5 are
asserted, Int3 will be serviced before Int5. The peripheral interrupts
are individually vectored as a consequence of Int5 being asserted,
however Int5 is not itself vectored. Within the set of peripheral
interrupts, bit 0 is vectored first, 31 is last.
Interrupts are not nested for MIPS1 or MIPS3 processors, but are
processed serially as possible. On an unloaded 50 task RTEMS program,
runnning on a 12mhz MIPS1 processor, worst-case latencies of 100us were
observed, the average being down at 60us or below.
These features are principally a consequence of fixes and tweaks to the
MIPS1 and MIPS3 processor support, and should be equally effective on
both levels of MIPS processors for any of their bsp's.
Address Map
===========
This is the generic address map of the Mongoose-V prototyping board
this BSP was tested on.
0x8000_0000 - 0x8FFF_FFFF - RAM (KSEG0 cached)
0xA000_0000 - 0xAFFF_FFFF - RAM (KSEG1, same memory uncached)
0xBFC0_0000 - 0xBFFF_FFFF - EEPROM
0xFFFE_xxxx - on-CPU peripherals
This is the hardware address map of the board used as it was
actually populated.
0x8000_0000 - 0x83FF_FFFF - 32 MB RAM (KSEG0 cached)
0xA000_0000 - 0xA3FF_FFFF - 32 MB RAM (KSEG1, same memory uncached)
0xBFC0_0000 - 0xBFDF_FFFF - 2 MB EEPROM
0xFFFE_xxxx - on-CPU peripherals
This is the organization of the EEPROM when fully populated. Since
the board used to develop this BSP only had the first bank of EEPROM
populated, only the first program image area was used.
0xBFC0_0000 - 0xBFC3_FFFF - PMON
0xBFC4_0000 - 0xBFC4_FFFF - reserved for boot loader
0xBFC5_0000 - 0xBFDF_FFFF - reserved for program 1 image
0xBFE0_0000 - 0xBFFF_FFFF - reserved for program 2 image
The Mongoose-V on this board is at 12 Mhz.
Downloading
===========
On the breadboard, a locally hacked PMON waits for a space to be pressed
while the board is reset/powered up. If found, the PMON console is
entered, else PMON jumps to the EEPROM address above, presuming a user
program is located there.
The default output of an RTEMS link is an image linked to run from
0x80020000. It is suitable for copying to S3 records or can be burned
to ROMs in whatever manner the user desires. If you want to locate the
image into ROM at some other address, use mips-rtems-objcopy to shift
the LMA.
Operation
=========
A small relocator is supplied in the bsp startup code which copies the
image down to RAM for execution before doing any other initialization.
This locator code is location independent, and will do nothing if the
image is already located at its run location. The LMA and VMA are both
controlled via the bsp's link script. The above behavior is produced by
using the default script. If this is not desirable, something like the
following may be added to the user's RTEMS link statement to override
the default linkcmds with a user-supplied version;
-qnolinkcmds -Wl,-T -Wl,mips-rtems-linkcmds-eprom
this causes the file ./mips-rtems-linkcmds-eprom to override the default
linkcmds.
Before relocating the RTEMS image, the bsp startup routine attempts to
configure the processor into a rational state. During this process,
status characters are emitted at 19200N81 on UART port 0.
The default link script simply places the image at 0x8002000 with
LMA=VMA, which is conviently located in RAM on our board. You should
probably consider creating your own linkcmds, putting things where you
want and supply it as above.
The Mongoose V has a somewhat restricted cache configuration model; you
can only flush it if the code which does so executes within noncached
memory, in our case, code in kseg1. If you do so from elsewhere the
code will appear to lock up, this is caused by the cache clearing
routine making the instruction fetch always return 0, or nop- leaving
the processor in an endless loop. The default start.S code detects if
its booting from outside kseg1, it which case it disables the cache
flush code. This means you cannot flush the cache with the bsp's
functions if you boot your program from outside kseg1. A more subtle
issue is the bsp keeps a pointer to the location in kseg1 where the
bsp's cache flush code resides. This is advantageous because you can
relocate the system anywhere and still control the cache, but might
cause trouble if the boot image becomes inaccessible. If this is
possible, you should probably consider rolling your own cache control &
disabling the bsp's.
As stated above, if you boot from outside kseg1, the bsp disables the
cache flush routines. This is not desirable in the long run because the
Mongoose V remote debugger stub assumes it can flush caches when exiting
an exception so it might not be able to update code/data properly,
though it should still nominally function. However, if you're not using
the remote debugger & don't care about flushing caches, then everything
should run just fine.
Our approach has to been locate ROM in kseg1, link the code for VMA in
RAM and relocate the LMA up into kseg1 ROM. Since the start.S code is
position-independent, it will relocate the entire app down to the VMA
region before starting things up with everything in its proper place.
The cache clear code runs before relocation, so executes from ROM &
things work.
You can prevent including the default start.S by adding;
-qnostartfile
to the link command line in addition to the "nolinkcmds" options above.
Be sure to supply your replacement start.o.
Questions
=========
Why can I send characters slowly to a Mongoose V, but get framing errors
when sending them fast?
- The MongooseV chip seems to <require> that all incoming data have 2
stop bits. When typing on a serial terminal, this is not an issue
because the idle state of an RS232 line looks just like a stop bit-
but when streaming in data, such pacing is required. The manual does
not indicate anything along these lines, instead, we suspect a
somewhat faulty UART design.
Debugging
=========
After getting Joel's initial port of the gdb stub to the Mongoose bsp, I
worked up & tested this stub on our R3000 board. It seems to work OK.
Our MIPS has 2 serial ports, the first being dedicated to the console, I
chose to arrange the 2nd one for the remote gdb protocol. While this
solution is somewhat specific to our board & bsp, I think the technique
is quite generalizable.
The following is a code snippet to be included in the user program;
/***********************************************/
extern int mg5rdbgOpenGDBuart(int);
extern void mg5rdbgCloseGDBuart(void);
void setupgdb(void)
{
printf("Configuring remote GDB stub...\n");
/* initialize remote gdb support */
if( mg5rdbgOpenGDBuart(-1) != RTEMS_SUCCESSFUL )
{
printf("Remote GDB stub is disabled.\n\n");
}
}
/***********************************************/
It allows the program to decide if it wants gdb to be ready to pick up
exceptions or not. The 2 extern functions are located in the MongooseV
bsp inside gdb-support.c. They configure & initialize the 2nd serial
port & invoke the vector initialization routine located in cpu_asm.
Note, we call directly down into the MongooseV UART driver- its quite
unfriendly to TERMIO. I chose this approach because I wanted to
minimize dependence on the I/O subsystems because they might be in a
state just short of collapsing if the program had done something bad to
cause the exception.
If user code leaves the 2nd port alone, then things will work out OK.
Greg Menke
2/27/2002
============================================================================

15
c/src/lib/libbsp/mips/genmongoosev/bsp_specs
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@@ -1,15 +0,0 @@
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: \
%{qrtems: %{!qnostartfile: start.o%s -e _start} crti.o%s crtbegin.o%s}}
*link:
%(old_link) %{qrtems: -dc -dp -N}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}

59
c/src/lib/libbsp/mips/genmongoosev/clock/clockdrv.c
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@@ -1,59 +0,0 @@
/**
* @file
*
* Instantiate the clock driver shell for the Mongoose-V's on-CPU timer.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp/irq.h>
#include <bsp.h>
#if defined(USE_TIMER2_FOR_CLOCK)
#define CLOCK_BASE MONGOOSEV_TIMER2_BASE
#define CLOCK_VECTOR MONGOOSEV_IRQ_TIMER2
#else
#define CLOCK_BASE MONGOOSEV_TIMER1_BASE
#define CLOCK_VECTOR MONGOOSEV_IRQ_TIMER1
#endif
/* reset Timeout (TO) bit */
#define Clock_driver_support_at_tick() \
do { \
MONGOOSEV_WRITE_REGISTER( CLOCK_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, \
(MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE | MONGOOSEV_TIMER_CONTROL_INTERRUPT_ENABLE)); \
} while(0)
#define Clock_driver_support_install_isr( _new, _old ) \
do { \
rtems_interrupt_handler_install( \
CLOCK_VECTOR, \
"clock", \
0, \
_new, \
NULL \
); \
} while(0)
#define Clock_driver_support_initialize_hardware() \
do { \
uint32_t _clicks = CPU_CLOCK_RATE_MHZ * rtems_configuration_get_microseconds_per_tick(); \
MONGOOSEV_WRITE_REGISTER( CLOCK_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, _clicks ); \
Clock_driver_support_at_tick(); \
} while(0)
#define Clock_driver_support_shutdown_hardware() \
MONGOOSEV_WRITE_REGISTER( CLOCK_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0 )
#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
#include "../../../shared/clockdrv_shell.h"

21
c/src/lib/libbsp/mips/genmongoosev/configure.ac
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@@ -1,21 +0,0 @@
## Process this file with autoconf to produce a configure script.
AC_PREREQ([2.69])
AC_INIT([rtems-c-src-lib-libbsp-mips-genmongoosev],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
AC_CONFIG_SRCDIR([bsp_specs])
RTEMS_TOP(../../../../../..)
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
RTEMS_BSP_CONFIGURE
RTEMS_PROG_CC_FOR_TARGET
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
# Explicitly list all Makefiles here
AC_CONFIG_FILES([Makefile])
AC_OUTPUT

101
c/src/lib/libbsp/mips/genmongoosev/console/README.mguart
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@@ -1,101 +0,0 @@
Configuration Table Use
=======================
sDeviceName
The name of this device.
deviceType
This field must be SERIAL_MG5UART.
pDeviceFns
The device interface control table. This may be:
+ mg5uart_fns for interrupt driven IO
+ mg5uart_fns_polled for polled IO
deviceProbe
This is the address of the routine which probes to see if the device
is present.
pDeviceFlow
This field is ignored as hardware flow control is not currently supported.
ulMargin
This is currently unused.
ulHysteresis
This is currently unused.
pDeviceParams
This is set to the default settings.
ulCtrlPort1
This field is the address of the command register shared by both ports.
ulCtrlPort2
This field is the address of the port being used.
ulDataPort
This field is set to MG5UART_PORTA or MG5UART_PORTB.
getRegister
setRegister
These do NOT follow standard conventions and are ignored.
The register address routines are hard-coded as this is
an on-CPU part and assumed to provide a 32-bit wide interface.
getData
This is address of the RX buffer register.
setData
This is address of the TX buffer register.
ulClock
baudRate Clock
ulIntVector
This is the interrupt vector number associated with this chip.
Example:
#if (CONSOLE_USE_INTERRUPTS)
#define MG5UART_FUNCTIONS &mg5uart_fns
#else
#define MG5UART_FUNCTIONS &mg5uart_fns_polled
#endif
{
"/dev/com0", /* sDeviceName */
SERIAL_MG5UART, /* deviceType */
MG5UART_FUNCTIONS, /* pDeviceFns */
NULL, /* deviceProbe, assume it is there */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *) NULL, /* NULL */ /* pDeviceParams */
MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, /* ulCtrlPort1 */
MONGOOSEV_UART0_BASE, /* ulCtrlPort2 */
MG5UART_UART0, /* ulDataPort */
mg5uart_get_register, /* getRegister */
mg5uart_set_register, /* setRegister */
NULL, /* unused */ /* getData */
NULL, /* unused */ /* setData */
12000000, /* ulClock */
MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR /* ulIntVector -- base for port */
}

93
c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c
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@@ -1,93 +0,0 @@
/**
* @file
*
* This file contains the libchip configuration information
* to instantiate the libchip driver for the on-CPU DUART
* and any other serial ports in the system.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <unistd.h> /* write */
#include <bsp.h>
#include <bsp/irq.h>
#include <libchip/serial.h>
#include <bsp/mg5uart.h>
/* #define CONSOLE_USE_INTERRUPTS */
#ifdef CONSOLE_USE_INTERRUPTS
#define MG5UART_FUNCTIONS &mg5uart_fns
#else
#define MG5UART_FUNCTIONS &mg5uart_fns_polled
#endif
console_tbl Console_Configuration_Ports[] = {
{
"/dev/com0", /* sDeviceName */
SERIAL_MG5UART, /* deviceType */
MG5UART_FUNCTIONS, /* pDeviceFns */
NULL, /* deviceProbe, assume it is there */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *) NULL, /* NULL */ /* pDeviceParams */
MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, /* ulCtrlPort1 */
MONGOOSEV_UART0_BASE, /* ulCtrlPort2 */
MG5UART_UART0, /* ulDataPort */
NULL, /* getRegister */
NULL, /* setRegister */
NULL, /* unused */ /* getData */
NULL, /* unused */ /* setData */
CLOCK_RATE, /* ulClock */
MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR /* ulIntVector -- base for port */
},
{
"/dev/com1", /* sDeviceName */
SERIAL_MG5UART, /* deviceType */
MG5UART_FUNCTIONS, /* pDeviceFns */
NULL, /* deviceProbe, assume it is there */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *) NULL, /* NULL */ /* pDeviceParams */
MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, /* ulCtrlPort1 */
MONGOOSEV_UART1_BASE, /* ulCtrlPort2 */
MG5UART_UART1, /* ulDataPort */
NULL, /* getRegister */
NULL, /* setRegister */
NULL, /* unused */ /* getData */
NULL, /* unused */ /* setData */
CLOCK_RATE, /* ulClock */
MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR /* ulIntVector -- base for port */
},
};
/*
* Declare some information used by the console driver
*/
#define NUM_CONSOLE_PORTS \
(sizeof(Console_Configuration_Ports)/sizeof(console_tbl))
unsigned long Console_Configuration_Count = NUM_CONSOLE_PORTS;
/*
* printk() support that simply routes printk to stderr
*/
#include <rtems/bspIo.h>
static void GENMG5_output_char(char c) { write( 2, &c, 1 ); }
BSP_output_char_function_type BSP_output_char = GENMG5_output_char;
BSP_polling_getchar_function_type BSP_poll_char = NULL;

881
c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.c
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@@ -1,881 +0,0 @@
/**
* @file
*
* This file contains the termios TTY driver for the UART found
* on the Synova Mongoose-V.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <rtems/libio.h>
#include <rtems/score/sysstate.h>
#include <stdlib.h>
#include <libchip/serial.h>
#include <libchip/sersupp.h>
#include <bsp/mg5uart.h>
#include <bsp/mongoose-v.h>
#include <bsp/irq.h>
#include <bsp.h>
/*
* Indices of registers
*/
/*
* Per chip context control
*/
typedef struct _mg5uart_context
{
int mate;
} mg5uart_context;
/*
* Define MG5UART_STATIC to nothing while debugging so the entry points
* will show up in the symbol table.
*/
/* #define MG5UART_STATIC */
#define MG5UART_STATIC static
#define MG5UART_SETREG( _base, _register, _value ) \
MONGOOSEV_WRITE_REGISTER( _base, _register, _value )
#define MG5UART_GETREG( _base, _register ) \
MONGOOSEV_READ_REGISTER( _base, _register )
/*
* Console Device Driver Support Functions
*/
MG5UART_STATIC int mg5uart_baud_rate(
int minor,
uint32_t baud,
uint32_t *code
);
MG5UART_STATIC void mg5uart_enable_interrupts(
int minor,
int mask
);
/*
* mg5uart_isr_XXX
*
* This is the single interrupt entry point which parcels interrupts
* out to the handlers for specific sources and makes sure that the
* shared handler gets the right arguments.
*
* NOTE: Yes .. this is ugly but it provides 5 interrupt source
* wrappers which are nearly functionally identical.
*/
extern void mips_default_isr(int vector);
#define __ISR(_TYPE, _OFFSET) \
MG5UART_STATIC void mg5uart_process_isr_ ## _TYPE ( \
int minor \
); \
\
MG5UART_STATIC rtems_isr mg5uart_isr_ ## _TYPE ( \
void *arg \
) \
{ \
rtems_vector_number vector = (rtems_vector_number) arg; \
int minor; \
\
for(minor=0 ; minor<Console_Port_Count ; minor++) { \
if( Console_Port_Tbl[minor]->deviceType == SERIAL_MG5UART && \
vector == Console_Port_Tbl[minor]->ulIntVector + _OFFSET ) { \
mg5uart_process_isr_ ## _TYPE (minor); \
return; \
} \
} \
mips_default_isr( vector ); \
}
__ISR(rx_frame_error, MG5UART_IRQ_RX_FRAME_ERROR)
__ISR(rx_overrun_error, MG5UART_IRQ_RX_OVERRUN_ERROR)
__ISR(tx_empty, MG5UART_IRQ_TX_EMPTY)
__ISR(tx_ready, MG5UART_IRQ_TX_READY)
__ISR(rx_ready, MG5UART_IRQ_RX_READY)
/*
* mg5uart_set_attributes
*
* This function sets the UART channel to reflect the requested termios
* port settings.
*/
MG5UART_STATIC int mg5uart_set_attributes(
int minor,
const struct termios *t
)
{
uint32_t pMG5UART_port;
uint32_t pMG5UART;
uint32_t cmd, cmdSave;
uint32_t baudcmd;
uint32_t shift;
rtems_interrupt_level Irql;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
/*
* Set the baud rate
*/
if (mg5uart_baud_rate( minor, t->c_cflag, &baudcmd ) == -1)
return -1;
/*
* Base settings
*/
/*
* Base settings
*/
cmd = MONGOOSEV_UART_CMD_RX_ENABLE | MONGOOSEV_UART_CMD_TX_ENABLE;
/*
* Parity
*/
if (t->c_cflag & PARENB) {
cmd |= MONGOOSEV_UART_CMD_PARITY_ENABLE;
if (t->c_cflag & PARODD)
cmd |= MONGOOSEV_UART_CMD_PARITY_ODD;
else
cmd |= MONGOOSEV_UART_CMD_PARITY_EVEN;
} else {
cmd |= MONGOOSEV_UART_CMD_PARITY_DISABLE;
}
/*
* Character Size
*/
if (t->c_cflag & CSIZE) {
switch (t->c_cflag & CSIZE) {
case CS5:
case CS6:
case CS7:
return -1;
break;
case CS8:
/* Mongoose-V only supports CS8 */
break;
}
} /* else default to CS8 */
/*
* Stop Bits
*/
#if 0
if (t->c_cflag & CSTOPB) {
/* 2 stop bits not supported by Mongoose-V uart */
return -1;
}
#endif
/*
* XXX what about CTS/RTS
*/
/* XXX */
/*
* Now write the registers
*/
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_CMD_SHIFT;
else
shift = MONGOOSEV_UART1_CMD_SHIFT;
rtems_interrupt_disable(Irql);
cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
(cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
rtems_interrupt_enable(Irql);
return 0;
}
/*
* mg5uart_initialize_context
*
* This function sets the default values of the per port context structure.
*/
MG5UART_STATIC void mg5uart_initialize_context(
int minor,
mg5uart_context *pmg5uartContext
)
{
int port;
unsigned int pMG5UART;
unsigned int pMG5UART_port;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
pmg5uartContext->mate = -1;
for (port=0 ; port<Console_Port_Count ; port++ ) {
if ( Console_Port_Tbl[port]->ulCtrlPort1 == pMG5UART &&
Console_Port_Tbl[port]->ulCtrlPort2 != pMG5UART_port ) {
pmg5uartContext->mate = port;
break;
}
}
}
/*
* mg5uart_init
*
* This function initializes the DUART to a quiecsent state.
*/
MG5UART_STATIC void mg5uart_init(int minor)
{
uint32_t pMG5UART;
uint32_t cmdSave;
uint32_t shift;
mg5uart_context *pmg5uartContext;
pmg5uartContext = (mg5uart_context *) malloc(sizeof(mg5uart_context));
Console_Port_Data[minor].pDeviceContext = (void *)pmg5uartContext;
mg5uart_initialize_context( minor, pmg5uartContext );
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_CMD_SHIFT;
else
shift = MONGOOSEV_UART1_CMD_SHIFT;
/*
* Disable the uart and leave this port disabled.
*/
cmdSave = MG5UART_GETREG(pMG5UART, MG5UART_COMMAND_REGISTER) & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift);
MG5UART_SETREG( pMG5UART, MG5UART_COMMAND_REGISTER, cmdSave );
/*
* Disable interrupts on RX and TX for this port
*/
mg5uart_enable_interrupts( minor, MG5UART_DISABLE_ALL );
}
/*
* mg5uart_open
*
* This function opens a port for communication.
*
* Default state is 9600 baud, 8 bits, No parity, and 1 stop bit.
*/
MG5UART_STATIC int mg5uart_open(
int major,
int minor,
void *arg
)
{
uint32_t pMG5UART;
uint32_t pMG5UART_port;
uint32_t cmd, cmdSave;
uint32_t baudcmd;
uint32_t shift;
rtems_interrupt_level Irql;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_CMD_SHIFT;
else
shift = MONGOOSEV_UART1_CMD_SHIFT;
/* XXX default baud rate could be from configuration table */
(void) mg5uart_baud_rate( minor, B19200, &baudcmd );
/*
* Set the DUART channel to a default useable state
* B19200, 8Nx since there is no stop bit control.
*/
cmd = MONGOOSEV_UART_CMD_TX_ENABLE | MONGOOSEV_UART_CMD_RX_ENABLE;
rtems_interrupt_disable(Irql);
cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
rtems_interrupt_enable(Irql);
return RTEMS_SUCCESSFUL;
}
/*
* mg5uart_close
*
* This function shuts down the requested port.
*/
MG5UART_STATIC int mg5uart_close(
int major,
int minor,
void *arg
)
{
uint32_t pMG5UART;
uint32_t cmd, cmdSave;
uint32_t shift;
rtems_interrupt_level Irql;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
/*
* Disable interrupts from this channel and then disable it totally.
*/
/* XXX interrupts */
cmd = MONGOOSEV_UART_CMD_TX_DISABLE | MONGOOSEV_UART_CMD_RX_DISABLE;
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_CMD_SHIFT;
else
shift = MONGOOSEV_UART1_CMD_SHIFT;
rtems_interrupt_disable(Irql);
cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER,
(cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
rtems_interrupt_enable(Irql);
return(RTEMS_SUCCESSFUL);
}
/*
* mg5uart_write_polled
*
* This routine polls out the requested character.
*/
MG5UART_STATIC void mg5uart_write_polled(
int minor,
char c
)
{
uint32_t pMG5UART;
uint32_t pMG5UART_port;
uint32_t status;
int shift;
int timeout;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
/*
* wait for transmitter holding register to be empty
*/
timeout = 2000;
while( --timeout )
{
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
/*
if ( (status & (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY)) ==
(MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY) )
break;
*/
if( (status & (MONGOOSEV_UART_TX_READY | MONGOOSEV_UART_TX_EMPTY)) )
break;
/*
* Yield while we wait
*/
#if 0
if(_System_state_Is_up(_System_state_Get()))
{
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
}
#endif
}
/*
* transmit character
*/
MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, c);
}
MG5UART_STATIC void mg5uart_process_isr_rx_error(
int minor,
uint32_t mask
)
{
uint32_t pMG5UART;
int shift;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
/* now clear the error */
MG5UART_SETREG(
pMG5UART,
MG5UART_STATUS_REGISTER,
mask << shift );
}
MG5UART_STATIC void mg5uart_process_isr_rx_frame_error(
int minor
)
{
mg5uart_process_isr_rx_error( minor, MONGOOSEV_UART_RX_FRAME_ERROR );
}
MG5UART_STATIC void mg5uart_process_isr_rx_overrun_error(
int minor
)
{
mg5uart_process_isr_rx_error( minor, MONGOOSEV_UART_RX_OVERRUN_ERROR );
}
MG5UART_STATIC void mg5uart_process_tx_isr(
int minor,
uint32_t source
)
{
uint32_t pMG5UART;
int shift;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
MG5UART_SETREG(
pMG5UART,
MG5UART_STATUS_REGISTER,
source << shift );
if( rtems_termios_dequeue_characters( Console_Port_Data[minor].termios_data, 1) )
{
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL);
return;
}
/*
* There are no more characters to transmit. The tx interrupts are be cleared
* by writing data to the uart, so just disable the tx interrupt sources.
*/
Console_Port_Data[minor].bActive = FALSE;
/* mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); */
}
MG5UART_STATIC void mg5uart_process_isr_tx_empty(
int minor
)
{
/* mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_EMPTY ); */
}
MG5UART_STATIC void mg5uart_process_isr_tx_ready(
int minor
)
{
mg5uart_process_tx_isr( minor, MONGOOSEV_UART_TX_READY );
}
MG5UART_STATIC void mg5uart_process_isr_rx_ready(
int minor
)
{
uint32_t pMG5UART_port;
char c;
pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
/* reading the RX buffer automatically resets the interrupt flag */
c = (char) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
rtems_termios_enqueue_raw_characters(
Console_Port_Data[minor].termios_data,
&c,
1
);
}
static rtems_irq_connect_data mg5uart_rx_frame_error_cd = { \
0, /* filled in at initialization */
mg5uart_isr_rx_frame_error, /* filled in at initialization */
NULL, /* (void *) minor */
NULL,
NULL,
NULL
};
static rtems_irq_connect_data mg5uart_rx_overrun_error_cd = { \
0, /* filled in at initialization */
mg5uart_isr_rx_overrun_error, /* filled in at initialization */
NULL, /* (void *) minor */
NULL,
NULL,
NULL
};
static rtems_irq_connect_data mg5uart_tx_empty_cd = { \
0, /* filled in at initialization */
mg5uart_isr_tx_empty, /* filled in at initialization */
NULL, /* (void *) minor */
NULL,
NULL,
NULL
};
static rtems_irq_connect_data mg5uart_tx_ready_cd = { \
0, /* filled in at initialization */
mg5uart_isr_tx_ready, /* filled in at initialization */
NULL, /* (void *) minor */
NULL,
NULL,
NULL
};
static rtems_irq_connect_data mg5uart_rx_ready_cd = { \
0, /* filled in at initialization */
mg5uart_isr_rx_ready, /* filled in at initialization */
NULL, /* (void *) minor */
NULL,
NULL,
NULL
};
/*
* mg5uart_initialize_interrupts
*
* This routine initializes the console's receive and transmit
* ring buffers and loads the appropriate vectors to handle the interrupts.
*/
MG5UART_STATIC void mg5uart_initialize_interrupts(int minor)
{
unsigned long v;
mg5uart_init(minor);
Console_Port_Data[minor].bActive = FALSE;
v = Console_Port_Tbl[minor]->ulIntVector;
mg5uart_rx_frame_error_cd.name = v + MG5UART_IRQ_RX_FRAME_ERROR;
mg5uart_rx_overrun_error_cd.name = v + MG5UART_IRQ_RX_OVERRUN_ERROR;
mg5uart_tx_empty_cd.name = v + MG5UART_IRQ_TX_EMPTY;
mg5uart_tx_ready_cd.name = v + MG5UART_IRQ_TX_READY;
mg5uart_rx_ready_cd.name = v + MG5UART_IRQ_RX_READY;
mg5uart_rx_frame_error_cd.handle = (void *)mg5uart_rx_frame_error_cd.name;
mg5uart_rx_overrun_error_cd.handle = (void *)mg5uart_rx_overrun_error_cd.name;
mg5uart_tx_empty_cd.handle = (void *)mg5uart_tx_empty_cd.name;
mg5uart_tx_ready_cd.handle = (void *)mg5uart_tx_ready_cd.name;
mg5uart_rx_ready_cd.handle = (void *)mg5uart_rx_ready_cd.name;
BSP_install_rtems_irq_handler( &mg5uart_rx_frame_error_cd );
BSP_install_rtems_irq_handler( &mg5uart_rx_overrun_error_cd );
BSP_install_rtems_irq_handler( &mg5uart_tx_empty_cd );
BSP_install_rtems_irq_handler( &mg5uart_tx_ready_cd );
BSP_install_rtems_irq_handler( &mg5uart_rx_ready_cd );
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
}
/*
* mg5uart_write_support_int
*
* Console Termios output entry point when using interrupt driven output.
*/
MG5UART_STATIC int mg5uart_write_support_int(
int minor,
const char *buf,
size_t len
)
{
uint32_t pMG5UART_port;
pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
/*
* We are using interrupt driven output and termios only sends us
* one character at a time.
*/
if ( !len )
return 0;
/*
* Put the character out and enable interrupts if necessary.
*/
MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf);
if( Console_Port_Data[minor].bActive == FALSE )
{
Console_Port_Data[minor].bActive = TRUE;
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL);
}
return 1;
}
/*
* mg5uart_write_support_polled
*
* Console Termios output entry point when using polled output.
*
*/
MG5UART_STATIC ssize_t mg5uart_write_support_polled(
int minor,
const char *buf,
size_t len
)
{
int nwrite = 0;
/*
* poll each byte in the string out of the port.
*/
while (nwrite < len)
{
mg5uart_write_polled(minor, *buf++);
nwrite++;
}
/*
* return the number of bytes written.
*/
return nwrite;
}
/*
* mg5uart_inbyte_nonblocking_polled
*
* Console Termios polling input entry point.
*/
MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled(
int minor
)
{
uint32_t pMG5UART;
uint32_t pMG5UART_port;
uint32_t status;
uint32_t tmp,shift;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
pMG5UART_port = Console_Port_Tbl[minor]->ulCtrlPort2;
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
/* reset overrrun or framing errors */
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
if( (tmp = (status & 0x3)) )
{
MG5UART_SETREG(pMG5UART, MG5UART_STATUS_REGISTER, (tmp << shift) );
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
}
if ( status & MONGOOSEV_UART_RX_READY )
{
return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
}
else
{
return -1;
}
}
/*
* mg5uart_baud_rate
*/
MG5UART_STATIC int mg5uart_baud_rate(
int minor,
uint32_t baud,
uint32_t *code
)
{
uint32_t clock;
uint32_t tmp_code;
uint32_t baud_requested;
baud_requested = baud & CBAUD;
if (!baud_requested)
baud_requested = B9600; /* default to 9600 baud */
baud_requested = rtems_termios_baud_to_number( baud_requested );
clock = (uint32_t) Console_Port_Tbl[minor]->ulClock;
if (!clock)
rtems_fatal_error_occurred(RTEMS_INVALID_NUMBER);
/*
* Formula is Code = round(ClockFrequency / Baud - 1).
*
* Since this is integer math, we will divide by twice the baud and
* check the remaining odd bit.
*/
tmp_code = (clock / baud_requested) - 1;
/*
* From section 12.7, "Keep C>100 for best receiver operation."
* That is 100 cycles which is not a lot of instructions. It is
* reasonable to think that the Mongoose-V could not keep
* up with C < 100.
*/
if ( tmp_code < 100 )
return RTEMS_INVALID_NUMBER;
/*
* upper word is receiver baud and lower word is transmitter baud
*/
*code = (tmp_code << 16) | tmp_code;
return 0;
}
/*
* mg5uart_enable_interrupts
*
* This function enables specific interrupt sources on the DUART.
*/
MG5UART_STATIC void mg5uart_enable_interrupts(
int minor,
int mask
)
{
uint32_t pMG5UART;
uint32_t maskSave;
uint32_t shift;
rtems_interrupt_level Irql;
pMG5UART = Console_Port_Tbl[minor]->ulCtrlPort1;
/*
* Enable interrupts on RX and TX -- not break
*/
if ( Console_Port_Tbl[minor]->ulDataPort == MG5UART_UART0 )
shift = MONGOOSEV_UART0_IRQ_SHIFT;
else
shift = MONGOOSEV_UART1_IRQ_SHIFT;
rtems_interrupt_disable(Irql);
maskSave = MG5UART_GETREG( pMG5UART, MG5UART_INTERRUPT_MASK_REGISTER );
MG5UART_SETREG(
pMG5UART,
MG5UART_INTERRUPT_MASK_REGISTER,
(maskSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (mask << shift) );
rtems_interrupt_enable(Irql);
}
/*
* Flow control is only supported when using interrupts
*/
const console_fns mg5uart_fns =
{
libchip_serial_default_probe, /* deviceProbe */
mg5uart_open, /* deviceFirstOpen */
NULL, /* deviceLastClose */
NULL, /* deviceRead */
mg5uart_write_support_int, /* deviceWrite */
mg5uart_initialize_interrupts, /* deviceInitialize */
mg5uart_write_polled, /* deviceWritePolled */
mg5uart_set_attributes, /* deviceSetAttributes */
TRUE /* deviceOutputUsesInterrupts */
};
const console_fns mg5uart_fns_polled =
{
libchip_serial_default_probe, /* deviceProbe */
mg5uart_open, /* deviceFirstOpen */
mg5uart_close, /* deviceLastClose */
mg5uart_inbyte_nonblocking_polled, /* deviceRead */
mg5uart_write_support_polled, /* deviceWrite */
mg5uart_init, /* deviceInitialize */
mg5uart_write_polled, /* deviceWritePolled */
mg5uart_set_attributes, /* deviceSetAttributes */
FALSE, /* deviceOutputUsesInterrupts */
};

97
c/src/lib/libbsp/mips/genmongoosev/console/mg5uart.h
View File

@@ -1,97 +0,0 @@
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _MG5UART_H_
#define _MG5UART_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* This is the ASCII for "MG5U" which should be unique enough to
* distinguish this type of serial device from others.
*/
#define SERIAL_MG5UART 0x474D5535
#define MG5UART_UART0 0
#define MG5UART_UART1 1
/*
* These are just used in the interface between this driver and
* the read/write register routines when accessing the first
* control port. They are indices of registers from the bases.
*/
/* shared registers from peripheral base (i.e. from ulCtrlPort1) */
/*
#define MG5UART_COMMAND_REGISTER 0
#define MG5UART_STATUS_REGISTER 1
#define MG5UART_INTERRUPT_CAUSE_REGISTER 2
#define MG5UART_INTERRUPT_MASK_REGISTER 3
*/
#define MG5UART_COMMAND_REGISTER 0
#define MG5UART_STATUS_REGISTER 0x04
#define MG5UART_INTERRUPT_CAUSE_REGISTER 0x08
#define MG5UART_INTERRUPT_MASK_REGISTER 0x0C
/* port specific registers from uart base (i.e. from ulCtrlPort2) */
#define MG5UART_RX_BUFFER 0
#define MG5UART_TX_BUFFER 4
#define MG5UART_BAUD_RATE 8
/*
* Interrupt mask values
*/
#define MG5UART_ENABLE_ALL_EXCEPT_TX MONGOOSEV_UART_ALL_RX_STATUS_BITS
/* all rx ints on, but only tx ready. no need to also int on tx empty */
#define MG5UART_ENABLE_ALL (MONGOOSEV_UART_ALL_STATUS_BITS & ~MONGOOSEV_UART_TX_EMPTY)
#define MG5UART_DISABLE_ALL 0x0000
/*
* Assume vectors are sequential.
*/
#define MG5UART_IRQ_RX_FRAME_ERROR 0
#define MG5UART_IRQ_RX_OVERRUN_ERROR 1
#define MG5UART_IRQ_TX_EMPTY 2
#define MG5UART_IRQ_TX_READY 3
#define MG5UART_IRQ_RX_READY 4
/*
* Driver function table
*/
extern const console_fns mg5uart_fns;
extern const console_fns mg5uart_fns_polled;
/*
* Default register access routines
*/
uint32_t mg5uart_get_register( /* registers are on 32-bit boundaries */
uintptr_t ulCtrlPort, /* and accessed as word */
uint32_t ucRegNum
);
void mg5uart_set_register(
uintptr_t ulCtrlPort,
uint32_t ucRegNum,
uint32_t ucData
);
#ifdef __cplusplus
}
#endif
#endif /* _MG5UART_H_ */

58
c/src/lib/libbsp/mips/genmongoosev/console/mg5uart_reg.c
View File

@@ -1,58 +0,0 @@
/*
* This file contains a typical set of register access routines which may be
* used with the mg5uart chip if accesses to the chip are as follows:
*
* + registers are accessed as uint32_t 's
* + registers are only u32-aligned (no address gaps)
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#ifndef _MG5UART_MULTIPLIER
#define _MG5UART_MULTIPLIER 1
#define _MG5UART_NAME(_X) _X
#define _MG5UART_TYPE uint32_t
#endif
#define CALCULATE_REGISTER_ADDRESS( _base, _reg ) \
(_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER ))
/*
* MG5UART Get Register Routine
*/
uint8_t _MG5UART_NAME(mg5uart_get_register)(
uint32_t ulCtrlPort,
uint8_t ucRegNum
)
{
_MG5UART_TYPE *port;
port = CALCULATE_REGISTER_ADDRESS( ulCtrlPort, ucRegNum );
return *port;
}
/*
* MG5UART Set Register Routine
*/
void _MG5UART_NAME(mg5uart_set_register)(
uint32_t ulCtrlPort,
uint8_t ucRegNum,
uint8_t ucData
)
{
_MG5UART_TYPE *port;
port = CALCULATE_REGISTER_ADDRESS( ulCtrlPort, ucRegNum );
*port = ucData;
}

73
c/src/lib/libbsp/mips/genmongoosev/include/bsp.h
View File

@@ -1,73 +0,0 @@
/**
* @file
*
* This include file contains some definitions specific to a board
* based upon the generic capabilities of a Mongoose-V.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_MIPS_GENMONGOOSEV_BSP_H
#define LIBBSP_MIPS_GENMONGOOSEV_BSP_H
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#include <rtems.h>
#include <rtems/iosupp.h>
#include <rtems/console.h>
#include <rtems/clockdrv.h>
#include <bsp/mongoose-v.h>
#ifdef __cplusplus
extern "C" {
#endif
#define BSP_FEATURE_IRQ_EXTENSION
#define BSP_SHARED_HANDLER_SUPPORT 1
#ifndef CPU_CLOCK_RATE
#define CLOCK_RATE 12000000
#endif
#define CPU_CLOCK_RATE_HZ CLOCK_RATE
#define CPU_CLOCK_RATE_MHZ (CLOCK_RATE/1000000)
/*
* Useful defines set here so we can avoid duplicating them all over
* creation.
*
*/
/*
* assertSoftwareInt defined in vectorisrs.c the prototype is here so
* userspace code can get to it directly.
* */
extern void assertSoftwareInterrupt(uint32_t);
#define CLOCK_VECTOR MONGOOSEV_IRQ_TIMER1
/* from start.S */
extern void promCopyIcacheFlush(void);
extern void promCopyDcacheFlush(void);
/*
* Called from user programs wanting to use the GDB stub.
*/
void mg5rdbgCloseGDBuart(void);
int mg5rdbgOpenGDBuart(int);
#ifdef __cplusplus
}
#endif
#endif

95
c/src/lib/libbsp/mips/genmongoosev/include/irq.h
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@@ -1,95 +0,0 @@
/**
* @file
*
* @ingroup bsp_interrupt
*
* @brief interrupt definitions.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_MIPS_MONGOOSEV_IRQ_H
#define LIBBSP_MIPS_MONGOOSEV_IRQ_H
#ifndef ASM
#include <rtems.h>
#include <rtems/irq.h>
#include <rtems/irq-extension.h>
#include <rtems/score/mips.h>
#endif
/**
* @addtogroup bsp_interrupt
*
* @{
*/
/*
* Interrupt Vector Numbers
*
* NOTE: IRQ INT5 is logical or of peripheral cause register
* per p. 5-22 of Mongoose-V manual.
*/
#define BSP_INTERRUPT_VECTOR_MIN 0
#define MONGOOSEV_IRQ_INT0 MIPS_INTERRUPT_BASE+0
#define MONGOOSEV_IRQ_TIMER1 MONGOOSEV_IRQ_INT0
#define MONGOOSEV_IRQ_INT1 MIPS_INTERRUPT_BASE+1
#define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1
#define MONGOOSEV_IRQ_INT2 MIPS_INTERRUPT_BASE+2
#define MONGOOSEV_IRQ_INT3 MIPS_INTERRUPT_BASE+3
#define MONGOOSEV_IRQ_FPU MONGOOSEV_IRQ_INT3
#define MONGOOSEV_IRQ_INT4 MIPS_INTERRUPT_BASE+4
/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
#define MONGOOSEV_IRQ_PERIPHERAL_BASE MIPS_INTERRUPT_BASE+5
#define MONGOOSEV_IRQ_XINT0 MONGOOSEV_IRQ_PERIPHERAL_BASE + 0
#define MONGOOSEV_IRQ_XINT1 MONGOOSEV_IRQ_PERIPHERAL_BASE + 1
#define MONGOOSEV_IRQ_XINT2 MONGOOSEV_IRQ_PERIPHERAL_BASE + 2
#define MONGOOSEV_IRQ_XINT3 MONGOOSEV_IRQ_PERIPHERAL_BASE + 3
#define MONGOOSEV_IRQ_XINT4 MONGOOSEV_IRQ_PERIPHERAL_BASE + 4
#define MONGOOSEV_IRQ_XINT5 MONGOOSEV_IRQ_PERIPHERAL_BASE + 5
#define MONGOOSEV_IRQ_XINT6 MONGOOSEV_IRQ_PERIPHERAL_BASE + 6
#define MONGOOSEV_IRQ_XINT7 MONGOOSEV_IRQ_PERIPHERAL_BASE + 7
#define MONGOOSEV_IRQ_XINT8 MONGOOSEV_IRQ_PERIPHERAL_BASE + 8
#define MONGOOSEV_IRQ_XINT9 MONGOOSEV_IRQ_PERIPHERAL_BASE + 9
#define MONGOOSEV_IRQ_RESERVED_BIT_10 MONGOOSEV_IRQ_PERIPHERAL_BASE + 10
#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 11
#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12
#define MONGOOSEV_IRQ_UART0_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 13
#define MONGOOSEV_IRQ_UART0_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 14
#define MONGOOSEV_IRQ_UART0_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 15
#define MONGOOSEV_IRQ_RESERVED_BIT_16 MONGOOSEV_IRQ_PERIPHERAL_BASE + 16
#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 17
#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18
#define MONGOOSEV_IRQ_UART1_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 19
#define MONGOOSEV_IRQ_UART1_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 20
#define MONGOOSEV_IRQ_UART1_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 21
#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 22
#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23
#define MONGOOSEV_IRQ_RESERVED_24 MONGOOSEV_IRQ_PERIPHERAL_BASE + 24
#define MONGOOSEV_IRQ_RESERVED_25 MONGOOSEV_IRQ_PERIPHERAL_BASE + 25
#define MONGOOSEV_IRQ_RESERVED_26 MONGOOSEV_IRQ_PERIPHERAL_BASE + 26
#define MONGOOSEV_IRQ_RESERVED_27 MONGOOSEV_IRQ_PERIPHERAL_BASE + 27
#define MONGOOSEV_IRQ_RESERVED_28 MONGOOSEV_IRQ_PERIPHERAL_BASE + 28
#define MONGOOSEV_IRQ_RESERVED_29 MONGOOSEV_IRQ_PERIPHERAL_BASE + 29
#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 30
#define MONGOOSEV_IRQ_CORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 31
#define MONGOOSEV_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+37
#define MONGOOSEV_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+38
#define MONGOOSEV_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+39
#define BSP_INTERRUPT_VECTOR_MAX MONGOOSEV_MAXIMUM_VECTORS
/** @} */
#endif /* LIBBSP_MIPS_MONGOOSEV_IRQ_H */

99
c/src/lib/libbsp/mips/genmongoosev/include/lr33000.h
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/* lr33000.h - LSI LR33000 CPU header */
/*
modification history
--------------------
01c,22sep92,rrr added support for c++
01b,20apr92,ajm added CR_DCAS for ethernet support
01a,10feb92,ajm written for FCS
*/
#ifndef __INClr33000h
#define __INClr33000h
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#define C0_DCIC $7 /* cache control */
#define C0_BPC $3 /* breakpoint on instr */
#define C0_BDA $5 /* breakpoint on data */
#endif /* _ASMLANGUAGE */
#define DEBUG_VECT 0x00000040
#define K0_DEBUG_VECT (K0BASE+DEBUG_VECT)
#define K1_DEBUG_VECT (K1BASE+DEBUG_VECT)
/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
#define DCIC_TR 0x80000000 /* Trap enable */
#define DCIC_UD 0x40000000 /* User debug enable */
#define DCIC_KD 0x20000000 /* Kernel debug enable */
#define DCIC_TE 0x10000000 /* Trace enable */
#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */
#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */
#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */
#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */
#define DCIC_DE 0x00800000 /* Debug enable */
#define DCIC_DL 0x00008000 /* Data cache line invalidate */
#define DCIC_IL 0x00004000 /* Instruction cache line invalidate */
#define DCIC_D 0x00002000 /* Data cache invalidate enable */
#define DCIC_I 0x00001000 /* Instr. cache invalidate enable */
#define DCIC_T 0x00000020 /* Trace, set by CPU */
#define DCIC_W 0x00000010 /* Write reference, set by CPU */
#define DCIC_R 0x00000008 /* Read reference, set by CPU */
#define DCIC_DA 0x00000004 /* Data address, set by CPU */
#define DCIC_PC 0x00000002 /* Program counter, set by CPU */
#define DCIC_DB 0x00000001 /* Debug, set by CPU */
/* Define counter/timer register addresses */
#define M_TIC1 0xfffe0000 /* timer 1 initial count */
#define M_TC1 0xfffe0004 /* timer 1 control */
#define M_TIC2 0xfffe0008 /* timer 2 initial count */
#define M_TC2 0xfffe000c /* timer 2 control */
#define M_RTIC 0xfffe0010 /* refresh timer */
#define M_CFGREG 0xfffe0020 /* configuration reg */
/* Definitions for counter/timer control register bits */
#define TC_CE 0x00000004 /* count enable */
#define TC_IE 0x00000002 /* interrupt enable (1 == enable) */
#define TC_INT 0x00000001 /* interrupt acknowlege (0 == ack) */
#define TCNT_MASK 0x00ffffff /* 24 bit timer mask */
/* Definitions for Configuration register bits */
#define CR_ICDISABLE 0x00800000 /* Instruction cache disable */
#define CR_DCDISABLE 0x00400000 /* Data cache disable */
#define CR_IBLK_2 0x00000000 /* Instruction cache block size */
#define CR_IBLK_4 0x00100000 /* Instruction cache block size */
#define CR_IBLK_8 0x00200000 /* Instruction cache block size */
#define CR_IBLK_16 0x00300000 /* Instruction cache block size */
#define CR_IBLKMSK 0x00300000 /* Instruction cache block size */
#define CR_DBLK_2 0x00000000 /* Data cache block size */
#define CR_DBLK_4 0x00040000 /* Data cache block size */
#define CR_DBLK_8 0x00080000 /* Data cache block size */
#define CR_DBLK_16 0x000c0000 /* Data cache block size */
#define CR_DBLKMSK 0x000c0000 /* Data cache block size */
#define CR_IODIS 0x00020000 /* Disable DRDY for I/O addresses */
#define CR_IOWAITSHFT 13 /* I/O wait states */
#define CR_PDIS 0x00001000 /* Disable DRDY for PROM addresses */
#define CR_PWAITSHFT 8 /* PROM wait states */
#define CR_DCAS 0x00000080 /* Define # cycles of DCAS */
#define CR_DPEN 0x00000040 /* Enable parity check for DRAM */
#define CR_RDYGEN 0x00000020 /* Disable DRDY for DRAM addresses */
#define CR_BLKFDIS 0x00000010 /* Disable DRAM block refill */
#define CR_RFSHEN 0x00000008 /* Enable refresh generator */
#define CR_RASPCHG 0x00000004 /* Define RAS precharge */
#define CR_CASLNTH 0x00000002 /* Define CAS active time */
#define CR_DRAMEN 0x00000001 /* Enable DRAM controller */
#define CR_PWT(x) ((x) << 8) /* memory wait states */
#define CR_IOWT(x) ((x) << 13) /* io wait states */
#define LR33000_DSIZE 0x400 /* Data cache = 1Kbytes */
#define LR33000_ISIZE 0x2000 /* Instructrion cache = 8Kbytes */
#ifdef __cplusplus
}
#endif
#endif /* __INClr33000h */

180
c/src/lib/libbsp/mips/genmongoosev/include/lr333x0.h
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/* lr333x0.h - LSI LR333x0 CPU header */
#ifndef __INClr333x0h
#define __INClr333x0h
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#define C0_BPC $3 /* breakpoint on instr */
#define C0_BDA $5 /* breakpoint on data */
#define C0_TAR $6 /* target address register */
#define C0_DCIC $7 /* cache control */
#define C0_BDAM $9 /* breakpoint data addr mask */
#define C0_BPCM $11 /* breakpoint instr addr mask */
#else
IMPORT int sysICsize; /* inst cache size defined in BSP */
IMPORT int sysDCsize; /* data cache size defined in BSP */
IMPORT BOOL sysICset0; /* inst cache set 0 present ? */
#endif /* _ASMLANGUAGE */
#define DEBUG_VECT 0x00000040
#define K0_DEBUG_VECT (K0BASE+DEBUG_VECT)
#define K1_DEBUG_VECT (K1BASE+DEBUG_VECT)
/* Define register addresses */
#define M_TIC1 0xfffe0000 /* timer 1 initial count */
#define M_TC1 0xfffe0004 /* timer 1 control */
#define M_TIC2 0xfffe0008 /* timer 2 initial count */
#define M_TC2 0xfffe000c /* timer 2 control */
#define M_RTIC 0xfffe0010 /* refresh timer */
#define M_SRAM 0xfffe0100 /* SRAM config reg */
#define M_SPEC0 0xfffe0104
#define M_SPEC1 0xfffe0108
#define M_SPEC2 0xfffe010c
#define M_SPEC3 0xfffe0110
#define M_DRAM 0xfffe0120 /* DRAM configuration */
#define M_BIU 0xfffe0130 /* BIU/cache configuration */
/* Definitions for Debug and Cache Invalidate control (DCIC) register bits */
#define DCIC_TR 0x80000000 /* Trap enable */
#define DCIC_UD 0x40000000 /* User debug enable */
#define DCIC_KD 0x20000000 /* Kernel debug enable */
#define DCIC_TE 0x10000000 /* Trace enable */
#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */
#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */
#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */
#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */
#define DCIC_DE 0x00800000 /* Debug enable */
#define DCIC_T 0x00000020 /* Trace, set by CPU */
#define DCIC_W 0x00000010 /* Write reference, set by CPU */
#define DCIC_R 0x00000008 /* Read reference, set by CPU */
#define DCIC_DA 0x00000004 /* Data address, set by CPU */
#define DCIC_PC 0x00000002 /* Program counter, set by CPU */
#define DCIC_DB 0x00000001 /* Debug, set by CPU */
/* Definitions for counter/timer control register bits */
#define TC_CE 0x00000004 /* count enable */
#define TC_IE 0x00000002 /* interrupt enable (1 == enable) */
#define TC_INT 0x00000001 /* interrupt acknowlege (0 == ack) */
/* Definitions for Wait-state configuration register bits */
#define SPC_INHIBITSHFT 24 /* Inhibit shift count */
#define SPC_EXTGNT 0x00800000 /* External data ready */
#define SPC_16WIDE 0x00400000 /* 16-bit wide memory */
#define SPC_8WIDE 0x00200000 /* 8-bit wide memory */
#define SPC_PENA 0x00100000 /* Parity enable */
#define SPC_CACHED 0x00080000 /* Cache data */
#define SPC_CSDLY_3 0x00060000 /* Select delay, 3 cycles */
#define SPC_CSDLY_2 0x00040000 /* Select delay, 2 cycles */
#define SPC_CSDLY_1 0x00020000 /* Select delay, 1 cycles */
#define SPC_CSDLY_0 0x00000000 /* Select delay, 0 cycles */
#define SPC_BLKENA 0x00010000 /* Block enable */
#define SPC_BLKWAIT_7 0x0000e000 /* Block delay, 7 cycles */
#define SPC_BLKWAIT_6 0x0000c000 /* Block delay, 6 cycles */
#define SPC_BLKWAIT_5 0x0000a000 /* Block delay, 5 cycles */
#define SPC_BLKWAIT_4 0x00008000 /* Block delay, 4 cycles */
#define SPC_BLKWAIT_3 0x00006000 /* Block delay, 3 cycles */
#define SPC_BLKWAIT_2 0x00004000 /* Block delay, 2 cycles */
#define SPC_BLKWAIT_1 0x00002000 /* Block delay, 1 cycles */
#define SPC_BLKWAIT_0 0x00000000 /* Block delay, 0 cycles */
#define SPC_RECSHFT 7 /* Recovery time shift count */
#define SPC_WAITENA 0x00000040 /* Wait-state generator enable */
#define SPC_WAITSHFT 0 /* Wait shift count */
/* Definitions for DRAM configuration register bits */
#define DRAM_DLP1 0x10000000 /* Data latch in phase 1 */
#define DRAM_SYNC 0x08000000 /* Sunchronous DRAM mode */
#define DRAM_SCFG 0x04000000 /* Synchronous Configuration mode */
#define DRAM_DMARDY 0x02000000 /* DMA ready */
#define DRAM_DMABLK_64 0x01400000 /* DMA block refill size, 64 words */
#define DRAM_DMABLK_32 0x01000000 /* DMA block refill size, 32 words */
#define DRAM_DMABLK_16 0x00c00000 /* DMA block refill size, 16 words */
#define DRAM_DMABLK_8 0x00800000 /* DMA block refill size, 8 words */
#define DRAM_DMABLK_4 0x00400000 /* DMA block refill size, 4 words */
#define DRAM_DMABLK_2 0x00000000 /* DMA block refill size, 2 words */
#define DRAM_DPTH_8 0x00300000 /* CAS ready depth, 8 per cycle */
#define DRAM_DPTH_4 0x00200000 /* CAS ready depth, 4 per cycle */
#define DRAM_DPTH_2 0x00100000 /* CAS ready depth, 2 per cycle */
#define DRAM_DPTH_1 0x00000000 /* CAS ready depth, 1 per cycle */
#define DRAM_RDYW 0x00080000 /* Ready Wait */
#define DRAM_PGSZ_2K 0x00070000 /* Page size, 2K words */
#define DRAM_PGSZ_1K 0x00060000 /* Page size, 1K words */
#define DRAM_PGSZ_512 0x00050000 /* Page size, 512 words */
#define DRAM_PGSZ_256 0x00040000 /* Page size, 256 words */
#define DRAM_PGSZ_128 0x00030000 /* Page size, 128 words */
#define DRAM_PGSZ_64 0x00020000 /* Page size, 64 words */
#define DRAM_PGSZ_32 0x00010000 /* Page size, 32 words */
#define DRAM_PGSZ_16 0x00000000 /* Page size, 16 words */
#define DRAM_PGMW 0x00008000 /* Page mode write enable */
#define DRAM_RFWE_0 0x00004000 /* Refresh write enable mode, bit 1 */
#define DRAM_RFWE_1 0x00002000 /* Refresh write enable mode, bit 0 */
#define DRAM_RFEN 0x00001000 /* Internal refresh enable */
#define DRAM_RDYEN 0x00000800 /* Internal ready generation */
#define DRAM_BFD 0x00000400 /* Block fetch disable */
#define DRAM_PE 0x00000200 /* Parity checking enable */
#define DRAM_RPC_3 0x00000180 /* RAS precharge, 3 */
#define DRAM_RPC_2 0x00000100 /* RAS precharge, 2 */
#define DRAM_RPC_1 0x00000080 /* RAS precharge, 1 */
#define DRAM_RPC_0 0x00000000 /* RAS precharge, 0 */
#define DRAM_RCD_3 0x00000060 /* RAS to CAS delay, 3 */
#define DRAM_RCD_2 0x00000040 /* RAS to CAS delay, 2 */
#define DRAM_RCD_1 0x00000020 /* RAS to CAS delay, 1 */
#define DRAM_RCD_0 0x00000000 /* RAS to CAS delay, 0 */
#define DRAM_CS 0x00000010 /* CAS short */
#define DRAM_CL_8_5 0x0000000f /* CAS length, 8.5 cycles */
#define DRAM_CL_7_5 0x0000000c /* CAS length, 7.5 cycles*/
#define DRAM_CL_6_5 0x0000000a /* CAS length, 6.5 cycles */
#define DRAM_CL_5_5 0x00000008 /* CAS length, 5.5 cycles */
#define DRAM_CL_4_5 0x00000006 /* CAS length, 4.5 cycles */
#define DRAM_CL_3_5 0x00000004 /* CAS length, 3.5 cycles*/
#define DRAM_CL_2_5 0x00000002 /* CAS length, 2.5 cycles */
#define DRAM_CL_1_5 0x00000000 /* CAS length, 1.5 cycles */
#define DRAM_DCE 0x00000001 /* DRAM controller enable */
/* Definitions for BIU/cache configuration register bits */
#define BIU_NOSTR 0x00020000 /* no instruction streaming */
#define BIU_LDSCH 0x00010000 /* enable load scheduling */
#define BIU_BGNT 0x00008000 /* enable bus grant */
#define BIU_NOPAD 0x00004000 /* no wait state */
#define BIU_RDPRI 0x00002000 /* enable read priority */
#define BIU_INTP 0x00001000 /* interrupt polarity */
#define BIU_IS1 0x00000800 /* enable Inst cache, set 1 */
#define BIU_IS0 0x00000400 /* enable Inst cache, set 0 */
#define BIU_IBLKSZ_16 0x00000300 /* Inst cache fill sz = 16 words */
#define BIU_IBLKSZ_8 0x00000200 /* Inst cache fill sz = 8 words */
#define BIU_IBLKSZ_4 0x00000100 /* Inst cache fill sz = 4 words */
#define BIU_IBLKSZ_2 0x00000000 /* Inst cache fill sz = 2 words */
#define BIU_DS 0x00000080 /* enable Data cache */
#define BIU_DBLKSZ_16 0x00000030 /* Data cache fill sz = 16 words */
#define BIU_DBLKSZ_8 0x00000020 /* Data cache fill sz = 8 words */
#define BIU_DBLKSZ_4 0x00000010 /* Data cache fill sz = 4 words */
#define BIU_DBLKSZ_2 0x00000000 /* Data cache fill sz = 2 words */
#define BIU_RAM 0x00000008 /* scratchpad RAM */
#define BIU_TAG 0x00000004 /* tag test mode */
#define BIU_INV 0x00000002 /* invalidate mode */
#define BIU_LOCK 0x00000001 /* lock mode */
/* Definitions for cache sizes */
#define LR33300_IC_SIZE 0x1000 /* 33300 Inst cache = 4Kbytes */
#define LR33310_IC_SIZE 0x1000 /* 33310 Inst cache = 4Kbytes */
/* Note: each set is 4Kbytes! */
#define LR33300_DC_SIZE 0x800 /* 33300 Data cache = 2Kbytes */
#define LR33310_DC_SIZE 0x1000 /* 33310 Data cache = 4Kbytes */
#ifdef __cplusplus
}
#endif
#endif /* __INClr333x0h */

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c/src/lib/libbsp/mips/genmongoosev/include/mongoose-v.h
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/**
* @file
*
* MIPS Mongoose-V specific information
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __MONGOOSEV_h
#define __MONGOOSEV_h
/*
* Macros to assist in accessing memory mapped Mongoose registers
*/
#define MONGOOSEV_READ( _base ) \
( *((volatile uint32_t*)(_base)) )
#define MONGOOSEV_WRITE( _base, _value ) \
( *((volatile uint32_t*)(_base)) = (_value) )
#define MONGOOSEV_READ_REGISTER( _base, _register ) \
( *((volatile uint32_t*)((_base) + (_register))) )
#define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \
( *((volatile uint32_t*)((_base) + (_register))) = (_value) )
/*
* Macros to read/write the Mongoose FPU control register.
*/
/*
* BIU and DRAM Registers
*/
#define MONGOOSEV_BIU_CACHE_CONFIGURATION_REGISTER 0xFFFE0130
#define MONGOOSEV_DRAM_CONFIGURATION_REGISTER 0xFFFE0120
#define MONGOOSEV_REFRESH_TIMER_INITIAL_COUNTER_REGISTER 0xFFFE0010
#define MONGOOSEV_WAIT_STATE_CONFIGURATION_REGISTER_BASE 0xFFFE0100
/*
* Peripheral Function Addresses
*
* NOTE: Status and Interrupt Cause use the same bits
*/
#define MONGOOSEV_PERIPHERAL_COMMAND_REGISTER 0xFFFE0180
#define MONGOOSEV_PERIPHERAL_STATUS_REGISTER 0xFFFE0184
#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER 0xFFFE0188
#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER 0xFFFE018C
#define MONGOOSEV_WATCHDOG 0xBE000000
/* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */
#define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS 0x0001
#define MONGOOSEV_UART_CMD_LOOPBACK_CTSN 0x0002
#define MONGOOSEV_UART_CMD_LOOPBACK_RXTX 0x0004
#define MONGOOSEV_UART_CMD_RX_ENABLE 0x001
#define MONGOOSEV_UART_CMD_RX_DISABLE 0x000
#define MONGOOSEV_UART_CMD_TX_ENABLE 0x002
#define MONGOOSEV_UART_CMD_TX_DISABLE 0x000
#define MONGOOSEV_UART_CMD_TX_READY 0x004
#define MONGOOSEV_UART_CMD_PARITY_ENABLE 0x008
#define MONGOOSEV_UART_CMD_PARITY_DISABLE 0x000
#define MONGOOSEV_UART_CMD_PARITY_EVEN 0x010
#define MONGOOSEV_UART_CMD_PARITY_ODD 0x000
#define MONGOOSEV_UART0_CMD_SHIFT 5
#define MONGOOSEV_UART1_CMD_SHIFT 11
#define MONGOOSEV_UART_CMD_TX_ENABLE_0 \
(MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_RX_ENABLE_0 \
(MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_TX_READY_0 \
(MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_ENABLE_0 \
(MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_DISABLE_0 \
(MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_EVEN_0 \
(MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_ODD_0 \
(MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_TX_ENABLE_1 \
(MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART1_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_RX_ENABLE_1 \
(MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART1_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_TX_READY_1 \
(MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART1_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_ENABLE_1 \
(MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART1_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_DISABLE_1 \
(MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART1_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_EVEN_1 \
(MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART1_CMD_SHIFT)
#define MONGOOSEV_UART_CMD_PARITY_ODD_1 \
(MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART1_CMD_SHIFT)
/* UART Bits in Peripheral Status and Interrupt Cause Register */
#define MONGOOSEV_UART_RX_FRAME_ERROR 0x0001
#define MONGOOSEV_UART_RX_OVERRUN_ERROR 0x0002
#define MONGOOSEV_UART_TX_EMPTY 0x0004
#define MONGOOSEV_UART_TX_READY 0x0008
#define MONGOOSEV_UART_RX_READY 0x0010
#define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013
#define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F
/*
* The Peripheral Interrupt Status, Cause, and Mask registers have the
* same bit assignments although some revisions of the document have
* the Cause and Status registers incorrect.
*/
#define MONGOOSEV_UART0_IRQ_SHIFT 11
#define MONGOOSEV_UART1_IRQ_SHIFT 17
#define MONGOOSEV_UART_FRAME_ERROR_0 \
(MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART0_IRQ_SHIFT)
#define MONGOOSEV_UART_RX_OVERRUN_ERROR_0 \
(MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART0_IRQ_SHIFT)
#define MONGOOSEV_UART_TX_EMPTY_0 \
(MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART0_IRQ_SHIFT)
#define MONGOOSEV_UART_TX_READY_0 \
(MONGOOSEV_UART_TX_READY << MONGOOSEV_UART0_IRQ_SHIFT)
#define MONGOOSEV_UART_RX_READY_0 \
(MONGOOSEV_UART_RX_READY << MONGOOSEV_UART0_IRQ_SHIFT)
#define MONGOOSEV_UART_FRAME_ERROR_1 \
(MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_RX_OVERRUN_ERROR_1 \
(MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_TX_EMPTY_1 \
(MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_TX_READY_1 \
(MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
#define MONGOOSEV_UART_RX_READY_1 \
(MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
/*
* Bits in the Peripheral Interrupt Mask Register
*/
/*
** Interrupt Status/Cause/Mask register bits - from 31 to 0
*/
#define MONGOOSEV_EDAC_SERR_BIT 0x80000000
#define MONGOOSEV_EDAC_MERR_BIT 0x40000000
/* 29 - 24 reserved */
#define MONGOOSEV_MAVN_WRITE_ACCESS 0x00800000
#define MONGOOSEV_MAVN_READ_ACCESS 0x00400000
#define MONGOOSEV_UART_1_RX_READY 0x00200000
#define MONGOOSEV_UART_1_TX_READY 0x00100000
#define MONGOOSEV_UART_1_TX_EMPTY 0x00080000
#define MONGOOSEV_UART_1_RX_OVERRUN 0x00040000
#define MONGOOSEV_UART_1_FRAME_ERROR 0x00020000
#define MONGOOSEV_RESERVED_16 0x00010000
#define MONGOOSEV_UART_0_RX_READY 0x00008000
#define MONGOOSEV_UART_0_TX_READY 0x00004000
#define MONGOOSEV_UART_0_TX_EMPTY 0x00002000
#define MONGOOSEV_UART_0_RX_OVERRUN 0x00001000
#define MONGOOSEV_UART_0_FRAME_ERROR 0x00000800
#define MONGOOSEV_RESERVED_10 0x00000400
#define MONGOOSEV_EXTERN_INT_9 0x00000200
#define MONGOOSEV_EXTERN_INT_8 0x00000100
#define MONGOOSEV_EXTERN_INT_7 0x00000080
#define MONGOOSEV_EXTERN_INT_6 0x00000040
#define MONGOOSEV_EXTERN_INT_5 0x00000020
#define MONGOOSEV_EXTERN_INT_4 0x00000010
#define MONGOOSEV_EXTERN_INT_3 0x00000008
#define MONGOOSEV_EXTERN_INT_2 0x00000004
#define MONGOOSEV_EXTERN_INT_1 0x00000002
#define MONGOOSEV_EXTERN_INT_0 0x00000001
/*
** Peripheral Command bits (non-uart, those are defined above)
*/
#define MONGOOSEV_COMMAND_ENABLE_EDAC MONGOOSEV_EDAC_SERR_BIT
#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT
/*
* EDAC Registers
*/
#define MONGOOSEV_EDAC_ERROR_ADDRESS_REGISTER 0xFFFE0190
#define MONGOOSEV_EDAC_PARITY_TEST_MODE_REGISTER 0xFFFE0194
/*
* MAVN Registers
*/
#define MONGOOSEV_MAVN_TEST_REGISTER 0xFFFE01B4
#define MONGOOSEV_MAVN_ACCESS_PRIVILEGE_REGISTER 0xFFFE01B8
#define MONGOOSEV_MAVN_ACCESS_VIOLATION_REGISTER 0xFFFE01BC
#define MONGOOSEV_MAVN_RANGE_0_REGISTER 0xFFFE01C0
#define MONGOOSEV_MAVN_RANGE_1_REGISTER 0xFFFE01C4
#define MONGOOSEV_MAVN_RANGE_2_REGISTER 0xFFFE01C8
#define MONGOOSEV_MAVN_RANGE_3_REGISTER 0xFFFE01CC
#define MONGOOSEV_MAVN_RANGE_4_REGISTER 0xFFFE01D0
#define MONGOOSEV_MAVN_RANGE_5_REGISTER 0xFFFE01D4
#define MONGOOSEV_MAVN_RANGE_6_REGISTER 0xFFFE01D8
#define MONGOOSEV_MAVN_RANGE_7_REGISTER 0xFFFE01DC
/*
* Timer Base Addresses, Offsets, and Values
*/
#define MONGOOSEV_TIMER1_BASE 0xFFFE0000
#define MONGOOSEV_TIMER2_BASE 0xFFFE0008
#define MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER 0
#define MONGOOSEV_TIMER_CONTROL_REGISTER 4
/* Timer Control Register Constants */
#define MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE 0x04
#define MONGOOSEV_TIMER_CONTROL_INTERRUPT_ENABLE 0x02
#define MONGOOSEV_TIMER_CONTROL_TIMEOUT 0x01
/*
* UART Base Addresses and Offsets
*
* Many bits in the peripheral command register are UART related
* and the bits are defined there.
*/
#define MONGOOSEV_UART0_BASE 0xFFFE01E8
#define MONGOOSEV_UART1_BASE 0xFFFE01F4
#define MONGOOSEV_RX_BUFFER 0
#define MONGOOSEV_TX_BUFFER 4
#define MONGOOSEV_BAUD_RATE 8
/*
* Status Register Bits
*/
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
#define SR_BEV 0x00400000 /* use boot exception vectors */
#define SR_TS 0x00200000 /* TLB shutdown */
#define SR_PE 0x00100000 /* cache parity error */
#define SR_CM 0x00080000 /* cache miss */
#define SR_PZ 0x00040000 /* cache parity zero */
#define SR_SWC 0x00020000 /* swap cache */
#define SR_ISC 0x00010000 /* Isolate data cache */
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
#define SR_IMASK8 0x00000000 /* mask level 8 */
#define SR_IMASK7 0x00008000 /* mask level 7 */
#define SR_IMASK6 0x0000c000 /* mask level 6 */
#define SR_IMASK5 0x0000e000 /* mask level 5 */
#define SR_IMASK4 0x0000f000 /* mask level 4 */
#define SR_IMASK3 0x0000f800 /* mask level 3 */
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
#define SR_IBIT8 0x00008000 /* bit level 8 */
#define SR_IBIT7 0x00004000 /* bit level 7 */
#define SR_IBIT6 0x00002000 /* bit level 6 */
#define SR_IBIT5 0x00001000 /* bit level 5 */
#define SR_IBIT4 0x00000800 /* bit level 4 */
#define SR_IBIT3 0x00000400 /* bit level 3 */
#define SR_IBIT2 0x00000200 /* bit level 2 */
#define SR_IBIT1 0x00000100 /* bit level 1 */
#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
#define SR_KUMSK (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC)
#define SR_IMASKSHIFT 8
#define MONGOOSEV_IC_SIZE 0x1000 /* instruction cache = 4Kbytes */
#define MONGOOSEV_DC_SIZE 0x800 /* data cache 2Kbytes */
#endif

229
c/src/lib/libbsp/mips/genmongoosev/include/r3000.h
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@@ -1,229 +0,0 @@
/* r3000.h - mips R3k architecture header file */
/*
* Copyright 1985-1997 by MIPS Computer Systems, Inc.
*/
/*
modification history
--------------------
01k,17jan96,kkk made MINCACHE 512 (spr# 7556)
01j,13jan96,kkk undid 01i.
01i,18dec96,tam enabled FP exceptions via FP_TASK_STATUS (spr #7665).
01h,13sep93,caf fixed K2SIZE (SPR #1880).
01g,22sep92,rrr added support for c++
01f,02jun92,ajm the 5.0.5 merge
01e,26may92,rrr the tree shuffle
01d,04oct91,rrr passed through the ansification filter
-changed copyright notice
01c,23jul91,ajm changed default fp status register to all exceptions
off forcing the user to enable exceptions for signals
Enable FPA interrupt to tasks
01b,08jul91,ajm added SR_KUMSK for exception handling
01a,21feb91,ajm written.
*/
#ifndef __INCr3000h
#define __INCr3000h
#ifdef __cplusplus
extern "C" {
#endif
/*
* Segment base addresses and sizes
*/
#define K0BASE 0x80000000
#define K0SIZE 0x20000000
#define K1BASE 0xA0000000
#define K1SIZE 0x20000000
#define K2BASE 0xC0000000
#define K2SIZE 0x40000000
/*
* Exception vectors
*/
#define UT_VEC K0BASE /* utlbmiss vector */
#define E_VEC (K0BASE+0x80) /* exception vector */
#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
/*
* Address conversion macros
*/
#define K0_TO_K1(x) ((unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */
#define K1_TO_K0(x) ((unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
#define K0_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */
#define K1_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */
#define PHYS_TO_K0(x) ((unsigned)(x)|0x80000000) /* physical to kseg0 */
#define PHYS_TO_K1(x) ((unsigned)(x)|0xA0000000) /* physical to kseg1 */
/*
* Address predicates
*/
#define IS_KSEG0(x) ((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE)
#define IS_KSEG1(x) ((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE)
#define IS_KUSEG(x) ((unsigned)(x) < K0BASE)
/*
* Cache size constants
*/
#define MINCACHE +(1*512) /* leading plus for mas's benefit */
#define MAXCACHE +(256*1024) /* leading plus for mas's benefit */
/*
* Cause bit definitions
*/
#define CAUSE_BD 0x80000000 /* Branch delay slot */
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
#define CAUSE_CESHIFT 28
#define CAUSE_IP8 0x00008000 /* External level 8 pending */
#define CAUSE_IP7 0x00004000 /* External level 7 pending */
#define CAUSE_IP6 0x00002000 /* External level 6 pending */
#define CAUSE_IP5 0x00001000 /* External level 5 pending */
#define CAUSE_IP4 0x00000800 /* External level 4 pending */
#define CAUSE_IP3 0x00000400 /* External level 3 pending */
#define CAUSE_SW2 0x00000200 /* Software level 2 pending */
#define CAUSE_SW1 0x00000100 /* Software level 1 pending */
#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
#define CAUSE_IPSHIFT 8
#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */
#define CAUSE_EXCSHIFT 2
/*
* Status definition bits
*/
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
#define SR_BEV 0x00400000 /* use boot exception vectors */
#define SR_TS 0x00200000 /* TLB shutdown */
#define SR_PE 0x00100000 /* cache parity error */
#define SR_CM 0x00080000 /* cache miss */
#define SR_PZ 0x00040000 /* cache parity zero */
#define SR_SWC 0x00020000 /* swap cache */
#define SR_ISC 0x00010000 /* Isolate data cache */
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
#define SR_IMASK8 0x00000000 /* mask level 8 */
#define SR_IMASK7 0x00008000 /* mask level 7 */
#define SR_IMASK6 0x0000c000 /* mask level 6 */
#define SR_IMASK5 0x0000e000 /* mask level 5 */
#define SR_IMASK4 0x0000f000 /* mask level 4 */
#define SR_IMASK3 0x0000f800 /* mask level 3 */
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
#define SR_IBIT8 0x00008000 /* bit level 8 */
#define SR_IBIT7 0x00004000 /* bit level 7 */
#define SR_IBIT6 0x00002000 /* bit level 6 */
#define SR_IBIT5 0x00001000 /* bit level 5 */
#define SR_IBIT4 0x00000800 /* bit level 4 */
#define SR_IBIT3 0x00000400 /* bit level 3 */
#define SR_IBIT2 0x00000200 /* bit level 2 */
#define SR_IBIT1 0x00000100 /* bit level 1 */
#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
#define SR_KUMSK (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC)
#define SR_IMASKSHIFT 8
/*
* fpa definitions
*/
#define FP_ROUND 0x3 /* r3010 round mode mask */
#define FP_STICKY 0x7c /* r3010 sticky bits mask */
#define FP_ENABLE 0xf80 /* r3010 enable mode mask */
#define FP_EXC 0x3f000 /* r3010 exception mask */
#define FP_ROUND_N 0x0 /* round to nearest */
#define FP_ROUND_Z 0x1 /* round to zero */
#define FP_ROUND_P 0x2 /* round to + infinity */
#define FP_ROUND_M 0x3 /* round to - infinity */
#define FP_STICKY_I 0x4 /* sticky inexact operation */
#define FP_STICKY_U 0x8 /* sticky underflow */
#define FP_STICKY_O 0x10 /* sticky overflow */
#define FP_STICKY_Z 0x20 /* sticky divide by zero */
#define FP_STICKY_V 0x40 /* sticky invalid operation */
#define FP_ENABLE_I 0x80 /* enable inexact operation */
#define FP_ENABLE_U 0x100 /* enable underflow exc */
#define FP_ENABLE_O 0x200 /* enable overflow exc */
#define FP_ENABLE_Z 0x400 /* enable divide by zero exc */
#define FP_ENABLE_V 0x800 /* enable invalid operation exc */
#define FP_EXC_I 0x1000 /* inexact operation */
#define FP_EXC_U 0x2000 /* underflow */
#define FP_EXC_O 0x4000 /* overflow */
#define FP_EXC_Z 0x8000 /* divide by zero */
#define FP_EXC_V 0x10000 /* invalid operation */
#define FP_EXC_E 0x20000 /* unimplemented operation */
#define FP_COND 0x800000 /* condition bit */
#define FP_EXC_SHIFT 12
#define FP_ENABLE_SHIFT 7
#define FP_EXC_MASK (FP_EXC_I|FP_EXC_U|FP_EXC_O|FP_EXC_Z|FP_EXC_V|FP_EXC_E)
#define FP_ENABLE_MASK (FP_ENABLE_I|FP_ENABLE_U|FP_ENABLE_O|FP_ENABLE_Z| \
FP_ENABLE_V)
#define FP_TASK_STATUS 0x0 /* all FP exceptions are disabled
(see fppAlib.s and spr #7665) */
/*
* tlb definitions
*/
#define TLB_ENTRIES 64
#define TLBLO_PFNMASK 0xfffff000
#define TLBLO_PFNSHIFT 12
#define TLBLO_N 0x800 /* non-cacheable */
#define TLBLO_D 0x400 /* writeable */
#define TLBLO_V 0x200 /* valid bit */
#define TLBHI_VPNMASK 0xfffff000
#define TLBHI_VPNSHIFT 12
#define TLBHI_PIDMASK 0xfc0
#define TLBHI_PIDSHIFT 6
#define TLBHI_NPID 64
#define TLBINX_PROBE 0x80000000
#define TLBINX_INXMASK 0x00003f00
#define TLBINX_INXSHIFT 8
#define TLBRAND_RANDMASK 0x00003f00
#define TLBRAND_RANDSHIFT 8
#define TLBCTXT_BASEMASK 0xffe00000
#define TLBCTXT_BASESHIFT 21
#define TLBCTXT_VPNMASK 0x001ffffc
#define TLBCTXT_VPNSHIFT 2
/*
* Coprocessor 0 operations
*/
#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
#define C0_RFE 0x10 /* restore for exception */
#ifdef __cplusplus
}
#endif
#endif /* __INCr3000h */

36
c/src/lib/libbsp/mips/genmongoosev/include/tm27.h
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@@ -1,36 +0,0 @@
/**
* @file
*/
/*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Define the interrupt mechanism for Time Test 27
*/
#include <bsp/irq.h>
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
rtems_interrupt_handler_install( \
MONGOOSEV_IRQ_SOFTWARE_1, "benchmark", 0, \
(rtems_interrupt_handler)handler, NULL );
#define Cause_tm27_intr() assertSoftwareInterrupt(0);
#define Clear_tm27_intr() /* empty */
#define Lower_tm27_intr() /* empty */
#endif

257
c/src/lib/libbsp/mips/genmongoosev/irq/vectorisrs.c
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@@ -1,257 +0,0 @@
/**
* @file
*
* ISR Vectoring support for the Synova Mongoose-V.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <stdlib.h>
#include <bsp/mongoose-v.h>
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#include <rtems/irq.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <rtems/bspIo.h> /* for printk */
int mips_default_isr( int vector );
int assertSoftwareInterrupt( uint32_t n );
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
int mips_default_isr( int vector )
{
unsigned int sr, sr2;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
sr2 = sr & ~0xffff;
mips_set_sr(sr2);
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr );
rtems_fatal_error_occurred(1);
return 0;
}
/* userspace routine to assert either software interrupt */
int assertSoftwareInterrupt( uint32_t n )
{
if( n<2 )
{
uint32_t c;
mips_get_cause(c);
c = ((n+1) << CAUSE_IPSHIFT);
mips_set_cause(c);
return n;
}
else return -1;
}
/*
* Instrumentation tweaks for isr timing measurement, turning them off
* via this #if will remove the code entirely from the RTEMS kernel.
*/
#if 0
#define SET_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 1;
#define CLR_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 0;
#else
#define SET_ISR_FLAG( offset )
#define CLR_ISR_FLAG( offset )
#endif
static volatile uint32_t _ivcause, _ivsr;
static uint32_t READ_CAUSE(void)
{
mips_get_cause( _ivcause );
_ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */
return ((_ivcause & (_ivsr & SR_IMASK)) >> CAUSE_IPSHIFT);
}
/*
* This rather strangely coded routine enforces an interrupt priority
* scheme. As it runs thru finding whichever interrupt caused it to get
* here, it test for other interrupts arriving in the meantime (maybe it
* occured while the vector code is executing for instance). Each new
* interrupt will be served in order of its priority. In an effort to
* minimize overhead, the cause register is only fetched after an
* interrupt is serviced. Because of the intvect goto's, this routine
* will only exit when all interrupts have been serviced and no more
* have arrived, this improves interrupt latency at the cost of
* increasing scheduling jitter; though scheduling jitter should only
* become apparent in high interrupt load conditions.
*/
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
uint32_t cshifted;
/* mips_get_sr( sr ); */
_ivsr = frame->c0_sr;
cshifted = READ_CAUSE();
intvect:
if( cshifted & 0x3 )
{
/* making the software interrupt the highest priority is kind of
* stupid, but it makes the bit testing lots easier. On the other
* hand, these ints are infrequently used and the testing overhead
* is minimal. Who knows, high-priority software ints might be
* handy in some situation.
*/
/* unset both software int cause bits */
mips_set_cause( _ivcause & ~(3 << CAUSE_IPSHIFT) );
if ( cshifted & 0x01 ) /* SW[0] */
{
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_SOFTWARE_1 );
}
if ( cshifted & 0x02 ) /* SW[1] */
{
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_SOFTWARE_2 );
}
cshifted = READ_CAUSE();
}
if ( cshifted & 0x04 ) /* IP[0] ==> INT0 == TIMER1 */
{
SET_ISR_FLAG( 0x4 );
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_TIMER1 );
CLR_ISR_FLAG( 0x4 );
if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect;
}
if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/
{
SET_ISR_FLAG( 0x8 );
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_TIMER2 );
CLR_ISR_FLAG( 0x8 );
if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect;
}
if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */
{
SET_ISR_FLAG( 0x10 );
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT2 );
CLR_ISR_FLAG( 0x10 );
if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect;
}
if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */
{
SET_ISR_FLAG( 0x20 );
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT3 );
CLR_ISR_FLAG( 0x20 );
if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect;
}
if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */
{
SET_ISR_FLAG( 0x40 );
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT4 );
CLR_ISR_FLAG( 0x40 );
if( (cshifted = READ_CAUSE()) & 0x3f ) goto intvect;
}
if ( cshifted & 0x80 ) /* IP[5] ==> INT5, peripheral interrupt */
{
uint32_t bit;
uint32_t pf_icr, pf_mask, pf_reset = 0;
uint32_t i, m;
pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
/*
for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 )
{
if ( pf_icr & pf_mask )
{
SET_ISR_FLAG( 0x80 + (bit*4) );
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit );
CLR_ISR_FLAG( 0x80 + (bit*4) );
pf_reset |= pf_mask;
if( (cshifted = READ_CAUSE()) & 0xff ) break;
}
}
*/
/*
* iterate thru 32 bits in 4 chunks of 8 bits each. This lets us
* quickly get past unasserted interrupts instead of flogging our
* way thru a full 32 bits. pf_mask shifts left 8 bits at a time
* to serve as a interrupt cause test mask.
*/
for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) )
{
if ( pf_icr & pf_mask )
{
/* one or more of the 8 bits we're testing is high */
m = (1 << bit);
/* iterate thru the 8 bits, servicing any of the interrupts */
for(i=0; (i<8 && pf_icr); (i++, m <<= 1))
{
if( pf_icr & m )
{
SET_ISR_FLAG( 0x80 + ((bit + i) * 4) );
bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit + i );
CLR_ISR_FLAG( 0x80 + ((bit + i) * 4) );
/* or each serviced interrupt into our interrupt clear mask */
pf_reset |= m;
/* xor off each int we service so we can immediately
* exit once we get the last one
*/
pf_icr %= m;
/* if another interrupt has arrived, jump out right
* away but be sure to reset all the interrupts we've
* already serviced
*/
if( READ_CAUSE() & 0xff ) goto pfexit;
}
}
}
}
pfexit:
MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, pf_reset );
}
/*
* this is a last ditch interrupt check, if an interrupt arrives
* after this step, servicing it will incur the entire interrupt
* overhead cost.
*/
if( (cshifted = READ_CAUSE()) & 0xff ) goto intvect;
}

16
c/src/lib/libbsp/mips/genmongoosev/make/custom/genmongoosev.cfg
View File

@@ -1,16 +0,0 @@
#
# Config file for "generic" Mongoose-V board
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=mips
RTEMS_CPU_MODEL=mongoosev
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#
CPU_CFLAGS = -mips1 -G0
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g

103
c/src/lib/libbsp/mips/genmongoosev/preinstall.am
View File

@@ -1,103 +0,0 @@
## Automatically generated by ampolish3 - Do not edit
if AMPOLISH3
$(srcdir)/preinstall.am: Makefile.am
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
endif
PREINSTALL_DIRS =
DISTCLEANFILES += $(PREINSTALL_DIRS)
all-am: $(PREINSTALL_FILES)
PREINSTALL_FILES =
CLEANFILES = $(PREINSTALL_FILES)
all-local: $(TMPINSTALL_FILES)
TMPINSTALL_FILES =
CLEANFILES += $(TMPINSTALL_FILES)
$(PROJECT_LIB)/$(dirstamp):
@$(MKDIR_P) $(PROJECT_LIB)
@: > $(PROJECT_LIB)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
$(PROJECT_INCLUDE)/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)
@: > $(PROJECT_INCLUDE)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
$(PROJECT_INCLUDE)/bsp/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
$(PROJECT_INCLUDE)/bsp/regs.h: start/regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/regs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
$(PROJECT_INCLUDE)/bsp/lr33000.h: include/lr33000.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lr33000.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lr33000.h
$(PROJECT_INCLUDE)/bsp/lr333x0.h: include/lr333x0.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lr333x0.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lr333x0.h
$(PROJECT_INCLUDE)/bsp/mongoose-v.h: include/mongoose-v.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mongoose-v.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mongoose-v.h
$(PROJECT_INCLUDE)/bsp/r3000.h: include/r3000.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/r3000.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/r3000.h
$(PROJECT_INCLUDE)/bsp/mg5uart.h: console/mg5uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mg5uart.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mg5uart.h
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds

379
c/src/lib/libbsp/mips/genmongoosev/start/mg5.h
View File

@@ -1,379 +0,0 @@
/*
**
** Section 1: Registers
**
*/
/*
**
*/
#define PMON_ADDRESS 0xbfc00000
/*
** Mongoose V Peripheral Function Registers
*/
#define MG5_COMMAND_REG 0xfffe0180
/*
** Extended Interrupt Registers
** These registers are used as follows:
** 1. The mask register is used to allow peripheral function and external
** interrupts to function. To enable an interrupt, set the appropriate
** bit.
** 2. The status register contains the state of the peripheral functions
** and external devices. This register should be read to poll devices
** such as the uart when the interrupts are not enabled. Writing to this
** register will clear the interrupt.
** 3. The Cause register is similar to the status register, with the
** exception that it only shows the bits that are set in the mask
** register. This register should be read to determine which interrupt(s)
** need to be serviced. This register when written to will CAUSE the interrupt.
*/
#define MG5_INT_STATUS_REG 0xfffe0184 /* Read to determine state/Write to clear */
#define MG5_INT_CAUSE_REG 0xfffe0188 /* Read to determine int/Write to cause int */
#define MG5_INT_MASK_REG 0xfffe018c /* Set bit here to enable int */
/*
** EDAC Registers
*/
#define MG5_EDAC_ADDR_REG 0xfffe0190 /* edac error address */
#define MG5_EDAC_PARITY_REG 0xfffe0194 /* edac parity */
/*
** High speed serial port registers
** This section is reserved for future Mongoose Processors
*/
/*
** Floating Point Register
*/
#define MG5_FPU_CNTRL_REG 0xfffe0020 /* FPU control register */
/*
** MAVN Registers
*/
#define MG5_MAVN_TEST_REG 0xfffe01b4 /* test mavn */
#define MG5_MAVN_PRIVLEGE_REG 0xfffe01b8 /* privlege bits */
#define MG5_MAVN_VIOLATION_REG 0xfffe01bc /* address of violation */
#define MG5_MAVN_RANGE_0_REG 0xfffe01c0 /* Range 0 */
#define MG5_MAVN_RANGE_1_REG 0xfffe01c4 /* Range 1 */
#define MG5_MAVN_RANGE_2_REG 0xfffe01c8 /* Range 2 */
#define MG5_MAVN_RANGE_3_REG 0xfffe01cc /* Range 3 */
#define MG5_MAVN_RANGE_4_REG 0xfffe01d0 /* Range 4 */
#define MG5_MAVN_RANGE_5_REG 0xfffe01d4 /* Range 5 */
/*
** Uart Specific Peripheral Function Registers
*/
#define MG5_UART_0_RX_REG 0xfffe01e8
#define MG5_UART_0_TX_REG 0xfffe01ec
#define MG5_UART_0_BAUD_REG 0xfffe01f0
#define MG5_UART_1_RX_REG 0xfffe01f4
#define MG5_UART_1_TX_REG 0xfffe01f8
#define MG5_UART_1_BAUD_REG 0xfffe01fc
/*
** Section 2: Bit definitions
**
*/
/*
** Command Register Bits - defined from 31 to 0
*/
#define EDAC_ENABLE_BIT 0x80000000
#define EDAC_OVERRIDE_BIT 0x40000000
/* 29 - 16 reserved */
#define UART_1_PARITY_EVEN_BIT 0x00008000
#define UART_1_PARITY_ENABLE_BIT 0x00004000
#define UART_1_RTS_BIT 0x00002000
#define UART_1_TX_ENABLE_BIT 0x00001000
#define UART_1_RX_ENABLE_BIT 0x00000800
#define UART_1_TX_BREAK_BIT 0x00000400
#define UART_0_PARITY_EVEN_BIT 0x00000200
#define UART_0_PARITY_ENABLE_BIT 0x00000100
#define UART_0_RTS_BIT 0x00000080
#define UART_0_TX_ENABLE_BIT 0x00000040
#define UART_0_RX_ENABLE_BIT 0x00000020
#define UART_0_TX_BREAK_BIT 0x00000010
#define UART_LOOPBACK_MODE_BIT 0x00000008
#define UART_CTSN_TEST_BIT 0x00000004
#define UART_RESET_BIT 0x00000002
/*
** Interrupt Status/Cause/Mask register bits - from 31 to 0
*/
#define EDAC_SERR_BIT 0x80000000
#define EDAC_MERR_BIT 0x40000000
/* 29 - 24 reserved */
#define UART_0_RX_READY_BIT 0x00008000
#define UART_0_TX_READY_BIT 0x00004000
#define UART_0_TX_EMPTY_BIT 0x00002000
#define UART_0_RX_OVERRUN_BIT 0x00001000
#define UART_0_FRAME_ERR_BIT 0x00000800
#define UART_0_RESERVED_BIT 0x00000400
#define UART_1_RX_READY_BIT 0x00200000
#define UART_1_TX_READY_BIT 0x00100000
#define UART_1_TX_EMPTY_BIT 0x00080000
#define UART_1_RX_OVERRUN_BIT 0x00040000
#define UART_1_FRAME_ERR_BIT 0x00020000
#define UART_1_RESERVED_BIT 0x00010000
#define MAVN_WRITE_ACC_BIT 0x00400000
#define MAVN_READ_ACC_BIT 0x00800000
#define EXTERN_INT_9_BIT 0x00000200
#define EXTERN_INT_8_BIT 0x00000100
#define EXTERN_INT_7_BIT 0x00000080
#define EXTERN_INT_6_BIT 0x00000040
#define EXTERN_INT_5_BIT 0x00000020
#define EXTERN_INT_4_BIT 0x00000010
#define EXTERN_INT_3_BIT 0x00000008
#define EXTERN_INT_2_BIT 0x00000004
#define EXTERN_INT_1_BIT 0x00000002
#define EXTERN_INT_0_BIT 0x00000001
/*
** MAVN Range Bits
*/
#define MAVN_RANGE_0_WRITE_BIT 0x00000001
#define MAVN_RANGE_1_WRITE_BIT 0x00000002
#define MAVN_RANGE_2_WRITE_BIT 0x00000004
#define MAVN_RANGE_3_WRITE_BIT 0x00000008
#define MAVN_RANGE_4_WRITE_BIT 0x00000010
#define MAVN_RANGE_5_WRITE_BIT 0x00000020
#define MAVN_GLOBAL_WRITE_BIT 0x00000200
#define MAVN_RANGE_0_READ_BIT 0x00000400
#define MAVN_RANGE_1_READ_BIT 0x00000800
#define MAVN_RANGE_2_READ_BIT 0x00001000
#define MAVN_RANGE_3_READ_BIT 0x00002000
#define MAVN_RANGE_4_READ_BIT 0x00004000
#define MAVN_RANGE_5_READ_BIT 0x00008000
#define MAVN_GLOBAL_READ_BIT 0x00080000
#define MAVN_ENABLE_BIT 0x80000000
#define MAVN_TEST_BIT 0x40000000
#define MAVN_RANGE_NO_ACESS 0x00000000
#define MAVN_PS_CODE_512 0x00000009
#define MAVN_PS_CODE_1K 0x0000000a
#define MAVN_PS_CODE_2K 0x0000000b
#define MAVN_PS_CODE_4K 0x0000000c
#define MAVN_PS_CODE_8K 0x0000000d
#define MAVN_PS_CODE_16K 0x0000000e
#define MAVN_PS_CODE_32K 0x0000000f
#define MAVN_PS_CODE_64K 0x00000010
#define MAVN_PS_CODE_128K 0x00000011
#define MAVN_PS_CODE_256K 0x00000012
#define MAVN_PS_CODE_512K 0x00000013
#define MAVN_PS_CODE_1M 0x00000014
#define MAVN_PS_CODE_2M 0x00000015
/*
** FPU Control Bits
*/
#define FPU_CNTRL_CONDITION 0x00800000
#define FPU_CNTRL_EXCEPT_E 0x00020000
#define FPU_CNTRL_EXCEPT_V 0x00010000
#define FPU_CNTRL_EXCEPT_Z 0x00008000
#define FPU_CNTRL_EXCEPT_O 0x00004000
#define FPU_CNTRL_EXCEPT_U 0x00002000
#define FPU_CNTRL_EXCEPT_I 0x00001000
#define FPU_CNTRL_TRAP_V 0x00000800
#define FPU_CNTRL_TRAP_Z 0x00000400
#define FPU_CNTRL_TRAP_O 0x00000200
#define FPU_CNTRL_TRAP_U 0x00000100
#define FPU_CNTRL_TRAP_I 0x00000080
#define FPU_CNTRL_STICKY_V 0x00000040
#define FPU_CNTRL_STICKY_Z 0x00000020
#define FPU_CNTRL_STICKY_O 0x00000010
#define FPU_CNTRL_STICKY_U 0x00000008
#define FPU_CNTRL_STICKY_I 0x00000004
#define FPU_CNTRL_ROUND_RN 0x00000000
#define FPU_CNTRL_ROUND_RZ 0x00000001
#define FPU_CNTRL_ROUND_RP 0x00000002
#define FPU_CNTRL_ROUND_RM 0x00000003
#define FPU_EXCEPTIONS FPU_CNTRL_TRAP_V|FPU_CNTRL_TRAP_Z|FPU_CNTRL_TRAP_O|FPU_CNTRL_TRAP_U|FPU_CNTRL_TRAP_I
#define FPU_CONFIGURATION FPU_EXCEPTIONS|FPU_CNTRL_ROUND_RN
/*
**
** Section 3 -- Masks
**
*/
#define UART_TX_BAUD_MASK 0x00007FFF
#define UART_RX_BAUD_MASK 0x7FFF0000
#define UART_DATA_MASK 0x000000FF
#define UART_TX_BAUD_4800(x) ((((x*1000000)/4800) - 1) & UART_TX_BAUD_MASK)
#define UART_TX_BAUD_9600(x) ((((x*1000000)/9600) - 1) & UART_TX_BAUD_MASK)
#define UART_TX_BAUD_19200(x) ((((x*1000000)/19200) - 1)& UART_TX_BAUD_MASK)
#define UART_TX_BAUD_38400(x) ((((x*1000000)/38400) - 1)& UART_TX_BAUD_MASK)
#define UART_RX_BAUD_4800(x) (((((x*1000000)/4800) - 1) << 16) & UART_RX_BAUD_MASK)
#define UART_RX_BAUD_9600(x) (((((x*1000000)/9600) - 1) << 16) & UART_RX_BAUD_MASK)
#define UART_RX_BAUD_19200(x) (((((x*1000000)/19200) - 1) << 16)& UART_RX_BAUD_MASK)
#define UART_RX_BAUD_38400(x) (((((x*1000000)/38400) - 1) << 16)& UART_RX_BAUD_MASK)
#define UART_BAUD_4800(x) ((((x*1000000)/4800) - 1) & UART_TX_BAUD_MASK) | (((((x*1000000)/4800) - 1) << 16) & UART_RX_BAUD_MASK)
#define UART_BAUD_9600(x) ((((x*1000000)/9600) - 1) & UART_TX_BAUD_MASK) | (((((x*1000000)/9600) - 1) << 16) & UART_RX_BAUD_MASK)
#define UART_BAUD_19200(x) ((((x*1000000)/19200) - 1)& UART_TX_BAUD_MASK) | (((((x*1000000)/19200) - 1) << 16)& UART_RX_BAUD_MASK)
#define UART_BAUD_38400(x) ((((x*1000000)/38400) - 1)& UART_TX_BAUD_MASK) | (((((x*1000000)/38400) - 1) << 16)& UART_RX_BAUD_MASK)
#define EDAC_PARITY_MASK 0x000000FF
#define MAVN_START_ADDR_MASK 0xFFFFFE00
#define MAVN_PS_CODE_MASK 0x0000001F
/* lr33000.h - defines for LSI Logic LR33000 */
/* Define counter/timer register addresses */
#define M_TIC1 0xfffe0000 /* timer 1 initial count */
#define M_TC1 0xfffe0004 /* timer 1 control */
#define M_TIC2 0xfffe0008 /* timer 2 initial count */
#define M_TC2 0xfffe000c /* timer 2 control */
#define M_RTIC 0xfffe0010 /* refresh timer */
#ifdef LANGUAGE_C
#define TIC1 (*((volatile unsigned long *)M_TIC1)) /* timer1 count */
#define TC1 (*((volatile unsigned long *)M_TC1)) /* timer1 cntrl */
#define TIC2 (*((volatile unsigned long *)M_TIC2)) /* timer2 count */
#define TC2 (*((volatile unsigned long *)M_TC2)) /* timer2 cntrl */
#define RTIC (*((volatile unsigned long *)M_RTIC)) /* refrsh timer */
#endif
/* Definitions for counter/timer control register bits */
#define TC_CE 0x00000004 /* count enable */
#define TC_IE 0x00000002 /* interrupt enable */
#define TC_INT 0x00000001 /* interrupt request */
/* lr33000.h */
#define _LR33300_
#define M_SRAM 0xfffe0100 /* SRAM config reg */
#define M_SPEC0 0xfffe0104
#define M_SPEC1 0xfffe0108
#define M_SPEC2 0xfffe010c
#define M_SPEC3 0xfffe0110
#define M_DRAM 0xfffe0120 /* DRAM config reg */
#ifdef LANGUAGE_C
#define SRAM (*((volatile unsigned long *)M_SRAM))
#define SPEC0 (*((volatile unsigned long *)M_SPEC0))
#define SPEC1 (*((volatile unsigned long *)M_SPEC1))
#define SPEC2 (*((volatile unsigned long *)M_SPEC2))
#define SPEC3 (*((volatile unsigned long *)M_SPEC3))
#define DRAM (*((volatile unsigned long *)M_DRAM))
#endif
/* wait-state config registers */
#define SPC_INHIBITMASK (0xf<<24)
#define SPC_INHIBITSHFT 24
#define SPC_EXTGNT (1<<23)
#define SPC_16WIDE (1<<22)
#define SPC_8WIDE (1<<21)
#define SPC_PENA (1<<20)
#define SPC_CACHED (1<<19)
#define SPC_CSDLYMASK (3<<17)
#define SPC_CSDLYSHFT 17
#define SPC_BLKENA (1<<16)
#define SPC_BLKWAITMASK (7<<13)
#define SPC_BLKWAITSHFT 13
#define SPC_RECMASK (63<<7)
#define SPC_RECSHFT 7
#define SPC_WAITENA (1<<6)
#define SPC_WAITMASK (63<<0)
#define SPC_WAITSHFT 0
/* DCR */
#define DRAM_DLP1 (1<<28)
#define DRAM_SYNC (1<<27)
#define DRAM_SCFG (1<<26)
#define DRAM_DMARDY (1<<25)
#define DRAM_DMABLKMASK (7<<22)
#define DRAM_DMABLKSHFT 22
#define DRAM_DPTHMASK (3<<20)
#define DRAM_DPTHSHFT 20
#define DRAM_RDYW (1<<19)
#define DRAM_PGSZMASK (7<<16)
#define DRAM_PGSZSHFT 16
#define DRAM_PGMW (1<<15)
#define DRAM_RFWEMASK (3<<13)
#define DRAM_RFWESHFT 13
#define DRAM_RFEN (1<<12)
#define DRAM_RDYEN (1<<11)
#define DRAM_BFD (1<<10)
#define DRAM_PE (1<<9)
#define DRAM_RPCMASK (3<<7)
#define DRAM_RPCSHFT 7
#define DRAM_RCDMASK (3<<5)
#define DRAM_RCDSHFT 5
#define DRAM_CS (1<<4)
#define DRAM_CLMASK (7<<1)
#define DRAM_CLSHFT 1
#define DRAM_DCE (1<<0)
/* _LR33300_ */
#define _ERNIE_CORE_
#define M_BIU 0xfffe0130
#ifdef LANGUAGE_C
#define BIU (*((volatile unsigned long *)M_BIU))
#define C0_TAR 6 /* target address register */
#define C0_BDAM 9 /* breakpoint data addr mask */
#define C0_BPCM 11 /* breakpoint instr addr mask */
#else
#define C0_TAR $6 /* target address register */
#define C0_BDAM $9 /* breakpoint data addr mask */
#define C0_BPCM $11 /* breakpoint instr addr mask */
#endif
/* cause register */
#define CAUSE_BT (1<<30) /* branch taken */
/* BIU */
#define BIU_NOSTR (1<<17)
#define BIU_LDSCH (1<<16)
#define BIU_BGNT (1<<15)
#define BIU_NOPAD (1<<14)
#define BIU_RDPRI (1<<13)
#define BIU_INTP (1<<12)
#define BIU_IS1 (1<<11)
#define BIU_IS0 (1<<10)
#define BIU_IBLKSZMASK (3<<8)
#define BIU_IBLKSZSHFT 8
#define BIU_IBLKSZ2 (0<<BIU_IBLKSZSHFT)
#define BIU_IBLKSZ4 (1<<BIU_IBLKSZSHFT)
#define BIU_IBLKSZ8 (2<<BIU_IBLKSZSHFT)
#define BIU_IBLKSZ16 (3<<BIU_IBLKSZSHFT)
#define BIU_DS (1<<7)
#define BIU_DS1 (1<<7)
#define BIU_DS0 (1<<6)
#define BIU_DBLKSZMASK (3<<4)
#define BIU_DBLKSZSHFT 4
#define BIU_DBLKSZ2 (0<<BIU_DBLKSZSHFT)
#define BIU_DBLKSZ4 (1<<BIU_DBLKSZSHFT)
#define BIU_DBLKSZ8 (2<<BIU_DBLKSZSHFT)
#define BIU_DBLKSZ16 (3<<BIU_DBLKSZSHFT)
#define BIU_RAM (1<<3)
#define BIU_TAG (1<<2)
#define BIU_INV (1<<1)
#define BIU_LOCK (1<<0)
/* _ERNIE_CORE_ */
/* Definitions for cache sizes */
#define LR33300_IC_SIZE 0x1000 /* 33300 Inst cache = 4Kbytes */
#define LR33300_DC_SIZE 0x800 /* 33300 Data cache = 2Kbytes */

148
c/src/lib/libbsp/mips/genmongoosev/start/regs.h
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@@ -1,148 +0,0 @@
/*
* regs.S -- standard MIPS register names from
* newlib-1.8.2/libgloss/mips and adapted.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* Standard MIPS register names: */
#define zero $0
#define z0 $0
#define v0 $2
#define v1 $3
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24
#define t9 $25
#define k0 $26 /* kernel private register 0 */
#define k1 $27 /* kernel private register 1 */
#define gp $28 /* global data pointer */
#define sp $29 /* stack-pointer */
#define fp $30 /* frame-pointer */
#define ra $31 /* return address */
#define pc $pc /* pc, used on mips16 */
#define fp0 $f0
#define fp1 $f1
#define WATCHDOG 0xBE000000
/* Useful memory constants: */
#define K0BASE 0x80000000
#ifndef __mips64
#define K1BASE 0xA0000000
#else
#define K1BASE 0xFFFFFFFFA0000000LL
#endif
#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE)
/* Standard Co-Processor 0 register numbers: */
#define C0_DCIC $7 /* debug & cache invalidate control */
#define C0_COUNT $9 /* Count Register */
#define C0_SR $12 /* Status Register */
#define C0_CAUSE $13 /* last exception description */
#define C0_EPC $14 /* Exception error address */
#define C0_CONFIG $16 /* CPU configuration */
/* Standard Status Register bitmasks: */
#define SR_CU0 0x10000000
#define SR_CU1 0x20000000 /* Mark CP1 as usable */
#define SR_FR 0x04000000 /* Enable MIPS III FP registers */
#define SR_BEV 0x00400000 /* Controls location of exception vectors */
#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */
/* defined differently for Mongoose5- we don't use these anymore */
#if UNUSED
#define SR_KX 0x00000080 /* Kernel extended addressing enabled */
#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */
#define SR_UX 0x00000020 /* User extended addressing enabled */
#endif
/* R3000 */
#define SR_ISC 0x00010000 /* Isolate data cache */
/* Standard (R4000) cache operations. Taken from "MIPS R4000
Microprocessor User's Manual" 2nd edition: */
#define CACHE_I (0) /* primary instruction */
#define CACHE_D (1) /* primary data */
#define CACHE_SI (2) /* secondary instruction */
#define CACHE_SD (3) /* secondary data (or combined instruction/data) */
#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
#define INDEX_LOAD_TAG (1)
#define INDEX_STORE_TAG (2)
#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */
#define HIT_INVALIDATE (4)
#define CACHE_FILL (5) /* CACHE_I only */
#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */
#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */
#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */
#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c))
/* Individual cache operations: */
#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
/*> EOF regs.S <*/

909
c/src/lib/libbsp/mips/genmongoosev/start/start.S
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@@ -1,909 +0,0 @@
/*
** start.S -- startup file for Mongoose V BSP based upon crt0.S from
** newlib-1.8.2/libgloss/mips and adapted for RTEMS.
**
** crt0.S -- startup file for MIPS.
**
** Copyright (c) 1995, 1996, 1997 Cygnus Support
**
** The authors hereby grant permission to use, copy, modify, distribute,
** and license this software and its documentation for any purpose, provided
** that existing copyright notices are retained in all copies and that this
** notice is included verbatim in any distributions. No written agreement,
** license, or royalty fee is required for any of the authorized uses.
** Modifications to this software may be copyrighted by their authors
** and need not follow the licensing terms described here, provided that
** the new terms are clearly indicated on the first page of each file where
** they apply.
**
**
** Modification History:
** 01/XX/01 Joel Sherrill, OAR Corp,
** Modified for Mongoose V BSP for NASA/GSFC Code 582.
**
** 06/XX/01 Greg Menke, Raytheon, Code 582
** Debug modifications. Removed R4000 dependencies.
** Added HACKED_PMON defines to facilitate startup.
** Added DEFAULT_EXIT_RETURN_TO_MONITOR option.
**
** 11/14/01 A.Ferrer, NASA/GSFC, Code 582
** Cleanup for ST5 mission.
**
** 11/27/01 A.Ferrer, NASA/GSFC, Code 582
** Added cache flush routines.
*/
#ifndef LANGUAGE_ASSEMBLY
#define LANGUAGE_ASSEMBLY
#endif
#include <rtems/asm.h>
#include <bsp/regs.h>
#include "mg5.h"
#ifdef __mips16
/* This file contains 32 bit assembly code. */
.set nomips16
#endif
/*
** defined by linkcmds, pointing to the start of the relocation target
** memory, referenced in this way so we can avoid defining it
** multiply
*/
.bss
.word 0
.text
.align 2
/**********************************************************************
**
** Function: _start
*/
/* Without the following nop, GDB thinks _start is a data variable.
** This is probably a bug in GDB in handling a symbol that is at the
** start of the .text section.
*/
nop
.globl _start
.ent _start
.globl putch_rom
_start:
.set noreorder
$LF1 = . + 8
/*
** Get the address of start into $5 in a position independent fashion.
** This lets us know whether we have been relocated or not.
*/
bal $LF1
nop
_branch:
move a1, ra /* save return address from the jump above */
/* ensure we're sane before doing anything */
li t0, SR_CU0|SR_PE
mtc0 t0, C0_SR
nop
li t0, 0
mtc0 t0, C0_DCIC
nop
mtc0 t0, C0_CAUSE
nop
/*
** Call cpuinit. Masking used to call EEPROM address of _cpuinit. Label is RAM label.
*/
move t2,a1
and t2,0xffff0000
la t0,_cpuinit
and t0,0x0000ffff
or t0,t2
jal t0
nop
/*
** Configure UART
*/
move t2,a1
and t2,0xffff0000
la t0,config_uart
and t0,0x0000ffff
or t0,t2
jal t0
nop
/*
** Print 'b'. Show that we started.
*/
move t2,a1
and t2,0xffff0000
li a0,'b'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
li k0,0
li k1,0
move t1,a1
nop
li t2,0xa0000000 /* lower limit of kseg1 */
li t3,0xbfffffff /* upper limit of kseg1 */
subu t0,t1,t2
srl t0,31 /* shift high bit down to bit 0 */
bnez t0,1f /* booting from below kseg1 */
subu t0,t3,t1
srl t0,31 /* shift high bit down to bit 0 */
bnez t0,1f /* booting from above kseg1 */
/*
** Call IcacheFlush. Masking used to call EEPROM address of IcacheFlush. Label is RAM label.
*/
move t2,a1
and t2,0xffff0000
la t0,IcacheFlush
and t0,0x0000ffff
or t0,t2
move k0,t0 /* save cache flush in-prom address */
jal t0
nop
/*
** Print 'I'. Show that we flushed I cache.
*/
move t2,a1
and t2,0xffff0000
li a0,'I'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
/*
** Call DcacheFlush. Masking used to call EEPROM address of DcacheFlush. Label is RAM label.
*/
move t2,a1
and t2,0xffff0000
la t0,DcacheFlush
and t0,0x0000ffff
or t0,t2
jal t0
nop
/*
** Print 'D'. Show that we flushed D cache.
*/
move t2,a1
and t2,0xffff0000
li a0,'D'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
move k1,t0 /* save cache flush in-prom address */
jal t0
nop
1:
/*
** Print ' RTEMS b'. Show that we are booting.
*/
move t2,a1
and t2,0xffff0000
li a0,' '
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
move t2,a1
and t2,0xffff0000
li a0,'R'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
move t2,a1
and t2,0xffff0000
li a0,'T'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
move t2,a1
and t2,0xffff0000
li a0,'E'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
move t2,a1
and t2,0xffff0000
li a0,'M'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
move t2,a1
and t2,0xffff0000
li a0,'S'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
move t2,a1
and t2,0xffff0000
li a0,' '
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
move t2,a1
and t2,0xffff0000
li a0,'b'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
/*
** get the address of the _branch label above as it would appear in
** the relocated code
*/
la a2, _branch /* relocation destination */
beq a1, a2, _start_in_ram /* skip relocating if we're already there */
nop
/* relocate the code from EEPROM to RAM */
/*
** Print 'r'
*/
move t2,a1
and t2,0xffff0000
li a0,'r'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
la a3, _edata
relocate:
lw t0, (a1) /* load from EEPROM */
addu a1, 4
sw t0, (a2) /* store to RAM */
addu a2, 4
bne a2, a3, relocate /* copied all the way to edata? */
nop
/*
** Print 'R'
*/
li a0,'R'
la t0,putch_rom
and t0,0x0000ffff
or t0,t2
jal t0
nop
la a2, _start_in_ram
jr a2
nop
.end _start
/**********************************************************************
**
** Function: _start_in_ram
*/
.globl _start_in_ram
.ent _start_in_ram
_start_in_ram:
/*
** Print 'S'. Already in RAM no need to reference EEPROM address.
*/
li a0,'S'
jal putch_rom
nop
la gp, _gp /* set the global data pointer */
.end _start_in_ram
/**********************************************************************
**
** Function: zerobss
*/
.globl zerobss
.ent zerobss
zerobss:
/*
** Print 'z'. Starting to zero out bss.
*/
li a0,'z'
jal putch_rom
nop
la v0, _fbss
la v1, _end
3:
sw zero,0(v0)
bltu v0,v1,3b
addiu v0,v0,4 /* executed in delay slot */
la t0, _stack_init /* initialize stack so we */
/*
** We must subtract 24 bytes for the 3 8 byte arguments to main, in
** case main wants to write them back to the stack. The caller is
** supposed to allocate stack space for parameters in registers in
** the old MIPS ABIs. We must do this even though we aren't passing
** arguments, because main might be declared to have them.
**
** Some ports need a larger alignment for the stack, so we subtract
** 32, which satisifes the stack for the arguments and keeps the
** stack pointer better aligned.
*/
subu t0,t0,32
move sp,t0 /* set stack pointer */
nop
/*
** Print 'Z'. Finished zeroing bss.
*/
li a0,'Z'
jal putch_rom
nop
.end zerobss
/**********************************************************************
**
** Function: _init
*/
.globl exit .text
.globl _initialize_rtems
.ent _initialize_rtems
_initialize_rtems:
/*
** Print 'i'. Starting to initialize RTEMS.
*/
li a0, 'i'
jal putch_rom
nop
/*
** Save the boot-time addresses of the I & D cache flush routines.
** Note, if we're running from RAM, we cannot manipulate the cache
** so we just disable the cache flush functions.
*/
la a0,_promIcache
sw k0,0(a0)
nop
la a0,_promDcache
sw k1,0(a0)
nop
move a0,zero /* set command line to 0 */
jal boot_card /* call the program start function */
nop
/*
** fall through to the "exit" routine
*/
jal _sys_exit
nop
.end _initialize_rtems
/**********************************************************************
**
** Function: _sys_exit
**
** Exit from the application by jumping to PMON address in EEPROM.
*/
.globl _sys_exit
.ent _sys_exit
_sys_exit:
la t0, PMON_ADDRESS
jal t0
.end _sys_exit
/**********************************************************************
**
** function: putch
** input : ASCII character in A0
** registers used: ra, a0, t0, t1
**
*/
.globl putch_rom
.ent putch_rom
putch_rom:
/*
** Delay for UART
*/
li t0, 1000
move t1, zero
2:
beq t0, t1, 3f
addu t1, 1
b 2b
nop
3:
/*
** Print a character out from a0
*/
li t0, MG5_INT_STATUS_REG /* load uart register base address */
lw t1, 0(t0) /* Read status */
nop
and t1, t1, UART_0_TX_READY_BIT /* see if the transmitter is ready */
beq t1 , zero , 1f /* skip uart output if not ready */
nop
la t0, MG5_UART_0_TX_REG
sw a0, 0(t0)
nop
1: /*
** if jumped to here, UART was not ready...forget it
*/
j ra
.end putch_rom
/**********************************************************************
**
** function: config_uart
** registers used: ra, t0, t1
**
*/
.globl config_uart
.ent config_uart
config_uart:
/*
** Configure UART 0
*/
/* First, reset the uart */
la t0, MG5_COMMAND_REG
li t1, UART_RESET_BIT
sw t1, 0(t0)
/* Next, set the baud rate register for 19200 with a clock speed of 12 Mhz*/
la t0, MG5_UART_0_BAUD_REG
li t1, 0x02700270
sw t1, 0(t0)
/* Now, clear the reset bit & set the tx enable bit */
la t0, MG5_COMMAND_REG
li t1, UART_0_TX_ENABLE_BIT
sw t1, 0(t0)
/*
** return
*/
j ra
.end config_uart
/*************************************************************
* CpuInit:
* Perform CPU-specific initialization
* This routine is only callable from assembly because it
* clobbers s7. It should be called from your ROM-based startup
* code. It returns:
* s0 = address of cache flush routine
*/
.globl _cpuinit
.ent _cpuinit
_cpuinit:
/*
** BIU/Cache config register setup
**
** RES = 0: 31 -> 18 : Reserved
** RES = 1: 17 : Reserved must be set to 1 (Synova Manual)
** RES = 0: 16 : Reserved must be set to 0 (Synova Manual)
** BGNT = 0: 15 : Disable Bus Grant (set to 0)
** NOPAD = 1: 14 : No padding of waitstates between transactions
** RDPRI = 1: 13 : Loads have priority over stores
** INTP = 1: 12 : Interrupts are active high
** IS1 = 1: 11 : Enable I-Cache
** IS0 = 0: 10 : Hardwired to zero
** IBLKSZ =10: 9 -> 8 : I-Cache refill size = 8 words
** DS = 1: 7 : Enable D-Cache
** RES = 0: 6 : Hardwared to zero
** DBLKSZ =10: 5 -> 4 : D-Cache refill block size 8 words
** RAM = 0: 3 : No Scratchpad RAM
** TAG = 0: 2 : Disable tag test
** INV = 0: 1 : Disable invalidate mode
** LOCK = 0: 0 : Disable cache lock
**
** 0x00027AA0 caches on
** 0x00027220 caches off
*/
li t0,0x00027aa0
sw t0,M_BIU
/*
** Refresh register setup
**
** set 94 clock cycles at 12Mhz
*/
li t1,M_RTIC
li t0,0x5E
sw t0,(t1)
/*
** DRAM register setup
**
**
** RESERVED=0: 31 -> 29 : Reserved
** SYNC = 0 : 27 : No Syncronous DRAM
** SCFG = 0 : 26 : No Syncronous DRAM
** DMARDY =1 : 25 : Internal DRDY for DMA
** DMABLK =0 : 24 -> 22 : 2 word blk size for DMA transfers
** DPTH = 0 : 21 -> 20 : No interleaved or syncronous memory
** RDYW = 0 : 19 : No interleaved or syncronous memory
** PGSZ = 110: 18 -> 16 : Page size = 1K
** PGMW = 0 : 15 : Disable page mode write
** RFWE = 0 : 14 -> 13 : Allow BIU to do non-DRAM work during refresh
** RFEN = 1 : 12 : Enable Refresh generator
** RDYEN = 1 : 11 : Internal DRDY
** BFD = 1 : 10 : Block fetch disable
** PE = 0 : 9 : No parity checking
** RPC = 0 : 8 -> 7 : RAS Precharge = 2 SYSCLK cycles
** RCD = 1 : 6 -> 5 : RAS-to-CAS delay = 3 cycles
** CS = 0 : 4 : CAS shortened by 1/2 cycle
** CL = 1 : 3 -> 1 : 2.5 cycle CAS pulse width
** DCE = 1 : 0 : Enable DRAM controller
*/
li s0,0x02061C23
sw s0,M_DRAM
/*
** SRAM setup
** Dont Care about this, we are not using SRAM
** Power on default of 0x0 is ok
*/
li t0,0
sw t0,M_SRAM
/*
** SPEC0 setup
**
** SPEC0 contains the BCRT registers, BCRT Shared RAM and EEPROM
** This area is configured to use an external waitstate generator
** and Data Ready signal.
** Also, I see no need to cache this data. It could confuse the
** BCRT.
**
** - 9/29/99 - APC - set NOSNOOP to 1 and EXTGNT to 1
** Bit 23 = 1 : EXTGNT External data ready = 1
** Bit 19 = 1 : NOSNOOP No Snoop = 1
*/
li t0,0x00880000 # use external waitstates
sw t0,M_SPEC0
/*
** SPEC1 setup
**
** This is where most of the SDB I/O is.
**
** Important fields:
**
** Bit 19 =1 : NOSNOOP = 1
** Bit 6 = 1 : Enable DAWG
** Bit 5 -> 0 = 1 : 1 Wait state
*/
li t0,0x00880000 /* Bit23 EXTGNT set to 1, Bit19 NOSNOOP set to 1 */
sw t0,M_SPEC1
/*
** SPEC2 setup
**
** SPEC2 is not currently used on the SDB.
** Bit 19 = 1 : NOSNOOP = 1
**
**li t0, 0x00080000
**sw t0,M_SPEC2
*/
li t0, 0x0
sw t0,M_SPEC2
/*
** SPEC3 Setup
** SPEC3 will be used for the SONIC ethernet controller.
** Use the same ** of waitstates that the turborocket board uses.
** Bit 19 = 1 : NOSNOOP = 1
**
**li t0, (SPC_CACHED | SPC_WAITENA | (16<<SPC_WAITSHFT))
**sw t0,M_SPEC3
*/
li t0, 0x0
sw t0,M_SPEC3
/*
** Finally, delay to allow RAM to stabilize
*/
li t0,2000
1: subu t0,1
bne t0,zero,1b
nop
/*
** Init Mongoose V registers.
*/
/*
** Mongoose V Control Register Setup
** For now just setup UART defaults, turn edac off.
** May not even need to put anything in here...
*/
li t0,0
sw t0,MG5_COMMAND_REG
/*
** Setup Mongoose V extended interrupt mask
*/
li t0,0
sw t0,MG5_INT_MASK_REG
/*
** Clear Mongoose V extended interrupts
** Clear all of the pulse interrupts that may be pending.
*/
li t0,( EDAC_SERR_BIT | EDAC_MERR_BIT | UART_0_RX_OVERRUN_BIT | UART_0_FRAME_ERR_BIT | UART_1_RX_OVERRUN_BIT | UART_1_FRAME_ERR_BIT | MAVN_WRITE_ACC_BIT | MAVN_READ_ACC_BIT )
sw t0,MG5_INT_STATUS_REG
/*
** Setup MAVN Access Priv Register
*/
li t0,0x7FFFFFFF /* Default reset value */
sw t0,MG5_MAVN_PRIVLEGE_REG
/*
** Mavn Range Register 0 -- 0 and 1 cover EEPROM
** 0xbfc00000 -> 0xbfe00000
*/
li t0,( 0xBFC00000 | 0x15 )
sw t0,MG5_MAVN_RANGE_0_REG
/*
** Mavn Range Register 1
** 0xbfe00000 -> 0xc0000000
*/
li t0,( 0xBFE00000 | 0x15 )
sw t0,MG5_MAVN_RANGE_1_REG
/*
** Mavn Range Register 2 -- 2 and 3 cover the first RAM
** 0x80000000 -> 0x80200000
*/
li t0,( 0x80000000 | 0x15 )
sw t0,MG5_MAVN_RANGE_2_REG
/*
** Mavn Range Register 3
** 0x80200000 -> 0x80400000
*/
li t0, ( 0x80200000 | 0x15 )
sw t0, MG5_MAVN_RANGE_3_REG
/*
** Mavn Range Register 4 -- IO Space 1
** 0xBE00000 -> 0xBe0000200
*/
li t0, ( 0xBe000000 | 0x09 )
sw t0, MG5_MAVN_RANGE_4_REG
/*
** Mavn Range Register 5 -- IO Space 2
** 0xBe200000 -> 0xbe400000
*/
li t0, ( 0xBE200000 | 0x15 )
sw t0, MG5_MAVN_RANGE_5_REG
/*
** MAVN Error Address Register ( Unstick )
*/
la t0, MG5_MAVN_VIOLATION_REG
lw t1, 0(t0)
/*
** Read EDAC Error Register to unstick it
*/
la t0, MG5_EDAC_ADDR_REG
lw t1, 0(t0)
/*
** Enable Mongoose V EDAC
*/
la t0, MG5_COMMAND_REG
li t1, EDAC_ENABLE_BIT
sw t1, 0(t0)
nop
/*
** Program Watchdog to 10 seconds - If PMON will
** run, it will be set to MAX later.
*/
la t0, 0xBE000000
li t1, 0xA0
sw t1, 0(t0)
3: nop
j ra
.end _cpuinit
/**********************************************************************
**
** Keep the boot-time address of the I & D cache reset code for
** later on. If we need to clear the I/D caches, we <must> run from
** non-cached memory. This means the relocated versions are useless,
** thankfully they are quite small.
*/
_promIcache: .word 0
_promDcache: .word 0
.globl promCopyIcacheFlush
.ent promCopyIcacheFlush
.set noreorder
promCopyIcacheFlush:
move a0,ra
la t1,_promIcache
lw t0,0(t1)
nop
beqz t0,1f
jal t0
nop
1: j a0
nop
.set reorder
.end promCopyIcacheFlush
.globl promCopyDcacheFlush
.ent promCopyDcacheFlush
.set noreorder
promCopyDcacheFlush:
move a0,ra
la t1,_promDcache
lw t0,0(t1)
nop
beqz t0,1f
jal t0
nop
1: j a0
nop
.set reorder
.end promCopyDcacheFlush
/*******************************************************************************
** Function Name: IcacheFlush
** Description: This functions flushes the on chip icache.
*/
.ent IcacheFlush
.set noreorder
IcacheFlush:
1:
/*
** Assume I cache is already enabled in BIU/Cache setup
** Get contents of M_BIU register and save in t1
*/
li t0, M_BIU
lw t1, 0(t0)
/*
** Isolate I cache
*/
mfc0 t3, C0_SR /* Read Status Register */
nop
or t0, t3, SR_ISC /* Isolate Cache so we don't propagate operations */
mtc0 t0, C0_SR /* Write it back to Status Register */
nop
/*
** Setup for cache flush
*/
li t8, 0 /* Store zero */
li t9, LR33300_IC_SIZE
icache_write:
sw zero, 0(t8) /* Store zero to memory addres in t8 */
addu t8, 4 /* Increment t8 address by 4 */
bltu t8, t9, icache_write /* check to see if we are done */
nop
/*
** De-isolate I cache
*/
mtc0 t3, C0_SR /* Load unchanged t3 to Status Register */
nop
jal ra
nop
.set reorder
.end IcacheFlush
/********************************************************
** Function Name: DcacheFlush
** Description: This functions flushes the on chip dcache.
*/
.ent DcacheFlush
.set noreorder
DcacheFlush:
/*
** isolate icache
*/
mfc0 t3,C0_SR
nop
or t0, t3, SR_ISC
mtc0 t0, C0_SR
nop
/*
** Setup up for cache flush
*/
li t8, 0
li t9, LR33300_DC_SIZE
dcache_write:
sw zero, 0(t8)
addu t8, 4
bltu t8, t9, dcache_write /* check to see if we are done */
nop
/*
** De-isolate cache
*/
mtc0 t3, C0_SR
nop
jal ra
nop
.set reorder
.end DcacheFlush
/* EOF start.S */

97
c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c
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@@ -1,97 +0,0 @@
/**
* @file
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*
* Modification History:
* 12/10/01 A.Ferrer, NASA/GSFC, Code 582
* Set interrupt mask to 0xAF00 (Line 139).
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <string.h>
#include <bsp.h>
#include <bsp/mongoose-v.h>
#include <libcpu/isr_entries.h>
#include <bsp/irq-generic.h>
void bsp_start( void );
void clear_cache( void );
extern void _sys_exit(int);
extern void mips_gdb_stub_install(void);
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
/* mask off any interrupts */
MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 );
/* reset the config register & clear any pending peripheral interrupts */
MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 );
MONGOOSEV_WRITE(
MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, MONGOOSEV_UART_CMD_RESET_BOTH_PORTS );
MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 );
/* reset both timers */
MONGOOSEV_WRITE_REGISTER(
MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff);
MONGOOSEV_WRITE_REGISTER(
MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
MONGOOSEV_WRITE_REGISTER(
MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff);
MONGOOSEV_WRITE_REGISTER(
MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
/* clear any pending interrupts */
MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, 0xffffffff );
/* clear any writable bits in the cause register */
mips_set_cause( 0 );
/* set interrupt mask, but globally off. */
/*
* Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
* periph | unused | FPU | unused | timer2 | timer1 | swint1 | swint2 |
* extern | | | | | | | |
*
* 1 0 1 0 0 1 0 0
*
* 0x8C00 Enable only internal Mongoose V timers.
* 0xA400 Enable Peripherial ints, FPU and timer1
* 0x0400 Timer1 only
*/
/* mips_set_sr( (SR_CU0 | SR_CU1 | 0xA400) ); */
/* to start up, only enable coprocessor 0 & timer int. per-task
* processor settings will be applied as they are created, this
* is just to configure the processor for startup
*/
mips_set_sr( (SR_CU0 | 0x400) );
bsp_interrupt_initialize();
}
void clear_cache( void )
{
promCopyIcacheFlush();
promCopyDcacheFlush();
}

145
c/src/lib/libbsp/mips/genmongoosev/startup/gdb-support.c
View File

@@ -1,145 +0,0 @@
/*
* GDB Support Routines for the Mongoose-V
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <rtems/bspIo.h>
#include <bsp/mongoose-v.h>
#include "gdb_if.h"
#include <rtems/libio.h>
#include <stdio.h>
#include <string.h>
/*
We're going to call right down into the uart driver because we're
operating within an exception. if things are broken because something
bad happened, this may be our last chance to debug before RTEMS goes
mad, so we won't rely on the I/O subsystem to be operating. This is a
little messy, but at least we're not talking right to the hardware.
*/
extern int mg5uart_set_attributes(int minor,const struct termios *t);
extern int mg5uart_open(int major,int minor, void *arg);
extern int mg5uart_close(int major,int minor, void *arg);
extern void mg5uart_write_polled(int minor, char c );
extern int mg5uart_inbyte_nonblocking_polled(int minor);
/*
* Prototypes for methods assumed to exist by the gdb stub
*/
char getDebugChar (void);
void putDebugChar (char c);
static int debugUartEnabled = 0;
int mg5rdbgOpenGDBuart(int breakoninit)
{
struct termios t;
memset(&t,0,sizeof(struct termios));
if( mg5uart_open(0,1,NULL) != RTEMS_SUCCESSFUL )
{
printf("gdbstub: Failed to open UART port 2\n");
return -1;
}
t.c_cflag |= B19200;
t.c_cflag |= CS8;
if( mg5uart_set_attributes(1,&t) != 0 )
{
printf("gdbstub: Failed to configure UART 2 for 19200N82\n");
return -1;
}
printf("gdbstub: UART 2 configured for 19200N82\n");
debugUartEnabled = -1;
/* set up vectoring for gdb */
mips_gdb_stub_install(-1);
/*
this is a rough approximation of our memory map. Yours is
probably different. It only needs to be sufficient for the stub
to know what it can and can't do and where.
*/
gdbstub_add_memsegment(0 , 0x8001ffff, MEMOPT_READABLE );
gdbstub_add_memsegment(0x80020000, 0x80afffff, MEMOPT_READABLE | MEMOPT_WRITEABLE );
gdbstub_add_memsegment(0x80b00000, 0x814fffff, MEMOPT_READABLE );
gdbstub_add_memsegment(0x81500000, 0x81ffffff, MEMOPT_READABLE | MEMOPT_WRITEABLE );
if( breakoninit )
{
printf("gdbstub: GDB stub entered, connect host debugger now\n");
/*
break to gdb. We'll wait there for the operator to get their gdb
going, then they can 'continue' or do whatever.
*/
mips_break(0);
printf("gdbstub: User code running\n");
}
else
printf("gdbstub: GDB stub ready for exceptions\n");
return RTEMS_SUCCESSFUL;
}
void mg5rdbgCloseGDBuart(void)
{
mg5uart_close(0,1,NULL);
debugUartEnabled = 0;
}
char getDebugChar (void)
{
if( debugUartEnabled )
{
int rv;
while( (rv = mg5uart_inbyte_nonblocking_polled(1)) < 0 );
return (char)rv;
}
return 0;
}
void putDebugChar (char c)
{
if( debugUartEnabled )
return mg5uart_write_polled(1,c);
}
/*
{
* initialize hardware pc and data breakpoints to quiet state*
uint32_t dcic, reg, mask;
reg = 0xffffffff;
mask = 0xffffffff;
mips_set_bpcrm( reg, mask );
mips_set_bdarm( reg, mask );
mips_get_dcic( dcic );
* configure dcic for trapping, user & kernel mode, PC traps and enable it *
dcic = DCIC_TR | DCIC_UD | DCIC_KD | DCIC_PCE | DCIC_DE;
* dcic = DCIC_UD | DCIC_KD | DCIC_PCE | DCIC_DE; *
mips_set_dcic( dcic );
mips_get_bpcrm( reg, mask );
mips_get_dcic( dcic );
* printf("bpc is %08X, bpc_mask is %08X, dcic is now %08X\n", reg, mask, dcic ); *
}
*/

228
c/src/lib/libbsp/mips/genmongoosev/startup/linkcmds
View File

@@ -1,228 +0,0 @@
/*
* Linker script for Mongoose-V prototyping board.
* See README for address map details.
*/
/* . = 0x80020000; */
/*
* Declare some sizes.
*/
RamBase = DEFINED(RamBase) ? RamBase : 0x80000000;
RamSize = DEFINED(RamSize) ? RamSize : 32M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x4000;
ClockRate = DEFINED(ClockRate) ? ClockRate : 12000000;
MEMORY
{
ram : ORIGIN = 0x80020000, LENGTH = 4M
}
SECTIONS
{
.text :
{
_ftext = . ;
*/start.o(.text)
*(.text*)
*(.gnu.linkonce.t*)
*(.mips16.fn.*)
*(.mips16.call.*)
*(.reginfo)
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
*(.rel.dyn)
PROVIDE (__runtime_reloc_stop = .);
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
*(.gcc_except_table*)
*(.eh_frame_hdr)
*(.eh_frame)
} >ram
.init :
{
KEEP(*(.init))
} > ram
.fini :
{
KEEP(*(.fini))
} > ram
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >ram
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
etext = .;
_etext = .;
} >ram
.rdata :
{
*(.rdata)
*(.rodata)
*(.rodata.*)
KEEP (*(SORT(.rtemsroset.*)))
*(.gnu.linkonce.r*)
} >ram
.tdata : {
_TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
_TLS_Data_end = .;
} >ram
.tbss : {
_TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
_TLS_BSS_end = .;
} >ram
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
.data :
{
_fdata = ALIGN(16);
*(.data)
*(.data.*)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gnu.linkonce.d*)
} >ram
.jcr :
{
. = ALIGN(8);
KEEP (*(.jcr))
_gp = ALIGN(16) + 0x7440;
__global = _gp;
} >ram
.lit8 :
{
*(.lit8)
} >ram
.lit4 :
{
*(.lit4)
} >ram
.sdata :
{
*(.sdata*)
*(.gnu.linkonce.s*)
} >ram
.sbss :
{
edata = .;
_edata = .;
_fbss = .;
*(.sbss*)
*(.scommon)
} >ram
.bss :
{
_bss_start = . ;
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (64);
_stack_limit = .;
. += _StackSize;
__stack = .;
_stack_init = .;
_clear_end = .;
WorkAreaBase = .;
end = .;
_end = .;
} >ram
/*
** DWARF debug sections.
** Symbols in the DWARF debugging sections are relative to
** the beginning of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame)}
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

93
c/src/lib/libbsp/mips/genmongoosev/timer/timer.c
View File

@@ -1,93 +0,0 @@
/*
* This file implements a benchmark timer using a MONGOOSE-V timer.
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <assert.h>
#include <bsp.h>
#include <rtems/btimer.h>
bool benchmark_timer_find_average_overhead;
#if defined(USE_TIMER2_FOR_CLOCK)
#define TIMER_BASE MONGOOSEV_TIMER1_BASE
#define TIMER_VECTOR MONGOOSEV_IRQ_TIMER1
#else
#define TIMER_BASE MONGOOSEV_TIMER2_BASE
#define TIMER_VECTOR MONGOOSEV_IRQ_TIMER2
#endif
void benchmark_timer_initialize(void)
{
/*
* Programming the compare register as the maximum value should let
* it run long enough and accurate enough not to require an interrupt.
* but if it ever does generate an interrupt, we will simply fault.
*
* NOTE: This is similar to the clock driver initialization
* with the exception that the divider is disabled and
* the compare register is set to the maximum value.
*/
MONGOOSEV_WRITE_REGISTER( TIMER_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
MONGOOSEV_WRITE_REGISTER( TIMER_BASE,
MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER,
0xffffffff );
MONGOOSEV_WRITE_REGISTER( TIMER_BASE,
MONGOOSEV_TIMER_CONTROL_REGISTER,
MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE );
}
#define AVG_OVERHEAD 0 /* It typically takes N instructions */
/* to start/stop the timer. */
#define LEAST_VALID 1 /* Don't trust a value lower than this */
/* mongoose-v can count cycles. :) */
#include <rtems/bspIo.h>
benchmark_timer_t benchmark_timer_read(void)
{
uint32_t clicks;
uint32_t total;
uint32_t tcr;
clicks = MONGOOSEV_READ_REGISTER( TIMER_BASE,
MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER );
total = 0xffffffff - clicks;
tcr = MONGOOSEV_READ_REGISTER( TIMER_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER );
MONGOOSEV_WRITE_REGISTER( TIMER_BASE,
MONGOOSEV_TIMER_CONTROL_REGISTER,
0 );
if ( tcr & MONGOOSEV_TIMER_CONTROL_TIMEOUT )
printk( "MG5 timer overran\n" );
if ( benchmark_timer_find_average_overhead == true )
return total; /* in cycle units */
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
return (total - AVG_OVERHEAD) / CPU_CLOCK_RATE_MHZ;
}
void benchmark_timer_disable_subtracting_average_overhead(
bool find_flag
)
{
benchmark_timer_find_average_overhead = find_flag;
}
/* eof */