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2007-11-03 Ray Xu <rayx.cn@gmail.com>

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* shared/abort/simple_abort.c: Add veneer for ARM<->Thumb
        shared/irq/irq_asm.S: Add veneer for ARM<->Thumb
This commit is contained in:
Joel Sherrill
2007-11-06 22:50:51 +00:00
parent ac654234d6
commit f28bbe5c6b
3 changed files with 63 additions and 6 deletions
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9
c/src/lib/libbsp/arm/ChangeLog
View File

@@ -1,3 +1,8 @@
2007-11-03 Ray Xu <rayx.cn@gmail.com>
* shared/abort/simple_abort.c: Add veneer for ARM<->Thumb
shared/irq/irq_asm.S: Add veneer for ARM<->Thumb
2007-11-06 Till Straumann <strauman@slac.stanford.edu>
* gba/irq/irq.c: test for non-NULL-ness before calling
@@ -42,11 +47,11 @@
armulator/startup/swi.h, armulator/startup/syscalls.c,
armulator/startup/trap.S: Removed.
2007-05-15 Ray Xu <rayx@gmail.com>
2007-05-15 Ray Xu <rayx.cn@gmail.com>
* shared/abort/abort.c, shared/abort/simple_abort.c: New files.
2007-05-15 Ray Xu <rayx@gmail.com>
2007-05-15 Ray Xu <rayx.cn@gmail.com>
* Makefile.am: Add abort.rel since it is now in the BSP shared source,
not in score/cpu.

11
c/src/lib/libbsp/arm/shared/abort/simple_abort.c
View File

@@ -2,7 +2,7 @@
* ARM CPU Dependent Source
*
* COPYRIGHT (c) 2007 Ray Xu.
* mailto: Rayx at gmail dot com
* mailto: Rayx.cn at gmail dot com
*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
@@ -64,6 +64,15 @@ void _print_full_context(uint32_t spsr)
mode=_print_full_context_mode2txt[(spsr&0x1f)-0x10];
if(!mode) mode="unknown";
#if defined(__thumb__)
asm volatile (" .code 16 \n" \
"adr %[tmp], arm_code \n" \
"bx %[tmp] \n" \
"nop \n" \
".code 32 \n" \
"arm_code: \n" \
: [tmp]"=&r" (tmp) );
#endif
asm volatile (" MRS %[cpsr], cpsr \n"
" ORR %[tmp], %[spsr], #0xc0 \n"
" MSR cpsr_c, %[tmp] \n"

49
c/src/lib/libbsp/arm/shared/irq/irq_asm.S
View File

@@ -21,8 +21,14 @@
#include <rtems/asm.h>
#define __asm__
/*MUST be ARM code*/
/* assume that before interrupt we are in svc mode */
/* fix me: No priority support, interrupt disabled too long in the ISR */
.arm
.globl _ISR_Handler
_ISR_Handler:
.code 32
stmdb sp!, {r0, r1, r2, r3, r12} /* save regs on INT stack */
stmdb sp!, {lr} /* now safe to call C funcs */
@@ -41,7 +47,13 @@ _ISR_Handler:
/* BSP specific function to INT handler */
/* FIXME: I'm not sure why I can't save just r12. I'm also */
/* not sure which of r1-r3 are important. */
#if __thumb__
ldr r0, =ExecuteITHandler +1
mov lr, pc
bx r0
#else
bl ExecuteITHandler
#endif
/* one less nest level */
ldr r0, =_ISR_Nest_level
@@ -107,11 +119,15 @@ bframe:
ldr lr, =_ISR_Dispatch_p_4 /* On entry to an ISR, the lr is */
/* the return address + 4, so */
/* we have to emulate that */
#ifdef __thumb__
sub lr, #0x1
#endif
ldmia sp!, {r1} /* out with the old */
stmdb sp!, {lr} /* in with the new (lr) */
#ifndef __thumb__
orr r0, r0, #0xc0
msr spsr, r0
msr spsr_cf, r0 /* mask interrupt */
#endif
exitit:
ldmia sp!, {lr} /* restore regs from INT stack */
@@ -121,15 +137,41 @@ exitit:
/* on entry to _ISR_Dispatch, we're in SVC mode */
.globl _ISR_Dispatch
_ISR_Dispatch:
#ifdef __thumb__
/* will be called from ISR, with SPSR in T mode */
/* ISR will enter from here */
.code 16
.thumb_func
push {r0-r3,lr} /* save regs on SVC stack */
/* (now safe to call C funcs) */
/* we don't save lr, since */
/* it's just going to get */
/* overwritten */
#else
.code 32
stmdb sp!, {r0-r3, r12,lr} /* save regs on SVC stack */
/* (now safe to call C funcs) */
/* we don't save lr, since */
/* it's just going to get */
/* overwritten */
#endif
nop /*made _ISR_Dispatch_p_4 4-word align */
_ISR_Dispatch_p_4:
bl _Thread_Dispatch
ldmia sp!, {r0-r3, r12, lr}
#ifdef __thumb__
ldr r0, = .Thread_Disp_T
bx r0
.pool
.code 32
.Thread_Disp_T:
#endif
#ifdef __thumb__
ldmia sp!, {r0-r3, lr} /*r12 not saved in thumb mode*/
#else
ldmia sp!, {r0-r3, r12, lr}
#endif
stmdb sp!, {r0-r2}
/* Now we have to screw with the stack */
mov r0, sp /* copy the SVC stack pointer */
@@ -160,3 +202,4 @@ _ISR_Dispatch_p_4:
/* Finally, we can return to the interrupted task */
subs pc, lr, #4