forked from Imagelibrary/rtems
new file for MIPS port by Craig Lebakken (lebakken@minn.net) and
Derrick Ostertag (ostertag@transition.com).
This commit is contained in:
Joel Sherrill
298
c/src/lib/start/mips64orion/idt_csu.S
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298
c/src/lib/start/mips64orion/idt_csu.S
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@@ -0,0 +1,298 @@
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/*
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Based upon IDT provided code with the following release:
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This source code has been made available to you by IDT on an AS-IS
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basis. Anyone receiving this source is licensed under IDT copyrights
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to use it in any way he or she deems fit, including copying it,
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modifying it, compiling it, and redistributing it either with or
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without modifications. No license under IDT patents or patent
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applications is to be implied by the copyright license.
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Any user of this software should understand that IDT cannot provide
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technical support for this software and will not be responsible for
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any consequences resulting from the use of this software.
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Any person who transfers this source code or any derivative work must
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include the IDT copyright notice, this paragraph, and the preceeding
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two paragraphs in the transferred software.
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COPYRIGHT IDT CORPORATION 1996
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LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
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*/
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/*************************************************************************
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**
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** Copyright 1991-95 Integrated Device Technology, Inc.
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** All Rights Reserved
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**
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** idt_csu.S -- IDT stand alone startup code
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**
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**************************************************************************/
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#include <rtems/score/iregdef.h>
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#include <rtems/score/idtcpu.h>
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#include <rtems/score/idtmon.h>
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.extern _fbss,4 /* this is defined by the linker */
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.extern end,4 /* this is defined by the linker */
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.lcomm sim_mem_cfg_struct,12
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.text
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#define TMP_STKSIZE 1024
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/**************************************************************************
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**
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** start - Typicl standalone start up code required for R3000/R4000
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**
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**
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** 1) Initialize the STATUS Register
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** a) Clear parity error bit
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** b) Set co_processor 1 usable bit ON
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** c) Clear all IntMask Enables
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** d) Set kernel/disabled mode
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** 2) Initialize Cause Register
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** a) clear software interrupt bits
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** 3) Determine FPU installed or not
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** if not, clear CoProcessor 1 usable bit
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** 4) Clear bss area
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** 5) MUST allocate temporary stack until memory size determined
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** It MUST be uncached to prevent overwriting when caches are cleared
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** 6) Install exception handlers
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** 7) Determine memory and cache sizes
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** 8) Establish permanent stack (cached or uncached as defined by bss)
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** 9) Flush Instruction and Data caches
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** 10) If there is a Translation Lookaside Buffer, Clear the TLB
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** 11) Execute initialization code if the IDT/c library is to be used
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**
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** 12) Jump to user's "main()"
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** 13) Jump to promexit
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**
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** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
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** This is used to mark code specific to R3xxx or R4xxx processors.
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** IDT/C 6.x defines __mips to be the ISA level for which we're
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** generating code. This is used to make sure the stack etc. is
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** double word aligned, when using -mips3 (default) or -mips2,
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** when compiling with IDT/C6.x
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**
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***************************************************************************/
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FRAME(start,sp,0,ra)
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.set noreorder
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#ifdef _R3000
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li v0,SR_PE|SR_CU1 /* reset parity error and set */
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/* cp1 usable */
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#endif
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#ifdef _R4000
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#if __mips==3 || defined(R4650)
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li v0,SR_CU1|SR_DE|SR_FR /* initally clear ERL, enable FPA 64bit regs*/
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/* 4650: Need fr to be set anyway */
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#else
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li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPA 32bit regs*/
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#endif mips3
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#endif
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mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */
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nop
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mtc0 zero,C0_CAUSE /* clear software interrupts */
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nop
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#ifdef _R4000
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li v0,CFG_C_NONCOHERENT # initialise default cache mode
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mtc0 v0,C0_CONFIG
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#endif
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/*
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** check to see if an fpu is really plugged in
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*/
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li t3,0xaaaa5555 /* put a's and 5's in t3 */
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mtc1 t3,fp0 /* try to write them into fp0 */
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mtc1 zero,fp1 /* try to write zero in fp */
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mfc1 t0,fp0
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mfc1 t1,fp1
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nop
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bne t0,t3,1f /* branch if no match */
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nop
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bne t1,zero,1f /* double check for positive id */
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nop
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/* We have a FPU. clear fcsr */
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ctc1 zero, fcr31
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j 2f /* status register already correct */
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nop
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1:
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#ifdef _R3000
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li v0, SR_PE /* reset parity error/NO cp1 usable */
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#endif
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#ifdef _R4000
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li v0,SR_DE /* clear ERL and disable FPA */
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#endif
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mtc0 v0, C0_SR /* reset status register */
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2:
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la gp, _gp
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la v0,_fbss /* clear bss before using it */
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la v1,end /* end of bss */
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3: sw zero,0(v0)
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bltu v0,v1,3b
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add v0,4
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/************************************************************************
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**
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** Temporary Stack - needed to handle stack saves until
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** memory size is determined and permanent stack set
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**
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** MUST be uncached to avoid confusion at cache
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** switching during memory sizing
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**
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*************************************************************************/
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#if __mips==3
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/* For MIPS 3, we need to be sure that the stack is aligned on a
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* double word boundary.
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*/
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andi t0, v0, 0x7
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beqz t0, 11f /* Last three bits Zero, already aligned */
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nop
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add v0, 4
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11:
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#endif
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or v0, K1BASE /* switch to uncached */
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add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
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sub v1, v1, (4*4) /* overhead */
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move sp, v1 /* set sp to top of stack */
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4: sw zero, 0(v0)
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bltu v0, v1, 4b /* clear out temp stack */
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add v0, 4
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jal init_exc_vecs /* install exception handlers */
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nop /* MUST do before memory probes */
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la v0, 5f
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li v1, K1BASE /* force into uncached space */
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or v0, v1 /* during memory/cache probes */
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j v0
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nop
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5:
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la a0, sim_mem_cfg_struct
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jal sim_mem_cfg /* Make SIM call to get mem size */
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nop
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la a0, sim_mem_cfg_struct
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lw a0, 0(a0) /* Get memory size from struct */
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#ifdef _R3000
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jal config_Icache
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nop
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jal config_Dcache /* determine size of D & I caches */
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nop
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#endif
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#ifdef _R4000
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jal config_cache /* determine size of D & I caches */
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nop
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#endif
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move v0, a0 /* mem_size */
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#if __mips==3
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/* For MIPS 3, we need to be sure that the stack (and hence v0
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* here) is aligned on a double word boundary.
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*/
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andi t0, v0, 0x7
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beqz t0, 12f /* Last three bits Zero, already aligned */
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nop
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subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/
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12:
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#endif
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/**************************************************************************
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**
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** Permanent Stack - now know top of memory, put permanent stack there
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**
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***************************************************************************/
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la t2, _fbss /* cache mode as linked */
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and t2, 0xF0000000 /* isolate segment */
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la t1, 6f
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j t1 /* back to original cache mode */
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nop
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6:
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or v0, t2 /* stack back to original cache mode */
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addiu v0,v0,-16 /* overhead */
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move sp, v0 /* now replace count w top of memory */
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move v1, v0
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subu v1, P_STACKSIZE /* clear requested stack size */
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7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
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bltu v1,v0,7b
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add v1, 4
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.set reorder
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#ifdef _R3000
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jal flush_Icache
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jal flush_Dcache /* flush Data & Instruction caches */
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#endif
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#ifdef _R4000
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jal flush_cache_nowrite /* flush Data & Instruction caches */
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#endif
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/**************************************************************************
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**
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** If this chip supports a Translation Lookaside Buffer, clear it
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**
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***************************************************************************/
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.set noreorder
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mfc0 t1, C0_SR /* look at Status Register */
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nop
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.set reorder
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#ifdef _R3000
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li t2, SR_TS /* TLB Shutdown bit */
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and t1,t2 /* TLB Shutdown if 1 */
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bnez t1, 8f /* skip clearing if no TLB */
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#endif
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#ifndef R4650
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jal init_tlb /* clear the tlb */
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#endif
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/************************************************************************
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**
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** Initialization required if using IDT/c or libc.a, standard C Lib
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**
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** can SKIP if not necessary for application
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**
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************************************************************************/
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8:
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jal idtsim_init_sbrk
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jal idtsim_init_file
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/*********************** END I/O initialization **********************/
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jal main
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jal idtsim_promexit
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ENDFRAME(start)
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.globl sim_mem_cfg
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sim_mem_cfg:
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.set noat
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.set noreorder
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li AT, (0xbfc00000+((55)*8))
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jr AT
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nop
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.set at
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.set reorder
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